Semiconductor packaging structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor packaging structure and a manufacturing method thereof, and belongs to the technical field of semiconductor packaging. The semiconductor packaging structure comprises a lead frame, a semiconductor chip and a plurality of connecting columns, the connecting columns are arranged on the surface of the lead frame at intervals, each connecting column comprises a welding layer and a connecting piece, the welding layers are located between the lead frame and the connecting pieces, each connecting piece comprises a first column body and a plurality of second column bodies, the first column bodies are connected with the welding layers, and the second column bodies are connected with the welding layers. The second columns are arranged on the surface, away from the welding layer, of the first column at intervals; the semiconductor chip is located on the surfaces, away from the lead frame, of the connecting columns and electrically connected with the lead frame through the connecting columns. According to the embodiment of the invention, the reliability of the semiconductor packaging structure can be improved, and the performance of the semiconductor packaging structure under a large-current condition can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] With the development of electronic technology, consumers have higher and higher requirements for electronic products, and more and more functions are integrated into electronic products. In order to meet the development requirements of high integration and miniaturization, semiconductor chips are packaged to form semiconductor packaging structures.

[0003] In the related art, a semiconductor packaging structure includes a lead frame, a semiconductor chip and a plurality of connecting pillars. The plurality of connecting pillars are arranged at intervals on the surface of the lead frame, and the connecting pillars include a welding layer and a connecting piece, the welding layer is located between the lead frame and the connecting piece, and the connecting pillar is a cylinder, and in a direction parallel to the surface of the lead frame, the cross-sectional area of ​​the welding layer is equal to the cross-sectional area of ​​the connecting piece. The semiconductor chip is located on the surface of the plurality of connecting pillars away from the lead frame and is electrically connected to the lead frame through the plurality of connecting pillars.

[0004] However, since the semiconductor chip is electrically connected to the lead frame through multiple connecting columns, the cross-sectional area of ​​the welding layer is equal to the cross-sectional area of ​​the connector, and both are the cross-sectional areas of the connecting columns. If the cross-sectional area of ​​the connecting columns is too large, the contact area between the semiconductor chip and the connector will be too large, and the stress between the semiconductor chip and the connector during packaging will be too large, affecting the reliability of the semiconductor packaging structure; if the cross-sectional area of ​​the connecting columns is too small, when the current is conducted between the semiconductor chip and the lead frame through the welding layer in the connecting columns, it will pass through the welding layer with a too small cross-sectional area. In addition, the resistivity of the welding layer is generally large, so the resistance at the welding layer position is large and the current conduction capacity is weak, resulting in a smaller fusing current at the welding layer position. The welding layer may heat up and melt under high current conditions, affecting the performance of the semiconductor packaging structure under high current conditions. Summary of the invention

[0005] The disclosed embodiment provides a semiconductor packaging structure and a manufacturing method thereof, which can improve the reliability of the semiconductor packaging structure and improve the performance of the semiconductor packaging structure under high current conditions. The technical solution is as follows:

[0006] On the one hand, a semiconductor packaging structure is provided, comprising a lead frame, a semiconductor chip and a plurality of connecting pillars, wherein the plurality of connecting pillars are arranged at intervals on the surface of the lead frame, the connecting pillars comprise a welding layer and a connector, the welding layer is located between the lead frame and the connector, the connector comprises a first column and a plurality of second columns, the first column is connected to the welding layer, and the plurality of second columns are arranged at intervals on the surface of the first column away from the welding layer; the semiconductor chip is located on the surface of the plurality of connecting pillars away from the lead frame and is electrically connected to the lead frame through the plurality of connecting pillars.

[0007] Optionally, a maximum dimension of a cross section of the second column is 40 μm to 250 μm, and the cross section is parallel to a surface of the welding layer.

[0008] Optionally, a distance between two adjacent second pillars in the same connecting pillar is greater than 30 μm and less than 90 μm.

[0009] Optionally, in a direction perpendicular to the surface of the welding layer, a ratio of a height of the second column to a height of the first column is greater than 1 and less than 3.

[0010] Optionally, in a direction perpendicular to the surface of the welding layer, the height of the second column is 30 μm to 90 μm; and / or, in a direction perpendicular to the surface of the welding layer, the height of the first column is greater than 10 μm and less than 30 μm.

[0011] Optionally, the first column is a quadrangular prism or a circular cylinder, and the second column is a quadrangular prism or a circular cylinder.

[0012] Optionally, the welding layer is made of Sn or Au, and the connecting piece is made of Cu, Ni or Au.

[0013] Optionally, the semiconductor packaging structure further includes a packaging layer, wherein the packaging layer is located between the lead frame and the semiconductor chip and between the connecting pillar and the semiconductor chip, and covers the semiconductor chip.

[0014] Optionally, the lead frame includes a plurality of pins, the plurality of pins are arranged at intervals, and each of the pins is correspondingly connected to at least one of the connecting columns.

[0015] On the other hand, a method for manufacturing a semiconductor packaging structure is provided, comprising: providing a lead frame and a semiconductor chip; connecting the lead frame and the semiconductor chip through a plurality of connecting columns to obtain the semiconductor packaging structure, wherein the plurality of connecting columns are arranged at intervals on the surface of the lead frame, the connecting columns include a welding layer and a connector, the welding layer is located between the lead frame and the connector, the connector includes a first column and a plurality of second columns, the first column is connected to the welding layer, the plurality of second columns are arranged at intervals on the surface of the first column away from the welding layer, the semiconductor chip is located on the surface of the plurality of connecting columns away from the lead frame and is electrically connected to the lead frame through the plurality of connecting columns.

[0016] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0017] In the disclosed embodiment, the connection column includes a welding layer and a connection piece, the welding layer is located between the lead frame and the connection piece, the connection piece includes a first column and a plurality of second columns, the first column is connected to the welding layer, and the plurality of second columns are arranged at intervals on the surface of the first column away from the welding layer. In this way, in the same connection column, in the direction parallel to the surface of the lead frame, the cross-sectional area of ​​the welding layer and the cross-sectional area of ​​the first column are larger, and the cross-sectional area of ​​the second column is smaller.

[0018] Since the semiconductor chip is located on the surface of the plurality of connection pillars away from the lead frame and is electrically connected to the lead frame through the plurality of connection pillars, that is, the semiconductor chip is in contact with the second pillar, and the contact area between the semiconductor chip and the second pillar is small, the stress between the semiconductor chip and the connector during packaging can be effectively reduced, and the reliability of the semiconductor packaging structure can be improved. In addition, when the current is conducted between the semiconductor chip and the lead frame through the welding layer in the connection pillar, it will pass through the first pillar and the welding layer with a larger cross-sectional area. According to the law of resistance, it can be known that the resistance of the welding layer is inversely proportional to the cross-sectional area of ​​the welding layer. Therefore, the resistance at the welding layer position is small, and the current conduction capacity is strong, which can ensure that the fuse current at the welding layer position is large, thereby reducing the probability of the welding layer generating heat and fusing under high current conditions, and improving the performance of the semiconductor packaging structure under high current conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1It is a structural schematic diagram of a semiconductor packaging structure in the related art;

[0021] Figure 2 is a structural schematic diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0022] Figure 3 is a top view of a connecting column provided by an embodiment of the present disclosure;

[0023] Figure 4 is a flow chart of a method for manufacturing a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0024] Figure 5 It is a flow chart of another method for manufacturing a semiconductor packaging structure provided by an embodiment of the present disclosure.

[0025] Reference numerals:

[0026] 10: lead frame; 11: pin; 20: connection column; 21: welding layer; 22: connection piece; 221: first column; 222: second column; 30: semiconductor chip; 40: packaging layer. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0028] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity restriction, but indicate the existence of at least one. Words such as "include" and similar words mean that the elements or objects appearing before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In addition, "A and / or B" means that there are three situations: A, B and A and B.

[0029] Figure 1 Schematic diagram of a semiconductor packaging structure in the related art. Figure 1As shown, the semiconductor package structure includes a lead frame 10', a semiconductor chip 30' and a plurality of connecting pillars 20'. The plurality of connecting pillars 20' are arranged at intervals on the surface of the lead frame 10', and the connecting pillars 20' include a welding layer 21' and a connector 22'. The welding layer 21' is located between the lead frame 10' and the connector 22'. The connecting pillar 20' is a cylinder, and in a direction parallel to the surface of the lead frame 10', the cross-sectional area of ​​the welding layer 21' is equal to the cross-sectional area of ​​the connector 22'. The semiconductor chip 30' is located on the surface of the plurality of connecting pillars 20' away from the lead frame 10' and is electrically connected to the lead frame 10' through the plurality of connecting pillars 20'.

[0030] Figure 1 Part (a) and part (b) of FIG. 1 respectively show semiconductor package structures of connecting pillars 20' with different cross-sectional areas. Figure 1 As shown, if the cross-sectional area of ​​the connecting column 20' is too large, the contact area between the semiconductor chip 30' and the connecting part 22' will be too large, and the stress between the semiconductor chip 30' and the connecting part 22' will be too large during packaging, affecting the reliability of the semiconductor packaging structure; if the cross-sectional area of ​​the connecting column 20' is too small, when the current is conducted between the semiconductor chip 30' and the lead frame 10' through the welding layer 21' in the connecting column 20', it will pass through the welding layer 21' with a too small cross-sectional area. In addition, the resistivity of the welding layer 21' is generally large, so the resistance at the position of the welding layer 21' is large, and the current conduction ability is weak, resulting in a small fusing current at the position of the welding layer 21'. The welding layer 21' may heat up and fuse under high current conditions, affecting the performance of the semiconductor packaging structure under high current conditions.

[0031] Figure 2 Schematic diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure. Figure 2 As shown, the semiconductor package structure includes a lead frame 10, a semiconductor chip 30 and a plurality of connecting pillars 20. The plurality of connecting pillars 20 are arranged at intervals on the surface of the lead frame 10, the connecting pillars 20 include a welding layer 21 and a connector 22, the welding layer 21 is located between the lead frame 10 and the connector 22, the connector 22 includes a first column 221 and a plurality of second columns 222, the first column 221 is connected to the welding layer 21, and the plurality of second columns 222 are arranged at intervals on the surface of the first column 221 away from the welding layer 21. The semiconductor chip 30 is located on the surface of the plurality of connecting pillars 20 away from the lead frame 10 and is electrically connected to the lead frame 10 through the plurality of connecting pillars 20.

[0032] In the disclosed embodiment, the connection column 20 includes a welding layer 21 and a connection member 22, the welding layer 21 is located between the lead frame 10 and the connection member 22, the connection member 22 includes a first column 221 and a plurality of second columns 222, the first column 221 is connected to the welding layer 21, and the plurality of second columns 222 are arranged at intervals on the surface of the first column 221 away from the welding layer 21. In this way, in the same connection column 20, in the direction parallel to the surface of the lead frame 10, the cross-sectional area of ​​the welding layer 21 and the cross-sectional area of ​​the first column 221 are larger, and the cross-sectional area of ​​the second column 222 is smaller.

[0033] Since the semiconductor chip 30 is located on the surface of the plurality of connection pillars 20 away from the lead frame 10 and is electrically connected to the lead frame 10 through the plurality of connection pillars 20, that is, the semiconductor chip 30 is in contact with the second pillar 222, and the contact area between the semiconductor chip 30 and the second pillar 222 is small, the stress between the semiconductor chip 30 and the connector 22 during packaging can be effectively reduced, thereby improving the reliability of the semiconductor packaging structure. In addition, when the current is conducted between the semiconductor chip 30 and the lead frame 10 through the welding layer 21 in the connection pillar 20, it will pass through the first pillar 221 and the welding layer 21 with a larger cross-sectional area. According to the resistance law, it can be known that the resistance of the welding layer 21 is inversely proportional to the cross-sectional area of ​​the welding layer 21. Therefore, the resistance at the position of the welding layer 21 is small, and the current conduction capacity is strong, which can ensure that the fuse current at the position of the welding layer 21 is large, thereby reducing the probability of the welding layer 21 generating heat and fusing under high current conditions, and improving the performance of the semiconductor packaging structure under high current conditions.

[0034] It should be noted that, in the semiconductor packaging structure, the lead frame 10 is used to be welded with external wires, etc., so as to lead out the internal circuit of the semiconductor chip 30 .

[0035] Optionally, the semiconductor chip 30 may be a power semiconductor chip. Exemplarily, the power semiconductor chip may be a Schottky diode chip, a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) chip, or a High Electron Mobility Transistor (HEMT) chip.

[0036] In other embodiments, the type of the semiconductor chip 30 may be adjusted according to actual needs, and the present disclosure does not limit this.

[0037] In the embodiment of the present disclosure, the semiconductor chip 30 is taken as a HEMT chip as an example for illustrative description.

[0038] Figure 3is a top view of a connecting column provided by an embodiment of the present disclosure. Figure 2 and Figure 3 The maximum dimension W1 of the cross section of the second column 222 is 40 μm to 250 μm, and the cross section of the second column 222 is parallel to the surface of the welding layer 21 . Here, the maximum dimension refers to the maximum value of the dimension of the cross section of the second column 222 .

[0039] If the maximum dimension W1 of the cross section of the second column 222 is too large, the cross-sectional area of ​​the second column 222 may be too large, thereby increasing the stress between the semiconductor chip 30 and the second column 222 during packaging and affecting the reliability of the semiconductor packaging structure; if the maximum dimension W1 of the cross section of the second column 222 is too small, the cross-sectional area of ​​the second column 222 may be too small, and the resistance at the position of the second column 222 may be large, affecting the current flow requirement of the high-power semiconductor chip; if the maximum dimension W1 of the cross section of the second column 222 is within this range, it can not only effectively reduce the stress between the semiconductor chip 30 and the second column 222 during packaging, but also will not affect the current conduction capability of the semiconductor packaging structure.

[0040] For example, the maximum dimension W1 of the cross section of the second column 222 may be 40 μm, 150 μm, or 250 μm.

[0041] Optionally, the second column 222 is a quadrangular prism or a cylindrical body, which is conducive to connecting the semiconductor chip 30 through the second column 222 and is convenient for production and manufacturing.

[0042] In other embodiments, the second column 222 may also be other columnar shapes, which is not limited in the present disclosure.

[0043] See also Figure 2 and Figure 3 The second column 222 is a quadrangular prism, the cross section of the second column 222 is a rectangle, and the maximum dimension W1 of the cross section of the second column 222 may be the maximum side length of the rectangle.

[0044] In other embodiments, the second column 222 is a cylinder, the cross section of the second column 222 is a circle, and the maximum dimension W1 of the cross section of the second column 222 may be the diameter of the circle.

[0045] Optionally, the distance D1 between two adjacent second pillars 222 in the same connecting pillar 20 is greater than 30 μm and less than 90 μm. In this way, when the semiconductor chip 30 contacts the plurality of second pillars 222, the stress between the semiconductor chip 30 and the second pillars 222 during packaging can be effectively reduced.

[0046] For example, the distance D1 between two adjacent second pillars 222 in the same connecting pillar 20 may be 40 μm, 60 μm, or 80 μm.

[0047] like Figure 2 As shown, in the direction perpendicular to the surface of the welding layer 21, the ratio of the height H2 of the second pillar 222 to the height H1 of the first pillar 221 is greater than 1 and less than 3. If the ratio of the height H2 of the second pillar 222 to the height H1 of the first pillar 221 is too small, it may cause excessive stress between the semiconductor chip 30 and the second pillar 222 during packaging; if the ratio of the height H2 of the second pillar 222 to the height H1 of the first pillar 221 is too large, it may affect the reliability of the connection between the second pillar 222 and the semiconductor chip 30, and the current conduction capacity of the connector 22 may be affected due to the large proportion of the height H2 of the second pillar 222; when the ratio of the height H2 of the second pillar 222 to the height H1 of the first pillar 221 is within this range, the stress between the semiconductor chip 30 and the second pillar 222 during packaging can be effectively reduced, while ensuring that the reliability of the connection between the second pillar 222 and the semiconductor chip 30 is good, and the current conduction capacity of the connector 22 will not be affected.

[0048] For example, the ratio of the height H2 of the second column 222 to the height H1 of the first column 221 may be 1.5, 2, 2.5, or the like.

[0049] Optionally, the height H2 of the second pillar 222 is 30 μm to 90 μm in a direction perpendicular to the surface of the solder layer 21. In this way, the stress between the semiconductor chip 30 and the connecting pillar 20 during packaging can be effectively reduced while ensuring good reliability of the connection between the second pillar 222 and the semiconductor chip 30.

[0050] By way of example, the height H2 of the second pillar 222 may be 30 μm, 60 μm, or 90 μm.

[0051] Optionally, in a direction perpendicular to the surface of the welding layer 21, the height H1 of the first pillar 221 is greater than 10 μm and less than 30 μm. When the height H1 of the first pillar 221 is within this range, when the current is conducted between the semiconductor chip 30 and the lead frame 10 through the first pillar 221 with a larger cross-sectional area, the first pillar 221 can ensure that the resistance at this position is small and the current conduction capability is strong.

[0052] By way of example, the height H1 of the first pillar 221 may be 15 μm, 25 μm, or 30 μm.

[0053] See also Figure 2 and Figure 3, a maximum dimension W2 of a cross section of the first column 221 is greater than 110 μm and less than 590 μm, and a cross section of the first column 221 is parallel to a surface of the welding layer 21 .

[0054] For example, the maximum dimension W2 of the cross section of the first column 221 may be 150 μm, 350 μm, or 550 μm.

[0055] Optionally, the first column 221 is a quadrangular prism or a cylinder, which is conducive to connecting the lead frame 10 through the first column 221 and the welding layer 21, and is convenient for production and manufacturing.

[0056] Exemplarily, the shape of the first column 221 is the same as the shape of the second column 222. For example, the first column 221 and the second column 222 may both be quadrangular prisms.

[0057] In other embodiments, the shape of the first column 221 may be different from the shape of the second column 222. For example, the first column 221 is a quadrangular prism and the second column 222 is a cylindrical body; or the first column 221 is a cylindrical body and the second column 222 is a quadrangular prism, etc., which is not limited in the present disclosure.

[0058] See also Figure 2 and Figure 3 In the same connecting member 22 , two second columns 222 are provided on the first column 221 , and the second columns 222 are arranged at intervals on the edges of the first column 221 on two opposite sides.

[0059] In other embodiments, a larger number of second columns 222 may be disposed on the first column 221 , and the spacing arrangement of the second columns 222 may be adjusted according to actual needs, which is not limited in the present disclosure.

[0060] Optionally, the connecting member 22 is made of Cu, Ni or Au. These materials are convenient for reliable connection with the semiconductor chip 30 and have good electrical conductivity.

[0061] like Figure 2 As shown, in the direction perpendicular to the surface of the welding layer 21, the height H3 of the welding layer 21 is greater than 20 μm and less than 40 μm. When the height H3 of the welding layer 21 is within this range, the welding layer 21 can reliably weld the connector 22 and the lead frame 10, and when the current is conducted between the semiconductor chip 30 and the lead frame 10 through the welding layer 21 with a larger cross-sectional area, the welding layer 21 can ensure that the resistance at this position is small and the current conduction capacity is strong, thereby increasing the fusing current at the welding layer 21 position and improving the performance of the semiconductor packaging structure under high current conditions.

[0062] For example, the height H3 of the welding layer 21 may be 25 μm, 30 μm, or 35 μm.

[0063] Exemplarily, the maximum dimension of the cross section of the welding layer 21 is equal to the maximum dimension W2 of the cross section of the first column 221 .

[0064] Exemplarily, the shape of the welding layer 21 is the same as the shape of the first column 221 . For example, the welding layer 21 and the first column 221 may both be quadrangular prisms.

[0065] Optionally, the welding layer 21 is made of Sn or Au. These materials have low melting points, are easy to melt for welding, and have good electrical conductivity.

[0066] Optionally, the lead frame 10 includes a plurality of pins 11, the plurality of pins 11 are arranged at intervals, and each pin 11 is correspondingly connected to at least one connection column 20. In this way, the plurality of pins 11 are advantageously used to lead out the internal circuit of the semiconductor chip 30, so as to facilitate connection with external wires, etc., and the plurality of pins 11 are arranged at intervals to reduce the probability of short circuits between the internal circuits of the semiconductor chip 30.

[0067] In the disclosed embodiment, the semiconductor chip 30 is a HEMT chip, the lead frame 10 includes three pins, and the semiconductor package structure includes three connecting pillars 20. Each pin 11 is connected to a corresponding connecting pillar 20, and the three connecting pillars 20 are respectively connected to the drain, source and gate of the HEMT chip.

[0068] For example, Figure 2 Among the three connection pillars 20 arranged from left to right in the figure, the connection pillar 20 on the left is connected to the drain of the HEMT chip, the connection pillar 20 in the middle is connected to the source of the HEMT chip, and the connection pillar 20 on the right is connected to the gate of the HEMT chip.

[0069] In other embodiments, the number of pins 11 in the lead frame 10, the number of connecting columns 20 in the semiconductor packaging structure, and the connection method between the pins 11, connecting columns 20 and the semiconductor chip 30 can be adjusted according to actual needs, and the present disclosure does not impose any restrictions on this.

[0070] Optionally, the lead frame 10 is made of Cu.

[0071] By way of example, the lead frame 10 may be a lead frame with a main body made of Cu and a surface plated with Ag and NiPdAu.

[0072] Optionally, the semiconductor packaging structure further includes a packaging layer 40, which is located between the lead frame 10 and the semiconductor chip 30 and between the connecting pillar 20 and the semiconductor chip 30, and covers the semiconductor chip 30. Here, covering means that the packaging layer 40 covers all surfaces of the semiconductor chip 30. In this way, the packaging layer 40 can play a role in sealing, protecting and fixing the semiconductor chip 30, the connecting pillar 20 and the lead frame 10, thereby improving the reliability of the semiconductor packaging structure. In addition, the packaging layer 40 located in the area between the connecting pillar 20 and the semiconductor chip 30 can also buffer the stress between the semiconductor chip 30 and the connecting pillar 20 during packaging, thereby further improving the reliability of the semiconductor packaging structure.

[0073] Exemplarily, the packaging layer 30 is also located between the plurality of connection pillars 20 arranged at intervals and between the plurality of pins 11 arranged at intervals, and the surfaces of the pins 11 away from the semiconductor chip 30 are exposed from the surface of the packaging layer 40 .

[0074] Optionally, the encapsulation layer 30 may be made of a polymer material. For example, the encapsulation layer 30 may be a molding compound, such as epoxy resin.

[0075] Figure 4 1 is a flow chart of a method for manufacturing a semiconductor packaging structure provided by an embodiment of the present disclosure. Figure 4 As shown, the manufacturing method includes:

[0076] In step S1001 , a lead frame and a semiconductor chip are provided.

[0077] In step S1002 , a lead frame and a semiconductor chip are connected via a plurality of connection pillars to obtain a semiconductor package structure.

[0078] A plurality of connecting columns are arranged at intervals on the surface of the lead frame, the connecting columns include a welding layer and a connecting piece, the welding layer is located between the lead frame and the connecting piece, the connecting piece includes a first column and a plurality of second columns, the first column is connected to the welding layer, the plurality of second columns are arranged at intervals on the surface of the first column away from the welding layer, the semiconductor chip is located on the surface of the plurality of connecting columns away from the lead frame and is electrically connected to the lead frame through the plurality of connecting columns.

[0079] In the disclosed embodiment, the connection column includes a welding layer and a connection piece, the welding layer is located between the lead frame and the connection piece, the connection piece includes a first column and a plurality of second columns, the first column is connected to the welding layer, and the plurality of second columns are arranged at intervals on the surface of the first column away from the welding layer. In this way, in the same connection column, in the direction parallel to the surface of the lead frame, the cross-sectional area of ​​the welding layer and the cross-sectional area of ​​the first column are larger, and the cross-sectional area of ​​the second column is smaller.

[0080] Since the semiconductor chip is located on the surface of the plurality of connection pillars away from the lead frame and is electrically connected to the lead frame through the plurality of connection pillars, that is, the semiconductor chip is in contact with the second pillar, and the contact area between the semiconductor chip and the second pillar is small, the stress between the semiconductor chip and the connector during packaging can be effectively reduced, and the reliability of the semiconductor packaging structure can be improved. In addition, when the current is conducted between the semiconductor chip and the lead frame through the welding layer in the connection pillar, it will pass through the first pillar and the welding layer with a larger cross-sectional area. According to the law of resistance, it can be known that the resistance of the welding layer is inversely proportional to the cross-sectional area of ​​the welding layer. Therefore, the resistance at the welding layer position is small, and the current conduction capacity is strong, which can ensure that the fuse current at the welding layer position is large, thereby reducing the probability of the welding layer generating heat and fusing under high current conditions, and improving the performance of the semiconductor packaging structure under high current conditions.

[0081] Figure 5 FIG. 1 is a flow chart of another method for manufacturing a semiconductor packaging structure provided by an embodiment of the present disclosure. Figure 5 As shown, the manufacturing method includes:

[0082] In step S2001, a lead frame and a semiconductor chip are provided.

[0083] Optionally, the semiconductor chip is a HEMT chip.

[0084] Exemplarily, the HEMT chip includes a drain, a source and a gate.

[0085] Optionally, the lead frame includes a plurality of pins, and the plurality of pins are arranged at intervals.

[0086] In step S2002 , a plurality of connectors are formed on the semiconductor chip.

[0087] For example, a connection member may be formed on the drain, source and gate of the HEMT chip. The connection member includes a first column and a plurality of second columns, and the plurality of second columns are arranged at intervals on the surface of the first column close to the semiconductor chip.

[0088] Exemplarily, the connecting member is made of Cu.

[0089] In step S2003, a welding layer is formed on each connecting member to obtain a plurality of connecting columns.

[0090] Exemplarily, a Sn cap may be formed on each connection member to obtain a welding layer, so as to obtain a plurality of connection columns, and the first column is connected to the welding layer.

[0091] In step S2004 , the lead frame and the semiconductor chip are connected via a plurality of connection pillars.

[0092] For example, the soldering layer and the lead frame can be aligned and pasted together and then soldered by reflow soldering, so that the lead frame and the connector are connected by the soldering layer, that is, the lead frame and the semiconductor chip are connected by a plurality of connecting pillars, wherein the plurality of connecting pillars are located on the surface of the lead frame and arranged at intervals.

[0093] Exemplarily, each pin is connected to a corresponding connecting column.

[0094] Exemplarily, the lead frame is made of Cu.

[0095] Optionally, after completing the above step S2004, the manufacturing method may further include:

[0096] In step S2005 , the lead frame, the semiconductor chip and the plurality of connection pillars are packaged by a packaging layer.

[0097] Exemplarily, the packaging layer is located between multiple spaced connection columns, between multiple spaced pins, between the lead frame and the semiconductor chip, and between the connection columns and the semiconductor chip, and covers the semiconductor chip, with the surface of the pins away from the semiconductor chip exposing the surface of the packaging layer.

[0098] Optionally, the structure, material, shape, maximum size and height of each layer can be found in Figures 2 to 3 The detailed description of the related embodiments is omitted here.

[0099] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: The invention comprises a lead frame (10), a semiconductor chip (30) and a plurality of connecting pillars (20). The plurality of connection columns (20) are arranged at intervals on the surface of the lead frame (10); the connection columns (20) include a welding layer (21) and a connection member (22); the welding layer (21) is located between the lead frame (10) and the connection member (22); the connection member (22) includes a first column (221) and a plurality of second columns (222); the first column (221) is connected to the welding layer (21); and the plurality of second columns (222) are arranged at intervals on a surface of the first column (221) away from the welding layer (21); The semiconductor chip (30) is located on a surface of the plurality of connection pillars (20) away from the lead frame (10) and is electrically connected to the lead frame (10) through the plurality of connection pillars (20).

2. The semiconductor package structure according to claim 1, wherein: The maximum dimension of the cross section of the second column (222) is 40 μm to 250 μm, and the cross section is parallel to the surface of the welding layer (21).

3. The semiconductor package structure according to claim 1, wherein: The distance between two adjacent second pillars (222) in the same connecting pillar (20) is greater than 30 μm and less than 90 μm.

4. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: In a direction perpendicular to the surface of the welding layer (21), a ratio of a height of the second column (222) to a height of the first column (221) is greater than 1 and less than 3.

5. The semiconductor package structure according to claim 4, characterized in that: In a direction perpendicular to the surface of the welding layer (21), the height of the second column (222) is 30 μm to 90 μm; and / or, In a direction perpendicular to the surface of the welding layer (21), the height of the first column (221) is greater than 10 μm and less than 30 μm.

6. The semiconductor package structure according to any one of claims 1 to 3 and claim 5, characterized in that: The first column (221) is a quadrangular prism or a circular cylinder, and the second column (222) is a quadrangular prism or a circular cylinder.

7. The semiconductor package structure according to any one of claims 1 to 3 and claim 5, characterized in that: The welding layer (21) is made of Sn or Au, and the connecting piece (22) is made of Cu, Ni or Au.

8. The semiconductor package structure according to any one of claims 1 to 3 and claim 5, characterized in that: The semiconductor packaging structure further comprises a packaging layer (40), wherein the packaging layer (40) is located between the lead frame (10) and the semiconductor chip (30) and between the connecting column (20) and the semiconductor chip (30), and covers the semiconductor chip (30).

9. The semiconductor package structure according to any one of claims 1 to 3 and claim 5, characterized in that: The lead frame (10) comprises a plurality of pins (11), the plurality of pins (11) are arranged at intervals, and each of the pins (11) is correspondingly connected to at least one of the connection columns (20).

10. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Providing a lead frame (10) and a semiconductor chip (30); The lead frame (10) and the semiconductor chip (30) are connected via a plurality of connection pillars (20) to obtain the semiconductor packaging structure, wherein the plurality of connection pillars (20) are arranged at intervals on the surface of the lead frame (10), the connection pillars (20) comprise a welding layer (21) and a connector (22), the welding layer (21) is located between the lead frame (10) and the connector (22), the connector (22) comprises a first column (221) and a plurality of second columns (222), the first column (221) is connected to the welding layer (21), the plurality of second columns (222) are arranged at intervals on the surface of the first column (221) away from the welding layer (21), and the semiconductor chip (30) is located on the surface of the plurality of connection pillars (20) away from the lead frame (10) and is electrically connected to the lead frame (10) via the plurality of connection pillars (20).

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