High-bandwidth lead bonding structure

Abstract

The invention discloses a high-bandwidth lead bonding structure which comprises a carrier plate and a bare chip placed on the carrier plate, a first chip bonding pad and a third chip bonding pad on the bare chip are grounding ends of the chip, and a second bonding pad is a signal end of the chip. The high-bandwidth lead bonding structure is characterized in that the three bare chips and the three bonding pads of the bonding pad carrier plate are connected through bonding wires which are arranged in an overlapping mode to form the high-bandwidth lead bonding structure, and the first bonding pad and the third bonding pad of the bare chip are connected with the third bonding pad and the first bonding pad of the bonding pad carrier plate through two grounding bonding wires respectively; and the second bonding pad of the bare chip is connected with the second bonding pad of the bonding pad carrier plate through a signal bonding wire. Compared with the prior art, the invention has the advantages that the parasitic inductance of the signal bonding wire to the ground is reduced, the chip port bandwidth is improved, the distance between the signal bonding wire and the grounding bonding wire is reduced, the parasitic capacitance is increased, the parasitic inductance is compensated at a high frequency band, the chip port bandwidth is improved, and the cost is reduced. The high-bandwidth chip port can be widely applied to the fields of radio frequency, optical communication and the like which need high-bandwidth chip ports.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit packaging, in particular to a high-bandwidth wire bonding structure for a chip high-speed port. Background Art

[0002] Wire bonding is an important process in integrated circuit packaging. It connects the pads on the chip die to the pads on the substrate through metal bonding wires, so that the circuits in the chip die can be connected to the outside and powered.

[0003] See also Figure 1 , the conventional wire bonding structure includes: a chip die (101), a substrate (102), a chip die pad (103), a bonding wire (104), and a substrate pad (105). The first, second, and third chip die pads are respectively connected to the first, second, and third substrate pads through bonding wires, and the three ports on the chip die can be led out to the outside. Among them, the first and third chip die pads are the chip ground terminals G, and the second chip die pad is the chip signal terminal S. However, the bonding wire is not an ideal wire and has a certain parasitic inductance. As the frequency increases, the impedance mismatch caused by the parasitic inductance becomes more serious, which deteriorates the signal integrity and becomes one of the bottlenecks limiting the improvement of the chip port bandwidth. Therefore, reducing the parasitic inductance of the bonding wire is the key to improving the chip port bandwidth.

[0004] In summary, the wire bonding structure in the prior art has serious impedance mismatch, the parasitic inductance of the bonding wire reduces the chip port bandwidth, seriously deteriorates the signal integrity, and greatly limits the bandwidth improvement of the chip port. Summary of the invention

[0005] The purpose of the present invention is to provide a high-bandwidth wire bonding structure to address the deficiencies in the prior art. The wire bonding structure adopts an overlapping ground bonding wire and a signal bonding wire, which can reduce parasitic inductance and increase parasitic capacitance, thereby improving the signal bandwidth of the chip port. The structure is simple, and the problem of the parasitic inductance of the bonding wire reducing the bandwidth of the chip port is better solved. The structure has good application prospects and commercial development value.

[0006] The object of the present invention is achieved as follows: a high-bandwidth wire bonding structure, characterized in that the wire bonding structure includes: a carrier and a chip die placed on the carrier, three die pads on the chip die, which are recorded as the first, second and third die pads from left to right; wherein the first and third die pads are ground terminals of the chip, and the second die pad is a signal terminal of the chip; the three die pads on the carrier are recorded as the first, second and third carrier pads from left to right; the first, second and third die pads on the chip die are arranged in parallel and correspond one to one with the first, second and third carrier pads on the carrier; the first and third die pads are connected to the third and first carrier pads respectively through two ground bonding wires, and the second die pad is connected to the second carrier pad by a signal bonding wire, forming a high-bandwidth wire bonding structure in which the signal bonding wire and the two ground bonding wires are overlapped.

[0007] The carrier board may be made of any material such as a printed circuit board (PCB), a package substrate or an interposer.

[0008] The high-bandwidth wire bonding structure can lead out the chip grounding bonding structure only through a group of pads, that is, the chip grounding bonding structure can be led out by using any group of pads, including a ground bonding wire connecting the first bare chip pad and the third carrier pad, or another ground bonding wire connecting the third bare chip pad and the first carrier pad.

[0009] Compared with the prior art, the present invention has the following beneficial technical effects and significant technical progress: 1) The ground bonding wire overlaps with the signal bonding wire, which reduces the parasitic inductance of the signal bonding wire to the ground and improves the chip port bandwidth; 2) The ground bonding wire overlaps with the signal bonding wire, which reduces the distance between the signal bonding wire and the ground bonding wire, increases the parasitic capacitance, compensates the parasitic inductance in the high frequency band, and improves the chip port bandwidth; 3) It can be widely used in fields such as radio frequency and optical communication that require high-bandwidth chip ports. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the traditional wire bonding structure; Figure 2 It is a schematic diagram of the structure of the present invention; Figure 3 It is a structural schematic diagram of Example 1; Figure 4 It is a structural schematic diagram of Example 2; Figure 5 It is a schematic diagram comparing insertion loss curves of the present invention and the traditional wire bonding structure. DETAILED DESCRIPTION

[0011] See also Figure 2 The present invention includes a chip die 201, a carrier board 202, a signal bonding wire 204S and two ground bonding wires 204G. The three pads on the chip die 201 are respectively recorded as a first die pad 203G1, a second die pad 203S and a third die pad 203G2 from left to right; the first die pad 203G1 and the third die pad 203G2 are ground ports G, and the second die pad 203S is a signal port S; the three pads on the carrier board 202 are respectively recorded as a first carrier board pad 205a, a second carrier board pad 205b and a third die pad 205c from left to right. 5b, a third substrate pad 205c; the three pads on the chip die 201 and the three pads on the substrate 202 are arranged in parallel and correspond one to one; the second die pad 203S is connected to the second substrate pad 205b by a signal bonding wire 204S; the first die pad 203G1 and the third die pad 203G2 are connected to the third substrate pad 205c and the first substrate pad 205a by two ground bonding wires 204G, respectively, to form a high-bandwidth wire bonding structure in which the signal bonding wire 204S and the two ground bonding wires 204G are overlapped.

[0012] The principle of improving the chip port bandwidth of the present invention is: the ground G bonding wire overlaps with the signal S bonding wire, which reduces the parasitic inductance of the signal S bonding wire to the ground, thereby improving the chip port bandwidth; and the overlapping reduces the distance between the signal S bonding wire and the ground G bonding wire, thereby increasing the parasitic capacitance, compensating for the parasitic inductance in the high frequency band, and further improving the bandwidth of the signal S port.

[0013] The present invention is described in detail below with reference to the accompanying drawings. Example

[0014] See also Figure 3 The second chip bare die pad 203S is connected to the second carrier pad 205b through the signal bonding wire 204S, and the first bare die pad 203G1 is connected to the third carrier pad 205c through the ground bonding wire 204G, forming a group of pads leading to the chip grounding high bandwidth wire bonding structure. Example

[0015] See also Figure 4 The second chip bare die pad 203S is connected to the second carrier pad 205b through the signal bonding wire 204S, and the third bare die pad 203G2 is connected to the first carrier pad 205a through the ground bonding wire 204G, forming another group of pads leading out the chip grounding high bandwidth wire bonding structure.

[0016] See also Figure 5It can be seen that the insertion loss 302 of the present invention is lower than the insertion loss 301 of the traditional structure. By comparing the insertion loss S21 curve, it is fully demonstrated that the present invention can achieve a higher signal bandwidth.

[0017] The above is only an implementation mode of the present invention and is not intended to limit the present invention. Any modifications and improvements made without departing from the concept of the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A high-bandwidth wire bonding structure, comprising a carrier and a chip die placed on the carrier, wherein a first die pad and a third die pad on the chip die are ground ports of the chip, and the second die pad is a signal port of the chip, and the three pads on the carrier are respectively a first carrier pad, a second carrier pad and a third carrier pad, characterized in that: The second bare die pad is connected to the second carrier pad by a signal bonding wire; the first bare die pad and the third bare die pad are respectively connected to the third carrier pad and the first carrier pad by two ground bonding wires, forming a high-bandwidth wire bonding structure in which the signal bonding wire and the two ground bonding wires are overlapped.

2. The high-bandwidth wire bonding structure according to claim 1, characterized in that: The three pads on the chip die and the three pads on the carrier are arranged in parallel and correspond one to one.

3. The high-bandwidth wire bonding structure according to claim 1, characterized in that: The carrier board is a printed circuit board, a packaging substrate or an intermediate layer of any material.

4. The high-bandwidth wire bonding structure according to claim 1, characterized in that: The high-bandwidth wire bonding structure uses a group of pads connected to the first bare die pad and the third carrier pad to lead out the chip ground, or a group of pads connected to the third bare die pad and the first carrier pad to lead out the chip ground.

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