Electronic package and fabrication method thereof

Abstract

An electronic package and a method of fabricating the same, mainly including forming a groove space for accommodating an electronic component on a wiring structure, and forming an encapsulation layer on the wiring structure to cover the electronic component, the overall thickness of the electronic package being easily thinned by the design of the groove space to facilitate the satisfaction of miniaturization requirements.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, in particular to a thinned electronic packaging component and a manufacturing method thereof. Background Art

[0002] With the evolution of semiconductor packaging technology, semiconductor devices have developed different packaging types. In order to improve electrical functions and save packaging space, different three-dimensional packaging technologies have been developed to integrate integrated circuits with different functions into a single packaging structure. For example, electronic components with different functions (such as memory, central processing unit, graphics processor, image application processor, etc.) can be integrated into the system through stacking design for application in thin and light electronic products.

[0003] Figure 1 1 is a cross-sectional view of a conventional semiconductor package 1. The semiconductor package 1 comprises: a packaging body 15, a semiconductor chip 11 embedded in the packaging body 15, a circuit structure 10 and a wiring structure 14 disposed on opposite sides of the packaging body 15, and a plurality of conductive pillars 13 embedded in the packaging body 15 to electrically connect the circuit structure 10 and the wiring structure 14, and the semiconductor chip 11 is adhered to the wiring structure 14 through a die-mounting film 12 and electrically connected to the circuit structure 10 through a plurality of conductors 112, and a plurality of solder balls 17 and passive components 19 are formed on the lower side of the circuit structure 10, so that the semiconductor package 1 is connected to a circuit board (not shown) through the solder balls 17.

[0004] However, in the conventional semiconductor package 1 , the die-mounting film 12 is disposed between the semiconductor chip 11 and the wiring structure 14 , which makes it difficult to reduce the overall thickness of the semiconductor package 1 , and thus is not conducive to meeting the demand for miniaturization.

[0005] Therefore, how to overcome the above-mentioned problems of the prior art has become a difficult problem that needs to be overcome urgently in the industry. Summary of the invention

[0006] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, comprising: a wiring structure having a groove space; a packaging layer formed on the wiring structure, wherein the packaging layer has a first surface and a second surface relative to each other, and the packaging layer is combined with the wiring structure by its second surface; an electronic component embedded in the packaging layer and located in the groove space; a plurality of conductive pillars embedded in the packaging layer and electrically connected to the wiring structure; and a circuit structure formed on the first surface of the packaging layer and electrically connecting the plurality of conductive pillars and the electronic component.

[0007] The present invention also provides a method for manufacturing an electronic package, comprising: forming a conductive layer on a partial surface of a carrier board, and placing an electronic component on other surfaces of the carrier board; forming a packaging layer on the carrier board so that the packaging layer covers the electronic component, wherein the packaging layer has a first surface and a second surface relative to each other, and the packaging layer combines the carrier board and the conductive layer with its second surface so that the second surface of the packaging layer presents a concave-convex surface; removing the carrier board and the conductive layer to expose the second surface of the packaging layer and the electronic component; and forming a wiring structure on the second surface of the packaging layer and on the electronic component, wherein the wiring structure forms a groove space corresponding to the second surface so that the electronic component is located in the groove space.

[0008] In the aforementioned electronic package and its manufacturing method, the electronic component contacts the wiring structure.

[0009] The aforementioned electronic package and its manufacturing method also include forming a plurality of conductive elements on the wiring structure, and the conductive elements are electrically connected to the wiring structure.

[0010] The aforementioned electronic package and its manufacturing method further include forming a conductive column on the conductive layer so that the packaging layer covers the conductive column, and the conductive column is electrically connected to the wiring structure. For example, the conductive column is located outside the groove space. Alternatively, it also includes forming a wiring structure on the first surface of the packaging layer, and the wiring structure is electrically connected to the conductive column and the electronic component.

[0011] The aforementioned electronic package and its manufacturing method further include forming a circuit structure on the first surface of the packaging layer, and the circuit structure is electrically connected to the electronic element. Further, it includes forming a plurality of conductive elements on the circuit structure, and the conductive elements are electrically connected to the circuit structure.

[0012] From the above, it can be seen that the electronic package and its manufacturing method of the present invention are mainly designed through the conductive layer, so that after the carrier board and the conductive layer are removed, the wiring structure can form a groove space. Therefore, compared with the prior art, the electronic component is accommodated in the groove space of the electronic package of the present invention, so that the overall thickness of the electronic package can be easily thinned, so as to meet the needs of miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0014] FIG. 2A to FIG. 2F It is a cross-sectional schematic diagram of a method for manufacturing an electronic package of the present invention.

[0015] Figure 3 for Figure 2F A cross-sectional schematic diagram of another embodiment of the present invention.

[0016] Main component symbols

[0017] 1 Semiconductor Package

[0018] 10,20 Line Structure

[0019] 11. Semiconductor Chip

[0020] 112,212 Conductors

[0021] 12. Chip film

[0022] 13 Conductive column

[0023] 14,24,34 wiring structure

[0024] 15 Encapsulation colloid

[0025] 17 Solder Balls

[0026] 19 Passive Components

[0027] 2,3 Electronic packaging

[0028] 200 Insulation

[0029] 201 Line Layer

[0030] 202 Electrical contact pad

[0031] 21 Electronic components

[0032] 21a Action surface

[0033] 21b Non-active surface

[0034] 210 Electrode pads

[0035] 211 Protective film

[0036] 212a,23a,23b end faces

[0037] 23 Conductive pillars

[0038] 240,340 dielectric layer

[0039] 241,341 wiring layers

[0040] 242 Electrical connection pads

[0041] 25 Encapsulation layer

[0042] 25a First surface

[0043] 25b Second surface

[0044] 27,28 Conductive elements

[0045] 29 Auxiliary Function Elements

[0046] 8 Support plate

[0047] 9 Loading plate

[0048] 90 Release layer

[0049] 80,91 Adhesive layer

[0050] 92 Conductive layer

[0051] L Cutting path

[0052] S Groove space. DETAILED DESCRIPTION

[0053] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and technical effects of the present invention from the contents disclosed in this specification.

[0054] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment of size should still fall within the scope of the technical contents disclosed by the present invention without affecting the technical effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0055] FIG. 2A to FIG. 2F It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.

[0056] like Figure 2A As shown, a conductive layer 92 is formed on a portion of the surface of a carrier plate 9, a plurality of conductive pillars 23 are formed on the conductive layer 92, and at least one electronic component 21 is disposed on the other surface of the carrier plate 9 (the surface without the conductive layer).

[0057] The carrier plate 9 is, for example, a plate made of a semiconductor material (such as silicon or glass), and the conductive layer 92 is a metal layer.

[0058] In this embodiment, a release layer 90 and an adhesive layer 91 are sequentially formed on the carrier plate 9 by, for example, coating, so that the conductive layer 92 is bonded to the adhesive layer 91, and the conductive layer 92 is formed by etching a copper layer such as a copper foil. For example, a copper foil is bonded to the adhesive layer 91, and then the copper foil is patterned to expose a portion of the surface of the adhesive layer 91.

[0059] The conductive pillars 23 are formed on the conductive layer 92 by electroplating the conductive layer 92 .

[0060] In this embodiment, the conductive pillar 23 is made of a metal material such as copper or a solder material.

[0061] The electronic component 21 is an active component, a passive component or a combination of the two. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

[0062] In this embodiment, the electronic component 21 is a semiconductor chip, which has an active surface 21a and an inactive surface 21b opposite to each other. The electronic component 21 is bonded to the adhesive layer 91 with its inactive surface 21b, and the active surface 21a has a plurality of electrode pads 210 and a protective film 211 such as a passivation material, wherein a plurality of conductors 212 are bonded and electrically connected to the electrode pads 210, and the conductors 212 are embedded in the protective film 211. For example, the conductors 212 are spherical shapes such as conductive lines, solder balls, or pillars of metal materials such as copper pillars, solder bumps, or stud-shaped conductive parts made by a wire bonding machine, but are not limited thereto.

[0063] like Figure 2B As shown, a packaging layer 25 is formed on the adhesive layer 91 and the conductive layer 92 of the carrier board 9 so that the packaging layer 25 covers the electronic component 21, the multiple conductors 212 and the multiple conductive pillars 23, wherein the packaging layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the protective film 211, the end surface 212a of the conductor 212 and the end surface 23a of the conductive pillar 23 are exposed on the first surface 25a of the packaging layer 25, and the packaging layer 25 is combined with the adhesive layer 91 and the conductive layer 92 of the carrier board 9 with its second surface 25b, so that the second surface 25b of the packaging layer 25 presents a concave-convex surface.

[0064] In this embodiment, the packaging layer 25 is an insulating material, such as polyimide (PI), dry film, packaging colloid such as epoxy, or molding compound. For example, the packaging layer 25 can be formed on the adhesive layer 91 and the conductive layer 92 by a process such as liquid compound, injection, lamination, or compression molding.

[0065] Furthermore, a flattening process may be performed to make the first surface 25a of the packaging layer 25 flush with the protection film 211, the end surface 23a of the conductive column 23, and the end surface 212a of the conductor 212, so that the end surface 23a of the conductive column 23 and the end surface 212a of the conductor 212 are exposed on the first surface 25a of the packaging layer 25. For example, the flattening process removes part of the material of the protection film 211, part of the material of the conductive column 23, part of the material of the conductor 212, and part of the material of the packaging layer 25 by grinding.

[0066] like Figure 2C As shown, a circuit structure 20 is formed on the first surface 25 a of the packaging layer 25 , and the circuit structure 20 is electrically connected to the plurality of conductive pillars 23 and the plurality of conductive bodies 212 .

[0067] In this embodiment, the circuit structure 20 includes at least one insulating layer 200 and a circuit layer 201 disposed on the insulating layer 200, wherein the outermost insulating layer 200 can be used as a solder mask, and the outermost circuit layer 201 is exposed from the solder mask to serve as an electrical contact pad 202, so as to form a plurality of conductive elements 27 such as solder bumps, copper bumps or others on the electrical contact pad 202, and the conductive elements 27 are electrically connected to the electrical contact pad 202. For example, the circuit structure 20 is made with a circuit redistribution layer (RDL) specification. Further, an under bump metallurgy (UBM) (not shown) can be formed on the electrical contact pad 202 to facilitate the combination of the conductive element 27.

[0068] Furthermore, the material forming the circuit layer 201 is copper, and the material forming the insulating layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc., or a solder mask material such as green paint and ink.

[0069] In addition, at least one auxiliary functional element 29 , such as a passive element, can be connected to a portion of the electrical contact pads 202 of the circuit structure 20 as required.

[0070] like Figure 2D As shown, the conductive elements 27 are placed on a support plate 8, and then the carrier plate 9 and the conductive layer 92 thereon are removed to expose the second surface 25b of the packaging layer 25, the other end surface 23b of the conductive column 23 and the inactive surface 21b of the electronic element 21.

[0071] In this embodiment, an adhesive layer 80 is provided on the support plate 8 to allow the circuit structure 20 to adhere to the adhesive layer 80, so that the conductive elements 27 and the auxiliary functional elements 29 are buried in the adhesive layer 80, and after removing the carrier plate 9 and the release layer 90 and the adhesive layer 91 thereon, the conductive layer 92 is removed by etching. At this time, the other end surface 23b of the conductive column 23 is flush with the second surface 25b of the packaging layer 25 and is exposed on the second surface 25b of the packaging layer 25.

[0072] like Figure 2E As shown, a wiring structure 24 electrically connecting the plurality of conductive pillars 23 is formed on the second surface 25 b of the packaging layer 25 and the inactive surface 21 b of the electronic component 21 , wherein the wiring structure 24 forms a groove space S corresponding to the position of the electronic component 21 .

[0073] In this embodiment, the wiring structure 24 includes a plurality of dielectric layers 240 and a wiring layer 241 combined with the dielectric layer 240. For example, the dielectric layer 240 contacts the inactive surface 21b of the electronic element 21, and the wiring layer 241 is provided with a plurality of electrical connection pads 242 on the outermost dielectric layer 240 to combine with a conductive element 28 such as a solder bump, a copper bump or others.

[0074] Furthermore, the material forming the dielectric layer 240 may be polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials, and a redistribution layer (RDL) process may be used to form the wiring layer 241 and the dielectric layer 240.

[0075] In addition, the electronic component 21 is located in the groove space S, and the conductive pillars 23 are located outside the groove space S.

[0076] like Figure 2F As shown, remove the support plate 8, and then Figure 2E The cutting path L shown is used for performing a singulation process to obtain a plurality of electronic packages 2 , and the electronic packages 2 can be externally connected to another electronic module or other electronic components (not shown) through the conductive elements 27 , 28 .

[0077] See also Figure 3In other embodiments, the wiring structure 34 has only a single wiring layer 341, which is formed on the second surface 25b of the packaging layer 25 and electrically connected to the plurality of conductive pillars 23, and a dielectric layer 340 covers the wiring layer 341 and the inactive surface 21b of the electronic element 21. For example, the dielectric layer 341 is used as a solder mask, which has a plurality of openings, so that a portion of the surface of the wiring layer 341 is exposed in the openings for bonding the conductive element 28.

[0078] Therefore, the manufacturing method of the present invention mainly exposes the adhesive layer 91 through the design of the conductive layer 92, so that after removing the carrier board 9 and the conductive layer 92, the wiring structure 24, 34 can form a groove space S, so that the electronic component 21 can be accommodated in the groove space S. Therefore, compared with the prior art, there is no existing chip-mounting film between the electronic component 21 of the electronic package 2, 3 of the present invention and the wiring structure 24, 34, so that the overall thickness of the electronic package 2, 3 is thinned to meet the miniaturization requirements.

[0079] The present invention provides an electronic package 2 , 3 , which includes: a wiring structure 24 , 34 , a packaging layer 25 and at least one electronic component 21 .

[0080] The wiring structures 24 , 34 have a groove space S.

[0081] The packaging layer 25 is formed on the wiring structures 24 and 34 , wherein the packaging layer 25 has a first surface 25 a and a second surface 25 b opposite to each other, and the packaging layer 25 is combined with the wiring structures 24 and 34 via the second surface 25 b .

[0082] The electronic component 21 is embedded in the packaging layer 25 and located in the groove space S.

[0083] In one embodiment, the electronic component 21 contacts the wiring structures 24 , 34 .

[0084] In one embodiment, the electronic packages 2 , 3 further include a plurality of conductive elements 28 disposed on the wiring structures 24 , 34 and electrically connected to the wiring structures 24 , 34 .

[0085] In one embodiment, the electronic package 2, 3 further includes a plurality of conductive pillars 23 embedded in the packaging layer 25 and electrically connected to the wiring structures 24, 34. For example, the conductive pillars 23 are located outside the groove space S. Alternatively, the electronic package 2, 3 further includes a circuit structure 20 formed on the first surface 25a of the packaging layer 25, which electrically connects the conductive pillars 23 and the electronic element 21.

[0086] In one embodiment, the electronic package 2, 3 further includes a circuit structure 20 formed on the first surface 25a of the packaging layer 25, which is electrically connected to the electronic component 21. It further includes a plurality of conductive elements 27 disposed on the circuit structure 20 and electrically connected to the circuit structure 20.

[0087] In summary, the electronic package and the manufacturing method thereof of the present invention form a groove space through the design of the wiring structure to accommodate the electronic component in the groove space. Therefore, there is no need to configure the existing chip mounting film between the electronic component and the wiring structure of the electronic package of the present invention. Not only can the chip mounting film (DAF) be omitted to reduce the peeling and void problems, but the overall thickness of the electronic package can also be easily thinned to meet the needs of miniaturization.

[0088] The above embodiments are only used to illustrate the principles and technical effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the inventive concept and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, comprising: A wiring structure having a groove space; A packaging layer formed on the wiring structure, wherein the packaging layer has a first surface and a second surface opposite to each other, and the packaging layer is combined with the wiring structure at its second surface; An electronic component embedded in the packaging layer and located in the groove space; a plurality of conductive pillars embedded in the packaging layer and electrically connected to the wiring structure; and The circuit structure is formed on the first surface of the packaging layer and electrically connects the plurality of conductive pillars and the electronic element.

2. The electronic package of claim 1, wherein: The electronic component contacts the wiring structure.

3. The electronic package of claim 1, wherein: The electronic package also includes a plurality of conductive elements disposed on the wiring structure and electrically connected to the wiring structure.

4. The electronic package of claim 1, wherein: The conductive column is located outside the groove space.

5. The electronic package of claim 1, wherein: The electronic package also includes a plurality of conductive elements disposed on the circuit structure and electrically connected to the circuit structure.

6. A method for manufacturing an electronic package, comprising: Forming a conductive layer on a partial surface of a carrier board, and placing electronic components on the other surface of the carrier board; Forming a packaging layer on the carrier board so that the packaging layer covers the electronic component, wherein the packaging layer has a first surface and a second surface opposite to each other, and the packaging layer is combined with the carrier board and the conductive layer by the second surface thereof, so that the second surface of the packaging layer presents a concave-convex surface; removing the carrier plate and the conductive layer to expose the second surface of the packaging layer and the electronic component; and A wiring structure is formed on the second surface of the packaging layer and on the electronic element, wherein the wiring structure is formed with a groove space corresponding to the second surface, so that the electronic element is located in the groove space.

7. The method for manufacturing an electronic package as claimed in claim 6, wherein: The electronic component contacts the wiring structure.

8. The method for manufacturing an electronic package as claimed in claim 6, wherein: The manufacturing method also includes forming a plurality of conductive elements on the wiring structure, and the conductive elements are electrically connected to the wiring structure.

9. The method for manufacturing an electronic package as claimed in claim 6, wherein: The manufacturing method also includes forming a plurality of conductive pillars on the conductive layer so that the packaging layer covers the conductive pillars, and the conductive pillars are electrically connected to the wiring structure.

10. The method for manufacturing an electronic package according to claim 9, wherein: The plurality of conductive pillars are located outside the groove space.

11. The method for manufacturing an electronic package according to claim 9, wherein: The manufacturing method further comprises forming a circuit structure on the first surface of the packaging layer, and the circuit structure electrically connects the plurality of conductive pillars and the electronic element.

12. The method for manufacturing an electronic package according to claim 6, wherein: The manufacturing method also includes forming a circuit structure on the first surface of the packaging layer, and the circuit structure is electrically connected to the electronic element.

13. The method for manufacturing an electronic package according to claim 12, wherein: The manufacturing method also includes forming a plurality of conductive elements on the circuit structure, and the conductive elements are electrically connected to the circuit structure.

Images