Chip packaging structure

Abstract

The invention discloses a chip packaging structure. The chip packaging structure comprises a first chip and a second chip, a first connecting area and a second connecting area which are spaced from each other in a first direction are formed on the first chip, and a first connecting pin extending in a second direction is arranged in the first connecting area. A second connecting pin extending in a second direction is arranged in the second connecting area; the second chip is arranged on one side of the first chip in the second direction, a third connecting area is formed on the second chip, and a third connecting pin extending in the second direction is arranged in the third connecting area; wherein the first connecting pin is connected with the third connecting pin, and the first direction is orthogonal to the second direction. According to the chip packaging structure, the first connecting pin of the first chip and the third connecting pin of the second chip are directly connected, an adapter plate structure is omitted, cost and packaging size are reduced, a connecting path is shortened, and signal attenuation is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging structure. Background Art

[0002] The current chip packaging technology usually interconnects or connects multiple chips (such as main chips and memory chips) to the outside with the help of adapter boards to facilitate data transmission or signal transmission of the chips. However, the adapter board is expensive, and the introduction of the adapter board will increase the chip packaging volume and cost. At the same time, the signals of the main chip and the memory chip have a routing section on the adapter board, which will cause a certain amount of signal attenuation, and the signal routing distance is short, so the signals interfere with each other seriously. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a chip packaging structure. The chip packaging structure according to the present invention directly connects the first connecting pin of the first chip and the third connecting pin of the second chip, eliminates the adapter plate structure, reduces the cost and packaging volume, shortens the connection path, and reduces signal attenuation.

[0004] According to the present invention, the chip packaging structure includes a first chip and a second chip, wherein a first connection area and a second connection area spaced apart from each other in a first direction are formed on the first chip, a first connection pin extending in the second direction is arranged in the first connection area, and a second connection pin extending in the second direction is arranged in the second connection area; the second chip is arranged on one side of the first chip in the second direction, a third connection area is formed on the second chip, and a third connection pin extending in the second direction is arranged in the third connection area; wherein the first connection pin is connected to the third connection pin, and the first direction is orthogonal to the second direction.

[0005] According to the chip packaging structure of the present invention, a first chip and a second chip are provided, a first connection area and a second connection area are formed on the first chip, and a third connection area is provided on the second chip, wherein a first connection pin is formed in the first connection area, and a third connection pin is formed in the third connection area, and the first connection pin and the third connection pin extend toward each other in the second direction respectively, and when the chip is packaged, the first connection pin is connected with the third connection pin to realize the connection between the first chip and the second chip, thereby realizing the signal transmission between the first chip and the second chip; the second connection pin can be connected with an external power supply or other signal transmission structure, thereby realizing the external transmission function of the first chip. The chip packaging structure realizes the interconnection between the first chip and the second chip by directly connecting the first connection pin and the third connection pin, cancels the adapter plate structure in the background technology, reduces the cost of the chip packaging structure, and makes the manufacturing and assembly process of the chip packaging structure simpler and more efficient; at the same time, the cancellation of the adapter plate structure can also effectively reduce the volume of the chip packaging structure, which is convenient for the arrangement of the chip packaging structure. The way of directly connecting the first connection pin and the third connection pin reduces the transmission distance of the signal inside the package, thereby reducing the attenuation of the signal and the mutual interference between the signals.

[0006] According to an embodiment of the present invention, the first connection area and the third connection area are at least partially opposite to each other in the second direction.

[0007] According to an embodiment of the present invention, the chip packaging structure further includes: a substrate, which is disposed on a side of the second chip away from the first chip, the substrate is connected to an external signal, and the second connecting pin is connected to the substrate.

[0008] According to an embodiment of the present invention, the first chip, the second chip and the substrate are at least partially overlapped in the second direction.

[0009] According to one embodiment of the present invention, the first connection area and the third connection area are respectively constructed as a plurality of first connection pins corresponding to each other, each of the first connection areas is provided with a plurality of first connection pins spaced apart from each other, each of the third connection areas is provided with a plurality of third connection pins spaced apart from each other, and each of the third connection pins is connected to the corresponding first connection pin.

[0010] According to an embodiment of the present invention, a plurality of the first connection regions are arranged at intervals on at least a portion of the periphery of the second connection region.

[0011] According to an embodiment of the present invention, the second chips are configured as a plurality of second chips spaced apart from each other in the first direction, and the second connecting pins are disposed between two adjacent second chips.

[0012] According to an embodiment of the present invention, the second connecting pins are configured as a plurality of pins spaced apart from each other, and the plurality of second connecting pins are arranged in a plurality of columns in the first direction.

[0013] According to an embodiment of the present invention, a plurality of external connection terminals spaced apart from each other are disposed on a side of the substrate facing away from the second chip, and the plurality of external connection terminals are arranged in a plurality of rows and columns on the substrate.

[0014] According to an embodiment of the present invention, the device further includes: a protection layer, wherein the protection layer covers at least a portion of the periphery of the first chip and the second chip.

[0015] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0017] Figure 1 is a schematic diagram of a chip packaging structure according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of cooperation between a first chip and a second chip according to an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of a chip packaging structure according to another embodiment of the present invention.

[0020] Reference numerals:

[0021] Chip packaging structure 1;

[0022] A first chip 11, a first connection area 111, a first connection pin 1111, a second connection area 112, and a second connection pin 1121;

[0023] A second chip 12, a third connection area 121, and a third connection pin 1211;

[0024] Base plate 13, external connection terminal 131;

[0025] Protective layer 14. DETAILED DESCRIPTION

[0026] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0027] The current chip packaging technology usually interconnects or connects multiple chips (such as main chips and memory chips) to the outside with the help of adapter boards to facilitate data transmission or signal transmission of the chips. However, the adapter board is expensive, and the introduction of the adapter board will increase the chip packaging volume and cost. At the same time, the signals of the main chip and the memory chip have a routing section on the adapter board, which will cause a certain amount of signal attenuation, and the signal routing distance is short, so the signals interfere with each other seriously.

[0028] Reference below Figure 1-Figure 3 A chip packaging structure according to an embodiment of the present invention is described.

[0029] The chip packaging structure 1 according to the present invention includes a first chip 11 and a second chip 12, wherein a first connection area 111 and a second connection area 112 spaced apart from each other in a first direction are formed on the first chip 11, a first connection pin 1111 extending in the second direction is arranged in the first connection area 111, and a second connection pin 1121 extending in the second direction is arranged in the second connection area 112; the second chip 12 is arranged on one side of the first chip 11 in the second direction, a third connection area 121 is formed on the second chip 12, and a third connection pin 1211 extending in the second direction is arranged in the third connection area 121; wherein the first connection pin 1111 is connected to the third connection pin 1211, and the first direction is orthogonal to the second direction.

[0030] According to the chip packaging structure 1 of the present invention, a first chip 11 and a second chip 12 are provided, a first connection area 111 and a second connection area 112 are formed on the first chip 11, and a third connection area 121 is provided on the second chip 12, wherein a first connection pin 1111 is formed in the first connection area 111, and a third connection pin 1211 is formed in the third connection area 121, the first connection pin 1111 and the third connection pin 1211 extend toward each other in a second direction respectively, and when chip packaging is performed, the first connection pin 1111 is connected to the third connection pin 1211 to realize the connection between the first chip 11 and the second chip 12, thereby realizing signal transmission between the first chip 11 and the second chip 12; the second connection pin 1121 can be connected to an external power supply or other signal transmission structure, thereby realizing the external transmission function of the first chip 11. The chip package structure 1 realizes the interconnection between the first chip 11 and the second chip 12 by directly connecting the first connection pin 1111 and the third connection pin 1211, cancels the adapter plate structure in the background technology, reduces the cost of the chip package structure 1, and makes the manufacturing and assembly process of the chip package structure 1 simpler and more efficient; at the same time, the cancellation of the adapter plate structure can also effectively reduce the volume of the chip package structure 1, which is convenient for the layout of the chip package structure 1. The direct connection between the first connection pin 1111 and the third connection pin 1211 reduces the transmission distance of the signal inside the package, thereby reducing the attenuation of the signal and the mutual interference between the signals.

[0031] According to an embodiment of the present invention, the first connection area 111 and the third connection area 121 are at least partially opposite in the second direction. When the first chip 11 and the second chip 12 are packaged, the relative positions of the first chip 11 and the second chip 12 can be adjusted so that the first connection area 111 and the third connection area 121 are opposite in the second direction, which facilitates the direct connection of the first connection pin 1111 and the third connection pin 1211, without the need for a wiring method such as avoidance and bending. The connection method in which the first connection pin 1111 and the third connection pin 1211 are opposite in the second direction can further shorten the distance of signal transmission between the first chip 11 and the second chip 12, and reduce signal attenuation. The packaging method in which the first connection area 111 and the third connection area 121 are at least partially opposite in the second direction can maximize the use of the space on the chip surface, so that the alignment between the first connection pin 1111 and the third connection pin 1211 is more accurate and efficient, which helps to reduce errors and complexity in the connection process and improve the manufacturing accuracy and reliability of the package. In addition, the design that the first connection area 111 and the third connection area 121 are at least partially opposite in the second direction allows the first chip 11 and the second chip 12 to overlap in the second direction, thereby reducing the width of the chip packaging structure 1 in the first direction and making the entire chip packaging structure 1 more compact.

[0032] According to an embodiment of the present invention, the chip packaging structure 1 further includes: a substrate 13, which is disposed on a side of the second chip 12 away from the first chip 11, the substrate 13 is connected to an external signal, and the second connection pin 1121 is connected to the substrate 13. Figure 1 As shown, the substrate 13 is arranged on the side of the second chip 12 away from the first chip 11, and is connected to the external signal. During packaging, the second connection pin 1121 arranged in the second connection area 112 can be connected to the substrate 13, and the substrate 13 can be connected to an external power supply or other signal transmission structure. For example, when the substrate 13 is connected to an external power supply, the electrical signal generated by the power supply can be transmitted to the first chip 11 through the substrate 13 and the second connection pin 1121, and the first chip 11 can also transmit the electrical signal to the second chip 12, so that the entire chip packaging structure 1 can work normally. The second connection pin 1121 is connected to the external signal through the substrate 13, providing a reliable electrical interface for the chip packaging structure 1, so that the chip can receive and send signals normally.

[0033] In some embodiments, the connection points on the substrate 13 can be flexibly configured according to actual needs to adapt to different signal and power requirements, so that the chip packaging structure 1 can be easily integrated into various systems.

[0034] In some embodiments, the substrate 13 can also play a role in heat dissipation, helping to disperse the heat generated by the chip during operation, thereby improving the reliability and service life of the chip.

[0035] According to an embodiment of the present invention, the first chip 11, the second chip 12 and the substrate 13 are at least partially overlapped in the second direction. During packaging, the first chip 11, the second chip 12 and the substrate 13 may be partially overlapped in the second direction. By overlapping the chips, the occupied space of the chip packaging structure 1 in the second direction may be effectively reduced, which is conducive to the integration and miniaturization of the chip packaging structure 1.

[0036] According to one embodiment of the present invention, the first connection area 111 and the third connection area 121 are respectively constructed as a plurality of one-to-one corresponding ones, each first connection area 111 is provided with a plurality of first connection pins 1111 spaced apart from each other, each third connection area 121 is provided with a plurality of third connection pins 1211 spaced apart from each other, and each third connection pin 1211 is connected to the corresponding first connection pin 1111.

[0037] The first chip 11 has a plurality of first connection areas 111 and third connection areas 121 that correspond to each other one by one, so that the chip package structure 1 has more flexibility in layout. The first chip 11 has multiple independent connection areas, each of which can undertake specific signal transmission or power supply tasks, thereby enhancing the expansibility and functional diversity of the entire package structure. A plurality of first connection pins 1111 spaced from each other are arranged in each first connection area 111. Similarly, a plurality of third connection pins 1211 spaced from each other are also arranged in each third connection area 121. The design of spacing arrangement helps to reduce electromagnetic interference between pins and optimize signal transmission quality. At the same time, the use of multiple connection pins can disperse current or signal load, reduce the risk of overheating of a single pin, and improve the stability and reliability of the system. Each third connection pin 1211 is connected to the corresponding first connection pin 1111. This one-to-one connection mode ensures that the signal or power can be accurately transmitted between the first chip 11 and the second chip 12. The design of multi-pin correspondence also provides redundancy. Even if a pin fails, other pins can still maintain connection, thereby enhancing the connection reliability of the entire package structure.

[0038] According to one embodiment of the present invention, a plurality of first connection areas 111 are arranged at intervals on at least part of the periphery of the second connection area 112. Since a plurality of first connection areas 111 and at least one second connection area 112 are provided on the first chip 11, the arrangement positions of the first connection areas 111 and the second connection areas 112 will affect the performance of the entire chip packaging structure 1. Specifically, arranging a plurality of first connection areas 111 at intervals on at least part of the periphery of the second connection area 112 can more effectively utilize the space within the packaging structure. Compared with concentrating all the connection areas together, this dispersed layout can leave more space for other components (such as capacitors, resistors, etc.) or signal paths, thereby improving the compactness and integration of the entire packaging structure. The first connection areas 111 arranged at intervals can reduce electromagnetic interference, reduce signal distortion and noise, and also help reduce the mechanical stress concentration caused by too dense connection areas, thereby improving the reliability of the connection pins.

[0039] According to an embodiment of the present invention, the second chips 12 are configured to be multiple and spaced apart from each other in the first direction, and a second connecting pin 1121 is disposed between two adjacent second chips 12. Figure 1 As shown, the plurality of second chips 12 are arranged at intervals in the first direction, which can improve the air circulation inside the chip packaging structure 1, thereby improving the heat dissipation efficiency. A second connecting pin 1121 is provided between two adjacent second chips 12, that is, the second connecting pin 1121 can extend in the gap between the two adjacent second chips 12 and be connected to the substrate 13, which can make full use of the space of the chip packaging structure 1 and improve the packaging density and integration of the chip.

[0040] According to one embodiment of the present invention, the second connection pins 1121 are configured as a plurality of second connection pins 1121 spaced apart from each other, and the plurality of second connection pins 1121 are arranged in multiple columns in the first direction. The second connection pins 1121 are configured as a plurality of second connection pins 1121 spaced apart from each other, and arranged in multiple columns in the first direction, thereby improving the connection density, so that the chip packaging structure 1 can accommodate more second connection pins 1121 in a limited space, and different second connection pins 1121 can have different functions, so that the chip packaging structure 1 supports more signal channels and power / ground connections. The second connection pins 1121 arranged in multiple columns help to optimize the signal transmission path and the power management network. By reasonably arranging the position and number of the pins, signal interference and transmission delay can be reduced, while ensuring the stability and efficiency of the power supply, so as to support more complex signal processing and faster data transmission rates.

[0041] According to one embodiment of the present invention, a plurality of external connection terminals 131 spaced apart from each other are provided on the side of the substrate 13 facing away from the second chip 12, and the plurality of external connection terminals 131 are arranged in multiple rows and columns on the substrate 13. The arrangement of multiple rows and columns can arrange more external connection terminals 131 on a limited area of ​​the substrate 13, thereby improving the connection density between the entire packaging structure and the external circuit or other components, which is conducive to the realization of miniaturized and highly integrated electronic device design. At the same time, the plurality of external connection terminals 131 provide a variety of connection options. During actual assembly, part or all of the external connection terminals 131 can be selectively used to connect one or more external electronic devices according to specific application requirements. The flexibility of the external connection terminals 131 can enable the chip packaging structure 1 to adapt to different circuit layouts and connection requirements, thereby improving the versatility of the chip packaging structure 1.

[0042] According to an embodiment of the present invention, the device further comprises: a protective layer 14, the protective layer 14 covers at least a portion of the periphery of the first chip 11 and the second chip 12. Figure 1 As shown, the periphery of the first chip 11 and the second chip 12 is coated with a protective layer 14, which can effectively prevent the chips from being physically damaged by the outside, such as scratches, impacts or wear, etc., thereby improving the durability and reliability of the chips. At the same time, the protective layer 14 can be made of insulating and corrosion-resistant materials to provide a certain environmental isolation effect for the chips, prevent moisture, dust, chemicals and other harmful substances from invading the chip packaging structure 1, thereby extending the service life of the chip packaging structure 1.

[0043] In some embodiments, the protection layer 14 may be organic.

[0044] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0045] In the description of the present invention, "first feature" or "second feature" may include one or more of the features.

[0046] In the description of the present invention, "plurality" means two or more.

[0047] In the description of the present invention, a first feature being “on” or “under” a second feature may include that the first and second features are directly in contact with each other, or may include that the first and second features are not in direct contact with each other but are in contact with each other via another feature therebetween.

[0048] In the description of the present invention, “on”, “over” and “above” a first feature from a second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.

[0049] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0050] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that: include: A first chip (11), wherein a first connection area (111) and a second connection area (112) spaced apart from each other in a first direction are formed on the first chip (11), a first connection pin (1111) extending in a second direction is arranged in the first connection area (111), and a second connection pin (1121) extending in the second direction is arranged in the second connection area (112); a second chip (12), the second chip (12) being arranged on one side of the first chip (11) in the second direction, a third connection area (121) being formed on the second chip (12), and a third connection pin (1211) extending in the second direction being arranged in the third connection area (121); wherein The first connecting pin (1111) is connected to the third connecting pin (1211), and the first direction is orthogonal to the second direction.

2. The chip packaging structure according to claim 1, characterized in that: The first connection area (111) and the third connection area (121) are at least partially opposite to each other in the second direction.

3. The chip packaging structure according to claim 2, characterized in that: Also includes: A substrate (13), the substrate (13) being arranged on a side of the second chip (12) facing away from the first chip (11), the substrate (13) being connected to an external signal, and the second connecting pin (1121) being connected to the substrate (13).

4. The chip packaging structure according to claim 3, characterized in that: The first chip (11), the second chip (12) and the substrate (13) are arranged to at least partially overlap in the second direction.

5. The chip packaging structure according to claim 4, characterized in that: The first connection area (111) and the third connection area (121) are respectively constructed as a plurality of mutually corresponding first connection pins (1111) each arranged in the first connection area (111), and a plurality of mutually spaced third connection pins (1211) each arranged in the third connection area (121), and each third connection pin (1211) is connected to the corresponding first connection pin (1111).

6. The chip packaging structure according to claim 3, characterized in that: A plurality of the first connection areas (111) are arranged at intervals on at least a portion of the periphery of the second connection area (112).

7. The chip packaging structure according to claim 6, characterized in that: The second chips (12) are configured as a plurality of chips spaced apart from each other in the first direction, and a second connecting pin (1121) is provided between two adjacent second chips (12).

8. The chip packaging structure according to claim 5, characterized in that: The second connecting pins (1121) are configured as a plurality of second connecting pins spaced apart from each other, and the plurality of second connecting pins (1121) are arranged in a plurality of rows in a first direction.

9. The chip packaging structure according to claim 5, characterized in that: A plurality of external connection terminals (131) spaced apart from each other are provided on a side of the substrate (13) facing away from the second chip (12); the plurality of external connection terminals (131) are arranged in a plurality of rows and columns on the substrate (13).

10. The chip packaging structure according to claim 1, characterized in that: Also includes: A protective layer (14), the protective layer (14) covers at least a portion of the periphery of the first chip (11) and the second chip (12).

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