Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises an interlayer dielectric layer and at least one metal layer located in the interlayer dielectric layer, and the metal layer comprises at least one metal wire and a plurality of protruding parts; the metal wire extends in the direction parallel to the plane of the interlayer dielectric layer, and in the extending direction of the metal wire, the multiple protruding parts are arranged on the two sides of the metal wire at intervals and connected with the metal wire.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] When direct current passes through a conductor, the material transfer caused by the gradual movement of atoms in the conductor is called electron migration (EM). Its inherent mechanism is the momentum transfer between the conductive electrons and the diffused metal atoms. When electron migration occurs, part of the momentum of a moving electron is transferred to the adjacent activated atom, which causes the atom to move away from its original position.

[0003] As the integration of semiconductor structures (such as chips) increases, the metal layers of the semiconductor structures become finer, narrower and thinner. Therefore, the current density therein is also increasing, intensifying the movement of metal atoms caused by electron migration, forming voids or whiskers in the metal layer, causing the metal layer to open or short-circuit, resulting in electron migration failure. Summary of the invention

[0004] The present disclosure provides a semiconductor structure, including:

[0005] An interlayer dielectric layer and at least one metal layer located in the interlayer dielectric layer, the metal layer comprising: at least one metal wire and a plurality of protrusions; the metal wire extends in a direction parallel to the plane of the interlayer dielectric layer, and in the extending direction of the metal wire, the plurality of protrusions are respectively arranged at intervals on both sides of the metal wire and connected to the metal wire.

[0006] In some embodiments, the metal wire is used to transmit current, and along the transmission direction of the current in the metal wire, the arrangement density of the protrusions located on both sides of the metal wire gradually increases.

[0007] In some embodiments, the protrusion has a side wall protruding from the metal wire connected thereto, and the side wall is in a curved shape.

[0008] In some embodiments, the same metal layer includes a plurality of the metal wires, the plurality of the metal wires include a first metal wire and a second metal wire having the same extension direction, the first metal wire and the second metal wire are adjacently arranged in a direction perpendicular to the extension direction of the first metal wire and parallel to the plane of the interlayer dielectric layer; the plurality of the protrusions include a plurality of first protrusions connected to the first metal wire and located on a side of the first metal wire close to the second metal wire, and a plurality of second protrusions connected to the second metal wire and located on a side of the second metal wire close to the first metal wire, and in a direction perpendicular to the extension direction of the first metal wire and parallel to the plane of the interlayer dielectric layer, the projections of the first protrusions and the second protrusions do not overlap.

[0009] In some embodiments, in the extension direction of the metal wire, a distance between two adjacent protrusions located on the same side of the metal wire is greater than or equal to a line width of the metal wire connected thereto.

[0010] In some embodiments, the width of the protrusion in the extension direction of the metal line is less than or equal to the line width of the metal line connected to it; and / or the width of the protrusion in a direction perpendicular to the extension direction of the metal line and parallel to the plane of the interlayer dielectric layer is less than or equal to half the line width of the metal line connected to it.

[0011] In some embodiments, the number of the metal layers is multiple; the semiconductor structure further includes: a conductive plug located in the interlayer dielectric layer for connecting two adjacent metal layers, and the metal layers and the conductive plugs are alternately distributed in a direction perpendicular to the plane of the interlayer dielectric layer.

[0012] The present disclosure also provides a method for manufacturing a semiconductor structure, including:

[0013] An interlayer dielectric layer is formed, and at least one metal layer is formed in the interlayer dielectric layer, wherein the metal layer is formed by: forming at least one metal line and a plurality of protrusions; the metal line extends in a direction parallel to the plane of the interlayer dielectric layer, and in the extending direction of the metal line, the plurality of protrusions are respectively arranged at intervals on both sides of the metal line and connected to the metal line.

[0014] In some embodiments, forming the metal line and the plurality of protrusions located on both sides of the metal line includes:

[0015] Etching the interlayer dielectric layer to form a trench structure extending in a direction parallel to the plane of the interlayer dielectric layer, and a plurality of sub-trenches located on both sides of the trench structure along the extending direction of the trench structure, wherein the sub-trench is connected to the trench structure;

[0016] A conductive material is filled in the trench structure and the sub-trench to form the metal line and the protrusion respectively.

[0017] In some embodiments, the number of the metal layers is multiple; the manufacturing method further includes: forming a conductive plug in the interlayer dielectric layer, the conductive plug is used to connect two adjacent metal layers, and the metal layers and the conductive plug are alternately distributed in a direction perpendicular to the plane of the interlayer dielectric layer.

[0018] The semiconductor structure and manufacturing method thereof provided by the embodiment of the present disclosure, wherein the semiconductor structure comprises: an interlayer dielectric layer and at least one metal layer located in the interlayer dielectric layer, the metal layer comprises: at least one metal wire and a plurality of protrusions; the metal wire extends in a direction parallel to the plane of the interlayer dielectric layer, and in the extending direction of the metal wire, a plurality of the protrusions are arranged at intervals on both sides of the metal wire and connected to the metal wire. The protrusions provided by the embodiment of the present disclosure can act as a reservoir, and when a void caused by electron migration effect is generated in the metal wire near the protrusion, the atoms in the protrusion can be added into the void, thereby alleviating the occurrence of the electron migration effect; the generation position of the void in the metal wire is random, and the embodiment of the present disclosure respectively arranges a plurality of protrusions arranged at intervals on both sides of the metal wire, which can effectively reduce or eliminate the void caused by the electron migration effect; in addition, the arrangement of a plurality of protrusions can increase the heat dissipation area of ​​the metal layer, increase the heat dissipation efficiency of the metal layer, thereby indirectly alleviating the occurrence of the electron migration effect.

[0019] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, Figure 2 for Figure 1 A schematic diagram of a partial top view of two adjacent metal layers; Figure 3 for Figure 2 A schematic diagram of the three-dimensional structure of some metal wires in two adjacent metal layers; Figure 4 , Figure 5 as well as Figure 6 They are Figure 1Different examples of structural diagrams of metal wires;

[0022] Figure 7 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0023] Figures 8a to 9b as well as Fig.10 A process flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; wherein: Figure 8b and Figure 9b They are Figure 8a and Figure 9a Schematic top view of the local area Q in . DETAILED DESCRIPTION

[0024] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0026] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0027] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0028] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] When direct current passes through a conductor, the material transfer caused by the gradual movement of atoms in the conductor is called electron migration (EM). Its inherent mechanism is the momentum transfer between the conductive electrons and the diffused metal atoms. When electron migration occurs, part of the momentum of a moving electron is transferred to the adjacent activated atom, which causes the atom to move away from its original position.

[0031] As the integration of semiconductor structures (such as chips) increases, the metal layers of semiconductor structures become finer, narrower, and thinner. Therefore, the current density therein is also increasing, which aggravates electron migration and causes electron migration failure. Electron migration failures include: electron migration causes fractures or gaps in conductors (especially narrow wires) due to mass deficiency, which prevents current from flowing. Such fractures or gaps are called voids or internal failures, i.e., open circuits. Electron migration can also cause metal atoms in a conductor to migrate and produce mass accumulation in local areas and drift to adjacent conductors to form unexpected electrical connections. Such defects are called hillock failures or whisker failures, i.e., short circuits. Both of the above defects can cause circuit failures. Among them, the vast majority of electron migration failures are caused by the appearance of voids somewhere in the conductor, where the resistance increases, the Joule heat increases, and eventually electron migration failures occur.

[0032] Based on this, the following technical solutions of the embodiments of the present invention are proposed.

[0033] The metal layer provided by the embodiment of the present disclosure includes a metal wire, and a plurality of protrusions arranged on both sides of the metal wire along the extension direction of the metal wire and connected to the metal wire. The protrusions can act as a water reservoir. When voids caused by electron migration effect are generated in the metal wire near the protrusions, atoms in the protrusions can be added to the voids, thereby alleviating the occurrence of the electron migration effect. The generation position of the voids in the metal wire is random. The embodiment of the present disclosure arranges a plurality of protrusions arranged at intervals on both sides of the metal wire, which can effectively reduce or eliminate the voids caused by the electron migration effect. In addition, the arrangement of the plurality of protrusions can increase the heat dissipation area of ​​the metal layer and increase the heat dissipation efficiency of the metal layer, thereby indirectly alleviating the occurrence of the electron migration effect.

[0034] In order to make the above-mentioned purposes, features and advantages of the present invention more clearly understood, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the convenience of explanation, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention.

[0035] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, Figure 2 for Figure 1A schematic diagram of a partial top view of two adjacent metal layers; Figure 3 for Figure 2 A schematic diagram of the three-dimensional structure of some metal wires in two adjacent metal layers; Figure 4 , Figure 5 as well as Figure 6 They are Figure 1 Different examples of schematic diagrams of the structure of the metal wire; wherein, Figure 2 for Figure 1 A partial top view schematic diagram of the third metal layer and the fourth metal layer; Figure 3 for Figure 2 Schematic diagram of the three-dimensional structure of some metal wires in the third metal layer and the fourth metal layer. Figures 1 to 6 The semiconductor structure provided by the embodiment of the present disclosure is further described in detail.

[0036] like Figures 1 to 3 As shown, an embodiment of the present disclosure provides a semiconductor structure, including: an interlayer dielectric layer 11 and at least one metal layer 12 located in the interlayer dielectric layer 11, the metal layer 12 includes: at least one metal wire 13 and a plurality of protrusions 14; the metal wire 13 extends in a direction parallel to the plane of the interlayer dielectric layer 11, and in the extending direction of the metal wire 13, the plurality of protrusions 14 are respectively arranged at intervals on both sides of the metal wire 13 and connected to the metal wire 13.

[0037] like Figure 1 As shown, in some embodiments, the semiconductor structure further includes a substrate 10 , and an interlayer dielectric layer 11 may be formed on the substrate 10 .

[0038] Here, the substrate 10 may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, such as silicon. In some embodiments, the semiconductor structure may be a memory chip, and the substrate 10 may have structures such as a memory array and a peripheral circuit.

[0039] In some embodiments, the interlayer dielectric layer 11 is not a single-layer structure, but a multi-layer structure formed by insulating materials in multiple process steps. The material of the interlayer dielectric layer 11 includes one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), oxynitrides (e.g., silicon oxynitride), and the like.

[0040] like Figure 1As shown, in some embodiments, there are multiple metal layers 12, and the multiple metal layers 12 are sequentially distributed in the interlayer dielectric layer 11 along a direction perpendicular to the interlayer dielectric layer 11. In some embodiments, the semiconductor structure further includes: a conductive plug 15, which is located in the interlayer dielectric layer 11 and is used to connect two adjacent metal layers 12, and the metal layers 12 and the conductive plugs 15 are alternately distributed along a direction perpendicular to the plane of the interlayer dielectric layer 11.

[0041] In some embodiments, the material of the conductive plug 15 includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy.

[0042] Figure 1 The number of metal layers 12 shown in the figure is 4, namely, the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4, and the first metal layer M1 to the fourth metal layer M4 are arranged in sequence along a direction away from the substrate 10 and perpendicular to the plane of the interlayer dielectric layer 11. However, it is not limited thereto, and the number of metal layers 12 can also be more or less, such as 2 layers, 3 layers, 5 layers, 8 layers or more layers. Here, the plane of the interlayer dielectric layer 11 is parallel to the plane of the substrate 10.

[0043] like Figure 1 and Figure 2 As shown, in some embodiments, each metal layer 12 may include a plurality of metal wires 13, and the extension directions of any two metal wires 13 among the plurality of metal wires 13 may be the same or different, and any two metal wires 13 may be connected or spaced apart.

[0044] like Figure 2 and Figure 3 As shown, in the embodiment of the present disclosure, in the extension direction of the metal wire 13, a plurality of protrusions 14 are arranged on both sides of the metal wire 13, and the plurality of protrusions 14 are arranged at intervals on the side walls of the metal wire 13. The protrusions 14 can act as a water reservoir. When voids caused by the electron migration effect are generated in the metal wire 13 near the protrusions 14, the atoms in the protrusions 14 can be added to the voids, thereby alleviating the occurrence of the electron migration effect; at the same time, the generation position of the voids in the metal wire 13 is random. In the embodiment of the present disclosure, a plurality of protrusions 14 arranged at intervals are respectively arranged on both sides of the metal wire 13, which can effectively reduce or eliminate the voids caused by the electron migration effect; in addition, the setting of the protrusions 14 can increase the heat dissipation area of ​​the metal layer 12, increase the heat dissipation efficiency of the metal layer 12, thereby indirectly alleviating the occurrence of the electron migration effect.

[0045] It can be understood that the denser the arrangement of the multiple protrusions 14 on any side of the metal line 13, the better the effect of alleviating the electron migration effect, and the better the heat dissipation effect of the metal layer 12; however, if the arrangement of the protrusions 14 is too dense, the parasitic capacitance, electrical interference or crosstalk between adjacent protrusions 14 may increase, thereby reducing the performance of the semiconductor structure. In some embodiments, in the extension direction of the metal line 13, the spacing L1 between two adjacent protrusions 14 located on the same side of the metal line 13 is greater than or equal to the line width L0 of the metal line 13 connected thereto. By controlling the spacing L1 between the two adjacent protrusions 14 in the extension direction of the metal line 13 within the above range, the parasitic capacitance, electrical interference or crosstalk between the adjacent protrusions 14 can be reduced, thereby improving the performance of the semiconductor structure. Here, the line width of the metal line 13 refers to the width of the metal line 13 in a direction perpendicular to the extension direction of the metal line 13 and parallel to the plane of the interlayer dielectric layer 11.

[0046] It is understandable that the larger the size of the protrusion 14, the better the effect of alleviating the electron migration effect and the better the heat dissipation effect. However, the size of the protrusion 14 cannot be too large to avoid reducing the integration of the semiconductor structure. In some embodiments, the width L2 of the protrusion 14 in the extension direction of the metal line 13 is less than or equal to the line width L0 of the metal line 13 connected thereto; and / or, the width L3 of the protrusion 14 in the direction perpendicular to the extension direction of the metal line 13 and parallel to the plane of the interlayer dielectric layer 11 is less than or equal to half of the line width L0 of the metal line 13 connected thereto; such a setting can ensure that the protrusion 14 has a suitable size on the one hand to effectively alleviate the electron migration effect, and on the other hand, the protrusion 14 is not too large to reduce the integration of the semiconductor structure.

[0047] In some embodiments, the height of the protrusion 14 is the same as the height of the metal line 13 connected thereto. However, the height of the protrusion 14 may also be less than or greater than the height of the metal line 13 connected thereto to increase the applicability of the scene. The height here refers to the extension length of the protrusion 14 and the metal line 13 in the direction perpendicular to the plane of the interlayer dielectric layer 11.

[0048] In some embodiments, the cross-sectional shape of the protrusion 14 along the direction parallel to the plane of the interlayer dielectric layer 11 can be a regular shape or an irregular shape, for example, it can include a polygon such as a triangle, a quadrilateral, a pentagon, or one or a combination of irregular shapes.

[0049] like Figure 4As shown, in some embodiments, the protrusion 14 has a side wall SW protruding from the metal wire 13 connected thereto, and the shape of the side wall SW is a curved surface, that is, the shape of the protrusion 14 is surrounded by the side wall SW in the shape of a curved surface and the metal wire 13, and the portion of the protrusion 14 protruding from the metal wire 13 has no sharp corners. In this way, compared with the shape of the portion of the protrusion 14 protruding from the metal wire 13 having a sharp corner (for example, the cross-sectional shape of the protrusion 14 along the direction parallel to the plane of the interlayer dielectric layer 11 is a triangle, a quadrilateral, a pentagon, etc.), the problem of breakdown caused by high electric field strength at the sharp corner due to the tip effect is avoided, thereby improving the performance of the semiconductor structure.

[0050] In actual operation, the metal wire 13 is used to transmit current. The applicant has found through research that the probability of generating voids caused by the electron migration effect is related to the transmission direction of the current in the metal wire 13. In the area close to the positive end of the current direction, the probability of generating voids decreases, and in the area close to the negative end of the current direction, the probability of generating voids increases. Figure 5 As shown, in some embodiments of the present disclosure, along the transmission direction of the current in the metal wire 13, the arrangement density of the protrusions 14 located on both sides of the metal wire 13 gradually increases. In this way, the arrangement density of the protrusions 14 can be set in a targeted manner according to the probability of void generation. On the one hand, it can effectively alleviate the electron migration effect, and on the other hand, it can save wiring resources.

[0051] Here, the arrangement density of the protrusions 14 refers to the average arrangement density of the protrusions 14 located on both sides of the metal wire 13. For example, it can be set that along the transmission direction of the current in the metal wire 13, the arrangement density of the protrusions 14 located on both sides of the metal wire 13 gradually increases, or the protrusions 14 on one side are evenly arranged, and the arrangement density of the protrusions 14 on the other side gradually increases.

[0052] like Figure 6As shown, in some embodiments, the plurality of metal lines 13 of the same metal layer 12 include a first metal line 131 and a second metal line 132 extending in the same direction, and the first metal line 131 and the second metal line 132 are arranged adjacent to each other in a direction perpendicular to the extending direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11; the plurality of protrusions 14 include a plurality of first protrusions 141 connected to the first metal line 131 and located on a side of the first metal line 131 close to the second metal line 132, and a plurality of first protrusions 142 connected to the second metal line 132 and located on a side of the second metal line 132 close to the first metal line 131. For the multiple second protrusions 142 on one side of the metal line 131, in a direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11, the projections of the first protrusions 141 and the second protrusions 142 do not overlap, that is, in a direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11, the projections of one or more first protrusions 141 are located between the projections of two adjacent second protrusions 142, and / or the projections of one or more second protrusions 142 are located between the projections of two adjacent first protrusions 141.

[0053] In this way, on the one hand, the parasitic capacitance, electrical interference or crosstalk between the first protrusion 141 and the second protrusion 142 can be reduced; on the other hand, a closer distance can be allowed between the first metal line 131 and the second metal layer 132, thereby improving the integration of the semiconductor structure; on the other hand, in a direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11, the first protrusion 141 and the second protrusion 142 can be set to have a larger size, thereby increasing the effect of the first protrusion 141 and the second protrusion 142 in alleviating the electron migration effect.

[0054] like Figure 6 As shown, in a direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11, when there is no overlap between the projections of the first protrusion 141 and the second protrusion 142, the distance L4 between the first protrusion 141 and the second protrusion 142 can be greater than or equal to 0, that is, the projections of the first protrusion 141 and the second protrusion 142 in the extension direction of the first metal line 131 do not overlap; but not limited to this, in the extension direction of the first metal line 131, the projections of the first protrusion 141 and the second protrusion 142 can also partially overlap to increase the integration level or the size of the first protrusion 141 and the second protrusion 142.

[0055] Here, the extending direction of the first metal line 131 corresponds to Figure 6 The first direction in the direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11 corresponds to Figure 6 The second direction in .

[0056] But not limited to this, in a direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11, the projections of the first protrusion 141 and the second protrusion 142 may also partially overlap or completely overlap. In this case, L4 is greater than 0 to avoid a short circuit between the first protrusion 141 and the second protrusion 142 to increase scenario applicability.

[0057] In some embodiments, the material of the metal wire 13 and the protrusion 14 includes a metal material, and the material of the metal wire 13 and the protrusion 14 can be the same or different. Specifically, the material of the metal wire 13 and the protrusion 14 includes one or more of copper (Cu), cobalt (Co), aluminum (Al), and silver (Ag).

[0058] The present disclosure also provides a method for manufacturing a semiconductor structure. Figure 7 As shown, the method comprises the following steps:

[0059] Step S101, forming an interlayer dielectric layer, and forming at least one metal layer in the interlayer dielectric layer, the forming of the metal layer includes: forming at least one metal wire and a plurality of protrusions; the metal wire extends in a direction parallel to the plane of the interlayer dielectric layer, and in the extending direction of the metal wire, the plurality of protrusions are respectively arranged at intervals on both sides of the metal wire and connected to the metal wire.

[0060] Next, combine Figures 8a to 9b as well as Fig.10 The method for manufacturing the semiconductor structure according to the embodiment of the present disclosure is further described in detail.

[0061] Execute step S101, such as Figures 8a to 9b , Fig.10 as well as Figure 1 As shown, an interlayer dielectric layer 11 is formed, and at least one metal layer 12 is formed in the interlayer dielectric layer 11; the formation of the metal layer 12 includes: forming at least one metal wire 13 and a plurality of protrusions 14; the metal wire 13 extends in a direction parallel to the plane of the interlayer dielectric layer 11, and in the extending direction of the metal wire 13, the plurality of protrusions 14 are respectively arranged at intervals on both sides of the metal wire 13 and connected to the metal wire 13.

[0062] See again Figure 8a In some embodiments, before forming the interlayer dielectric layer 11 , the method further includes: providing a substrate 10 , and forming the interlayer dielectric layer 11 on the substrate 10 .

[0063] Here, the substrate 10 may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, such as silicon. In some embodiments, the semiconductor structure may be a memory chip, and the substrate 10 may have structures such as a memory array and a peripheral circuit.

[0064] In some embodiments, the interlayer dielectric layer 11 is not a single-layer structure, but a multi-layer structure formed by insulating materials in multiple process steps. The material of the interlayer dielectric layer 11 includes one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), oxynitrides (e.g., silicon oxynitride), and the like.

[0065] See again Figures 8a to 9b In some embodiments, forming a metal line 13 and a plurality of protrusions 14 located on both sides of the metal line 13 includes:

[0066] The interlayer dielectric layer 11 is etched to form a trench structure T1 extending in a direction parallel to the plane of the interlayer dielectric layer 11, and a plurality of sub-trench T2 located on both sides of the trench structure T1 along the extending direction of the trench structure T1, and the sub-trench T2 is connected to the trench structure T1 (such as Figure 8a and Figure 8b );

[0067] Conductive materials are filled in the trench structure T1 and the sub-trench T2 to form metal lines 13 and protrusions 14 (such as Figure 9a and Figure 9b ).

[0068] In some embodiments, the material of the metal wire 13 and the protrusion 14 includes a metal material, and the material of the metal wire 13 and the protrusion 14 can be the same or different. Specifically, the material of the metal wire 13 and the protrusion 14 includes one or more of copper (Cu), cobalt (Co), aluminum (Al), and silver (Ag).

[0069] In some embodiments, the sub-groove T2 has the same depth as the trench structure T1 connected thereto, and the two are formed in a unified step to simplify the manufacturing process, so that the height of the formed protrusion 14 is the same as the height of the metal line 13 connected thereto. However, it is not limited thereto, and the depth of the sub-groove T2 can also be less than or greater than the depth of the trench structure T1 connected thereto, so that the height of the formed protrusion 14 is less than or greater than the height of the metal line 13 connected thereto, so as to increase the applicability of the scene. The height here refers to the extension length of the protrusion 14 and the metal line 13 in the direction perpendicular to the plane of the interlayer dielectric layer 11.

[0070] In some embodiments, there are multiple metal layers 12; the manufacturing method also includes: forming a conductive plug 15 in the interlayer dielectric layer 11, the conductive plug 15 is used to connect two adjacent metal layers 12, and the metal layers 12 and the conductive plug 15 are alternately distributed in a direction perpendicular to the plane of the interlayer dielectric layer 11.

[0071] Specifically, Fig.10 As shown, forming a conductive plug 15 includes: forming an interlayer dielectric layer 11 covering the metal layer 12; etching the interlayer dielectric layer 11 to form a contact hole V in the interlayer dielectric layer 11 exposing the metal layer 12, and filling the contact hole V with a conductive material to form the conductive plug 15.

[0072] In some embodiments, the material of the conductive plug 15 includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy.

[0073] Next, if Figure 1 As shown, the above method is used to sequentially form more metal layers 12 and conductive plugs 15 located between adjacent metal layers 12 .

[0074] Figure 1 The number of metal layers 12 shown in the figure is 4, namely, a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4, and the first metal layer M1 to the fourth metal layer M4 are arranged in sequence along a direction away from the substrate 10 and perpendicular to the plane of the interlayer dielectric layer 11. However, it is not limited thereto, and the number of metal layers 12 can also be more or less, such as 2 layers, 3 layers, 5 layers, 8 layers or more layers.

[0075] like Figure 1 and Figure 2 As shown, in some embodiments, each metal layer 12 may include a plurality of metal wires 13. The extension directions of any two metal wires 13 among the plurality of metal wires 13 may be the same or different, and any two metal wires 13 may be connected or spaced apart.

[0076] In the embodiment of the present disclosure, a plurality of sub-grooves T2 are formed on both sides of the groove structure T1, and a protrusion 14 is formed in the sub-grooves T2, thereby forming a plurality of protrusions 14 on both sides of the metal wire 13 in the extension direction of the metal wire 13. The plurality of protrusions 14 are arranged at intervals on the side walls of the metal wire 13, and the protrusions 14 can act as a water reservoir. When voids caused by the electron migration effect are generated in the metal wire 13 near the protrusions 14, the atoms in the protrusions 14 can be added to the voids, thereby alleviating the occurrence of the electron migration effect. At the same time, the generation position of the voids in the metal wire 13 is random. In the embodiment of the present disclosure, a plurality of protrusions 14 arranged at intervals are respectively arranged on both sides of the metal wire 13, which can effectively reduce or eliminate the voids caused by the electron migration effect. In addition, the provision of the protrusions 14 can increase the heat dissipation area of ​​the metal layer 12, increase the heat dissipation efficiency of the metal layer 12, thereby indirectly alleviating the occurrence of the electron migration effect.

[0077] It can be understood that the denser the arrangement of the multiple protrusions 14 on any side of the metal line 13, the better the effect of alleviating the electron migration effect, and the better the heat dissipation effect of the metal layer 12; however, if the arrangement of the protrusions 14 is too dense, the parasitic capacitance, electrical interference or crosstalk between adjacent protrusions 14 may increase, thereby reducing the performance of the semiconductor structure. In some embodiments, in the extension direction of the metal line 13, the spacing L1 between two adjacent protrusions 14 located on the same side of the metal line 13 is greater than or equal to the line width L0 of the metal line 13 connected thereto. By controlling the spacing between the two adjacent protrusions 14 in the extension direction of the metal line 13 within the above range, the parasitic capacitance, electrical interference or crosstalk between the adjacent protrusions 14 can be reduced, thereby improving the performance of the semiconductor structure. Here, the line width of the metal line 13 refers to the width of the metal line 13 in a direction perpendicular to the extension direction of the metal line 13 and parallel to the plane of the interlayer dielectric layer 11.

[0078] It is understandable that the larger the size of the protrusion 14, the better the effect of alleviating the electron migration effect and the better the heat dissipation effect. However, the size of the protrusion 14 cannot be too large to avoid reducing the integration of the semiconductor structure. In some embodiments, the width L2 of the protrusion 14 in the extension direction of the metal line 13 is less than or equal to the line width L0 of the metal line 13 connected thereto; and / or, the width L3 of the protrusion 14 in the direction perpendicular to the extension direction of the metal line 13 and parallel to the plane of the interlayer dielectric layer 11 is less than or equal to half of the line width L0 of the metal line 13 connected thereto; such a setting can ensure that the protrusion 14 has a suitable size on the one hand to effectively alleviate the electron migration effect, and on the other hand, the protrusion 14 is not too large to reduce the integration of the semiconductor structure.

[0079] In some embodiments, the cross-sectional shape of the protrusion 14 along the direction parallel to the plane of the interlayer dielectric layer 11 can be a regular shape or an irregular shape, for example, it can include a polygon such as a triangle, a quadrilateral, a pentagon, or one or a combination of irregular shapes.

[0080] like Figure 4 As shown, in some embodiments, the protrusion 14 has a side wall SW protruding from the metal wire 13 connected thereto, and the shape of the side wall SW is a curved surface, that is, the shape of the protrusion 14 is surrounded by the side wall SW in the shape of a curved surface and the metal wire 13, and the portion of the protrusion 14 protruding from the metal wire 13 has no sharp corners. In this way, compared with the shape of the portion of the protrusion 14 protruding from the metal wire 13 having a sharp corner (for example, the cross-sectional shape of the protrusion 14 along the direction parallel to the plane of the interlayer dielectric layer 11 is a triangle, a quadrilateral, a pentagon, etc.), the problem of breakdown caused by high electric field strength at the sharp corner due to the tip effect is avoided, thereby improving the performance of the semiconductor structure.

[0081] In actual operation, the metal wire 13 is used to transmit current. The applicant has found through research that the probability of generating voids caused by the electron migration effect is related to the transmission direction of the current in the metal wire 13. In the area close to the positive end of the current direction, the probability of generating voids decreases, and in the area close to the negative end of the current direction, the probability of generating voids increases. Figure 5 As shown, in some embodiments of the present disclosure, along the transmission direction of the current in the metal wire 13, the arrangement density of the protrusions 14 located on both sides of the metal wire 13 gradually increases. In this way, the arrangement density of the protrusions 14 can be set in a targeted manner according to the probability of void generation. On the one hand, it can effectively alleviate the electron migration effect, and on the other hand, it can save wiring resources.

[0082] Here, the arrangement density of the protrusions 14 refers to the average arrangement density of the protrusions 14 located on both sides of the metal wire 13. For example, it can be set that along the transmission direction of the current in the metal wire 13, the arrangement density of the protrusions 14 located on both sides of the metal wire 13 gradually increases, or the protrusions 14 on one side are evenly arranged, and the arrangement density of the protrusions 14 on the other side gradually increases.

[0083] like Figure 6As shown, in some embodiments, the plurality of metal lines 13 of the same metal layer 12 include a first metal line 131 and a second metal line 132 extending in the same direction, and the first metal line 131 and the second metal line 132 are arranged adjacent to each other in a direction perpendicular to the extending direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11; the plurality of protrusions 14 include a plurality of first protrusions 141 connected to the first metal line 131 and located on a side of the first metal line 131 close to the second metal line 132, and a plurality of first protrusions 141 connected to the second metal line 132 and located on the second metal line 132. For the plurality of second protrusions 142 close to one side of the first metal line 131, in a direction perpendicular to the extending direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11, the projections of the first protrusion 141 and the second protrusion 142 do not overlap, that is, in the direction perpendicular to the extending direction of the first metal line 131, the projections of one or more first protrusions 141 are located between the projections of two adjacent second protrusions 142, and / or the projections of one or more second protrusions 142 are located between the projections of two adjacent first protrusions 141.

[0084] In this way, on the one hand, the parasitic capacitance, electrical interference or crosstalk between the first protrusion 141 and the second protrusion 142 can be reduced; on the other hand, a closer distance can be allowed between the first metal line 131 and the second metal layer 132, thereby improving the integration of the semiconductor structure; on the other hand, in a direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11, the first protrusion 141 and the second protrusion 142 can be set to have a larger size, thereby increasing the effect of the first protrusion 141 and the second protrusion 142 in alleviating the electron migration effect.

[0085] like Figure 6 As shown, in a direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11, when there is no overlap between the projections of the first protrusion 141 and the second protrusion 142, the distance L4 between the first protrusion 141 and the second protrusion 142 can be greater than or equal to 0, that is, the projections of the first protrusion 141 and the second protrusion 142 in the extension direction of the first metal line 131 do not overlap; but not limited to this, in the extension direction of the first metal line 131, the projections of the first protrusion 141 and the second protrusion 142 may also partially overlap, so as to further reduce the parasitic capacitance, electrical interference or crosstalk between the first protrusion 141 and the second protrusion 142, so as to increase the integration or the size of the first protrusion 141 and the second protrusion 142.

[0086] Here, the extending direction of the first metal line 131 corresponds to Figure 6 The first direction in the direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11 corresponds to Figure 6 The second direction in .

[0087] But not limited to this, in a direction perpendicular to the extension direction of the first metal line 131 and parallel to the plane of the interlayer dielectric layer 11, the projections of the first protrusion 141 and the second protrusion 142 may also partially overlap or completely overlap. In this case, L4 is greater than 0 to avoid a short circuit between the first protrusion 141 and the second protrusion 142 to increase scenario applicability.

[0088] It should be noted that those skilled in the art can change the order of the above steps without departing from the protection scope of the present disclosure. The above is only an optional embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: An interlayer dielectric layer and at least one metal layer located in the interlayer dielectric layer, wherein the metal layer comprises: at least one metal line and a plurality of protrusions; The metal line extends in a direction parallel to the plane of the interlayer dielectric layer. In the extending direction of the metal line, a plurality of protrusions are arranged at intervals on both sides of the metal line and connected to the metal line.

2. The semiconductor structure according to claim 1, characterized in that: The metal wire is used to transmit current, and along the transmission direction of the current in the metal wire, the arrangement density of the protrusions located on both sides of the metal wire gradually increases.

3. The semiconductor structure according to claim 1, characterized in that: The protrusion has a side wall protruding from the metal wire connected thereto, and the side wall is in a curved surface shape.

4. The semiconductor structure according to claim 1, characterized in that: The same metal layer includes multiple metal wires, and the multiple metal wires include a first metal wire and a second metal wire having the same extension direction, and the first metal wire and the second metal wire are adjacently arranged in a direction perpendicular to the extension direction of the first metal wire and parallel to the plane of the interlayer dielectric layer; the multiple protrusions include multiple first protrusions connected to the first metal wire and located on the side of the first metal wire close to the second metal wire, and multiple second protrusions connected to the second metal wire and located on the side of the second metal wire close to the first metal wire, and in the direction perpendicular to the extension direction of the first metal wire and parallel to the plane of the interlayer dielectric layer, the projections of the first protrusions and the second protrusions do not overlap.

5. The semiconductor structure according to claim 1, characterized in that: In the extending direction of the metal wire, a distance between two adjacent protrusions located on the same side of the metal wire is greater than or equal to a line width of the metal wire connected thereto.

6. The semiconductor structure according to claim 1, characterized in that The width of the protrusion in the extension direction of the metal line is less than or equal to the line width of the metal line connected to it; and / or the width of the protrusion in a direction perpendicular to the extension direction of the metal line and parallel to the plane of the interlayer dielectric layer is less than or equal to half of the line width of the metal line connected to it.

7. The semiconductor structure according to claim 1, characterized in that: The number of the metal layers is multiple; the semiconductor structure also includes: a conductive plug located in the interlayer dielectric layer for connecting two adjacent metal layers, and the metal layers and the conductive plug are alternately distributed along a direction perpendicular to the plane of the interlayer dielectric layer.

8. A method for manufacturing a semiconductor structure, characterized in that: include: forming an interlayer dielectric layer, and forming at least one metal layer in the interlayer dielectric layer, wherein forming the metal layer comprises: forming at least one metal line and a plurality of protrusions; The metal line extends in a direction parallel to the plane of the interlayer dielectric layer. In the extending direction of the metal line, a plurality of protrusions are arranged at intervals on both sides of the metal line and connected to the metal line.

9. The manufacturing method according to claim 8, characterized in that: The metal line and the plurality of protrusions located on both sides of the metal line are formed, comprising: Etching the interlayer dielectric layer to form a trench structure extending in a direction parallel to the plane of the interlayer dielectric layer, and a plurality of sub-trenches located on both sides of the trench structure along the extending direction of the trench structure, wherein the sub-trench is connected to the trench structure; A conductive material is filled in the trench structure and the sub-trench to form the metal line and the protrusion respectively.

10. The manufacturing method according to claim 8, characterized in that: The number of the metal layers is multiple; the manufacturing method further includes: forming a conductive plug in the interlayer dielectric layer, the conductive plug is used to connect two adjacent metal layers, and the metal layers and the conductive plug are alternately distributed along a direction perpendicular to the plane of the interlayer dielectric layer.

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