Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, the wafer structure comprises a substrate, a pre-bonding structure is arranged on the substrate, the pre-bonding structure comprises an outer dielectric layer covering a central area of the substrate and an annular absorption layer covering an annular peripheral area of the substrate, and the outer dielectric layer is provided with a first dielectric layer and a second dielectric layer; wherein the annular absorber layer adjoins the outer dielectric layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved semiconductor structure and a manufacturing method thereof. Background Art

[0002] Wafer bonding is a process that temporarily or permanently joins two or more wafers. Direct wafer bonding requires overcoming the formation of edge bonding voids, which are caused by the gas pressure drop that occurs at the edge of the wafer during the wafer bonding process. This adiabatic process causes the gas temperature to change, which causes small water droplets to condense near the edge of the wafer.

[0003] In order to avoid such bonding defects, the gas environment during wafer bonding is usually controlled, but the improvement effect is not significant. Therefore, the technical field needs to provide an improved semiconductor structure to avoid the formation of edge bonding gaps during wafer bonding. Summary of the invention

[0004] The main purpose of the present invention is to provide an improved semiconductor structure and a method for manufacturing the same to solve the deficiencies or shortcomings of the prior art.

[0005] On the one hand, the present invention provides a wafer structure, comprising: a substrate; an interconnection structure arranged on the substrate; a cover layer arranged on the interconnection structure; a top dielectric layer arranged on the cover layer; a pre-bonding structure arranged on the top dielectric layer, wherein the pre-bonding structure comprises an inner layer arranged on the top dielectric layer, an outer layer, and an intermediate absorption layer adjacent to the inner layer and arranged along the periphery of the outer layer; and a plurality of copper pads arranged in the pre-bonding structure, the top dielectric layer, and the cover layer.

[0006] According to an embodiment of the present invention, the intermediate absorption layer is exposed in a peripheral region at an edge portion of the wafer structure.

[0007] According to an embodiment of the present invention, the width of the peripheral area is 10 mm.

[0008] According to an embodiment of the present invention, the outer layer does not cover the intermediate absorbent layer in the peripheral area.

[0009] According to an embodiment of the present invention, the intermediate absorption layer comprises a porous dielectric material and has a thickness of 100 to 200 angstroms.

[0010] According to an embodiment of the present invention, the inner layer includes nitrogen-doped silicon carbide and has a thickness of 200 to 2000 angstroms.

[0011] According to an embodiment of the present invention, the outer layer comprises silicon oxynitride and has a thickness of 200 to 800 angstroms.

[0012] According to an embodiment of the present invention, the cap layer includes nitrogen-doped silicon carbide and has a thickness of 500-700 angstroms.

[0013] According to an embodiment of the present invention, the top dielectric layer comprises silicon oxide and has a thickness of 9000-9500 angstroms.

[0014] According to an embodiment of the present invention, the plurality of copper pads penetrate the pre-bonding structure, the top dielectric layer and the capping layer and are electrically connected to the interconnection structure.

[0015] On the other hand, the present invention provides a method for forming a wafer structure, comprising: providing a substrate; forming an interconnection structure on the substrate; forming a cover layer on the interconnection structure; forming a top dielectric layer on the cover layer; forming a pre-bonding structure on the top dielectric layer, wherein the pre-bonding structure comprises an inner layer located on the top dielectric layer, an outer layer, and an intermediate absorption layer adjacent to the inner layer and arranged along the periphery of the outer layer; and forming a plurality of copper pads in the pre-bonding structure, the top dielectric layer, and the cover layer.

[0016] According to an embodiment of the present invention, the intermediate absorption layer is exposed in a peripheral region at an edge portion of the wafer structure.

[0017] According to an embodiment of the present invention, the width of the peripheral area is 10 mm.

[0018] According to an embodiment of the present invention, the outer layer does not cover the intermediate absorbent layer in the peripheral area.

[0019] According to an embodiment of the present invention, the intermediate absorption layer comprises a porous dielectric material and has a thickness of 100 to 200 angstroms.

[0020] According to an embodiment of the present invention, the inner layer includes nitrogen-doped silicon carbide and has a thickness of 200 to 2000 angstroms.

[0021] According to an embodiment of the present invention, the outer layer includes silicon oxynitride and has a thickness of 200 to 800 angstroms.

[0022] According to an embodiment of the present invention, the cap layer includes nitrogen-doped silicon carbide and has a thickness of 500-700 angstroms.

[0023] According to an embodiment of the present invention, the top dielectric layer comprises silicon oxide and has a thickness of 9000-9500 angstroms.

[0024] According to an embodiment of the present invention, the plurality of copper pads penetrate the pre-bonding structure, the top dielectric layer, and the capping layer and are electrically connected to the interconnection structure.

[0025] According to another aspect of the present invention, a wafer structure is provided, comprising: a substrate having a pre-bonded structure thereon, wherein the pre-bonded structure comprises an outer dielectric layer covering a central area of ​​the substrate and an annular absorption layer covering an annular peripheral area of ​​the substrate, wherein the annular absorption layer is adjacent to the outer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of the wafer structure of the present invention;

[0027] Figure 2 For along Figure 1 A schematic cross-sectional view shown by the median tangent line II';

[0028] Figures 3 to 5 is a schematic diagram of a method for forming a wafer structure;

[0029] Figures 6 to 8 A schematic diagram of another method for forming a wafer structure.

[0030] Main component symbols

[0031] 1 Wafer structure

[0032] 100 Substrate

[0033] 101 Semiconductor components

[0034] 110 Interconnection Structure

[0035] 112 Metal conductor

[0036] 114 Dielectric layer

[0037] 120 Covering layer

[0038] 130 Top dielectric layer

[0039] 200 Pre-bonded structure

[0040] 210 outer dielectric layer, outer layer

[0041] 220 annular absorption layer, middle absorption layer

[0042] 230 Inner layer

[0043] 310 Copper pad

[0044] E Edge

[0045] CR Central Area

[0046] PR peripheral area, ring peripheral area

[0047] wWidth DETAILED DESCRIPTION

[0048] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0049] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0050] See also Figure 1 and Figure 2 ,in, Figure 1 The wafer structure of the present invention is illustrated. Figure 2 For along Figure 1 The cross-sectional view shown by the midline I-I'. Figure 1 As shown, the wafer structure 1 of the present invention includes a disc-shaped substrate 100, for example, a silicon substrate or a silicon-on-insulator (SOI) substrate, on which a pre-bonded structure 200 is provided. According to an embodiment of the present invention, the pre-bonded structure 200 includes an outer dielectric layer 210 covering a central region CR of the substrate 100 and an annular absorption layer 220 covering an annular peripheral region PR of the substrate 100. According to an embodiment of the present invention, the annular absorption layer 220 is adjacent to the outer dielectric layer 210. According to an embodiment of the present invention, the width w of the annular peripheral region PR is about 10 mm.

[0051] like Figure 2 As shown, a semiconductor element 101, such as a transistor, but not limited thereto, may be formed on a substrate 100. According to an embodiment of the present invention, an interconnect structure 110 is further formed on the substrate. According to an embodiment of the present invention, for example, the interconnect structure 110 may include a multi-layer metal conductor 112 and a multi-layer dielectric layer 114.

[0052] According to an embodiment of the present invention, a capping layer 120 is provided on the interconnect structure 110. According to an embodiment of the present invention, for example, the capping layer 120 may include nitrogen-doped silicon carbide, but is not limited thereto. According to an embodiment of the present invention, for example, the thickness of the capping layer 120 is about 500 to 700 angstroms. According to an embodiment of the present invention, a top dielectric layer 130 is provided on the capping layer 120. According to an embodiment of the present invention, for example, the top dielectric layer 130 may include silicon oxide. According to an embodiment of the present invention, for example, the thickness of the top dielectric layer 130 is about 9000 to 9500 angstroms.

[0053] like Figure 1 and Figure 2As shown, according to an embodiment of the present invention, the pre-bonded structure 200 is disposed on the top dielectric layer 130. According to an embodiment of the present invention, for example, the pre-bonded structure includes an inner layer 230 disposed on the top dielectric layer 130, an outer layer 210, and an intermediate absorption layer 220 adjacent to the inner layer 230 and disposed along the periphery of the outer layer 210. According to an embodiment of the present invention, the intermediate absorption layer 220 is exposed in the peripheral region PR at the edge portion E of the wafer structure 1. According to an embodiment of the present invention, the outer layer 210 does not cover the intermediate absorption layer 220 in the peripheral region PR.

[0054] exist Figure 2 In the embodiment of the present invention, the intermediate absorbent layer 220 is sandwiched between the inner layer 230 and the outer layer 210, and only the intermediate absorbent layer 220 in the peripheral region PR is exposed. The outer layer 210 has a tapered cross-sectional profile near the peripheral region PR. In another embodiment of the present invention, the intermediate absorbent layer 220 is formed only in the peripheral region PR, the outer layer 210 can directly contact the inner layer 230, and the intermediate absorbent layer 220 will not be sandwiched between the inner layer 230 and the outer layer 210.

[0055] According to an embodiment of the present invention, the middle absorption layer 220 includes a porous dielectric material and has a thickness of about 100 to 200 angstroms. According to an embodiment of the present invention, the middle absorption layer 220 includes an ultra-low dielectric material or a porous material that can easily absorb water vapor. According to an embodiment of the present invention, the inner layer 230 includes nitrogen-doped silicon carbide and has a thickness of about 200 to 2000 angstroms. According to an embodiment of the present invention, the outer layer 210 includes silicon oxynitride and has a thickness of about 200 to 800 angstroms.

[0056] According to an embodiment of the present invention, the wafer structure 1 further includes a plurality of copper pads 310, which are disposed in the pre-bonding structure 200, the top dielectric layer 130 and the cap layer 120. According to an embodiment of the present invention, the plurality of copper pads 310 penetrate the pre-bonding structure 200, the top dielectric layer 130 and the cap layer 120 and are electrically connected to the interconnect structure 110. When wafer bonding is performed, these copper pads 310 will be bonded with the corresponding copper pads of another wafer, and the intermediate absorption layer 220 can absorb or trap water molecules located at the edge E of the wafer, effectively avoiding the generation of edge bonding gaps. At the same time, since the intermediate absorption layer 220 is composed of ultra-low dielectric materials, the electrical properties and performance of the chip can be further improved.

[0057] See also Figures 3 to 5 , which illustrates a method of forming a wafer structure. Figure 3 As shown, a substrate 100 is first provided, for example, a silicon substrate or a silicon-on-insulator substrate. Then, a metallization process is performed to form an interconnect structure 110 on the substrate 100. According to an embodiment of the present invention, for example, the interconnect structure 110 may include a multi-layer metal conductor 112 and a multi-layer dielectric layer 114.

[0058] Then, a capping layer 120 is formed on the interconnect structure 110 by a chemical vapor deposition process. According to an embodiment of the present invention, for example, the capping layer 120 may include nitrogen-doped silicon carbide, but is not limited thereto. According to an embodiment of the present invention, for example, the thickness of the capping layer 120 is about 500 to 700 angstroms.

[0059] Next, a top dielectric layer 130 is formed on the cap layer 120 by a chemical vapor deposition process. According to an embodiment of the present invention, for example, the top dielectric layer 130 may include silicon oxide. According to an embodiment of the present invention, for example, the thickness of the top dielectric layer 130 is about 9000-9500 angstroms.

[0060] Next, a pre-bonded structure 200 is formed on the top dielectric layer 130 by using a chemical vapor deposition process. According to an embodiment of the present invention, the pre-bonded structure 200 includes an inner layer 230, an outer layer 210, and an intermediate absorption layer 220 adjacent to the inner layer 230 and arranged along the periphery of the outer layer 210 on the top dielectric layer 130. According to an embodiment of the present invention, the intermediate absorption layer 220 is exposed in the peripheral region PR at the edge portion E of the wafer structure 1. According to an embodiment of the present invention, the outer layer 210 does not cover the intermediate absorption layer 220 in the peripheral region PR. According to an embodiment of the present invention, the width w of the peripheral region PR is about 10 mm.

[0061] According to an embodiment of the present invention, the middle absorption layer 220 includes a porous dielectric material and has a thickness of about 100 to 200 angstroms. According to an embodiment of the present invention, the middle absorption layer 220 includes an ultra-low dielectric material or a porous material that can easily absorb water vapor. According to an embodiment of the present invention, the inner layer 230 includes nitrogen-doped silicon carbide and has a thickness of about 200 to 2000 angstroms. According to an embodiment of the present invention, the outer layer 210 includes silicon oxynitride and has a thickness of about 200 to 800 angstroms.

[0062] like Figure 4 As shown, the outer layer 210 of the peripheral region PR is removed by a grinding process, such as a chemical mechanical grinding process, to expose the middle absorption layer 220 of the peripheral region PR. At this time, the outer layer 210 has a tapered cross-sectional profile near the peripheral region PR.

[0063] like Figure 5 As shown, a metallization process is then performed to form a plurality of copper pads 310 in the pre-bonding structure 200, the top dielectric layer 130 and the capping layer 120. According to an embodiment of the present invention, the plurality of copper pads 310 penetrate the pre-bonding structure 200, the top dielectric layer 130 and the capping layer 120 and are electrically connected to the interconnection structure 110.

[0064] See also Figures 6 to 8 , which illustrates another method of forming a wafer structure. Figure 6As shown, a substrate 100 is first provided, for example, a silicon substrate or a silicon-on-insulator substrate. Then, a metallization process is performed to form an interconnect structure 110 on the substrate 100. According to an embodiment of the present invention, for example, the interconnect structure 110 may include a multi-layer metal conductor 112 and a multi-layer dielectric layer 114.

[0065] Then, a capping layer 120 is formed on the interconnect structure 110 by a chemical vapor deposition process. According to an embodiment of the present invention, for example, the capping layer 120 may include nitrogen-doped silicon carbide, but is not limited thereto. According to an embodiment of the present invention, for example, the thickness of the capping layer 120 is about 500 to 700 angstroms.

[0066] Next, a top dielectric layer 130 is formed on the cap layer 120 by a chemical vapor deposition process. According to an embodiment of the present invention, for example, the top dielectric layer 130 may include silicon oxide. According to an embodiment of the present invention, for example, the thickness of the top dielectric layer 130 is about 9000-9500 angstroms.

[0067] Next, an inner layer 230 and a patterned outer layer 210 are formed on the top dielectric layer 130 using a chemical vapor deposition process. The inner layer 230 in the peripheral region PR at the edge portion E of the wafer structure 1 is exposed. According to an embodiment of the present invention, the inner layer 230 includes nitrogen-doped silicon carbide and has a thickness of about 200 to 2000 angstroms. According to an embodiment of the present invention, the outer layer 210 includes silicon oxynitride and has a thickness of about 200 to 800 angstroms.

[0068] like Figure 7 As shown, a chemical vapor deposition process or a coating process is then performed to deposit the intermediate absorption layer 220 on the inner layer 230 of the peripheral region PR and the patterned outer layer 210. According to an embodiment of the present invention, the intermediate absorption layer 220 includes a porous dielectric material and has a thickness of about 100 to 200 angstroms. According to an embodiment of the present invention, the intermediate absorption layer 220 includes an ultra-low dielectric material or a porous material that can easily absorb water vapor.

[0069] like Figure 8 As shown, a grinding process, such as a chemical mechanical grinding process, is then performed to remove the intermediate absorption layer 220 located on the patterned outer layer 210, and form the intermediate absorption layer 220 adjacent to the inner layer 230 and arranged along the periphery of the outer layer 210. According to an embodiment of the present invention, the intermediate absorption layer 220 is exposed in the peripheral region PR at the edge portion E of the wafer structure 1. According to an embodiment of the present invention, the outer layer 210 does not cover the intermediate absorption layer 220 in the peripheral region PR.

[0070] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A wafer structure, comprising: substrate; An interconnect structure, disposed on the substrate; a cover layer, disposed on the interconnect structure; a top dielectric layer disposed on the cap layer; a pre-bonded structure disposed on the top dielectric layer, wherein the pre-bonded structure comprises an inner layer disposed on the top dielectric layer, an outer layer, and an intermediate absorbent layer adjacent to the inner layer and disposed along a periphery of the outer layer; as well as A plurality of copper pads are disposed in the pre-bonded structure, the top dielectric layer and the capping layer.

2. The wafer structure according to claim 1, characterized in that: The intermediate absorption layer is exposed in a peripheral area at an edge portion of the wafer structure.

3. The wafer structure according to claim 2, characterized in that: The width of the peripheral area is 10 mm.

4. The wafer structure according to claim 2, characterized in that: The outer layer does not cover the middle absorbent layer in the peripheral region.

5. The wafer structure according to claim 1, characterized in that: The intermediate absorption layer comprises a porous dielectric material and has a thickness of 100 to 200 angstroms.

6. The wafer structure according to claim 1, characterized in that: The inner layer includes nitrogen-doped silicon carbide and has a thickness of 200 to 2000 angstroms.

7. The wafer structure according to claim 1, characterized in that: The outer layer includes silicon oxynitride and has a thickness of 200 to 800 angstroms.

8. The wafer structure according to claim 1, characterized in that: The cap layer includes nitrogen-doped silicon carbide and has a thickness of 500 to 700 angstroms.

9. The wafer structure according to claim 1, characterized in that: The top dielectric layer includes silicon oxide and has a thickness of 9000-9500 angstroms.

10. The wafer structure according to claim 1, characterized in that: The plurality of copper pads penetrate the pre-bonding structure, the top dielectric layer, and the capping layer and are electrically connected to the interconnect structure.

11. A method for forming a wafer structure, comprising: providing a substrate; forming an interconnect structure on the substrate; forming a capping layer on the interconnect structure; forming a top dielectric layer on the cap layer; forming a pre-bonded structure on the top dielectric layer, wherein the pre-bonded structure comprises an inner layer on the top dielectric layer, an outer layer, and an intermediate absorber layer adjacent to the inner layer and disposed along a periphery of the outer layer; as well as A plurality of copper pads are formed in the pre-bonded structure, the top dielectric layer, and the capping layer.

12. The method according to claim 11, characterized in that The intermediate absorption layer is exposed in a peripheral area at an edge portion of the wafer structure.

13. The method according to claim 12, characterized in that The width of the peripheral area is 10 mm.

14. The method according to claim 12, characterized in that The outer layer does not cover the middle absorbent layer in the peripheral region.

15. The method according to claim 11, characterized in that The intermediate absorption layer comprises a porous dielectric material and has a thickness of 100 to 200 angstroms.

16. The method according to claim 11, characterized in that The inner layer includes nitrogen-doped silicon carbide and has a thickness of 200 to 2000 angstroms.

17. The method according to claim 11, characterized in that The outer layer includes silicon oxynitride and has a thickness of 200 to 800 angstroms.

18. The method according to claim 11, characterized in that The cap layer includes nitrogen-doped silicon carbide and has a thickness of 500 to 700 angstroms.

19. The method according to claim 11, characterized in that The top dielectric layer includes silicon oxide and has a thickness of 9000-9500 angstroms.

20. The method according to claim 11, characterized in that The plurality of copper pads penetrate the pre-bonding structure, the top dielectric layer, and the capping layer and are electrically connected to the interconnect structure.

21. A wafer structure comprising: A substrate having a pre-bonded structure thereon, wherein the pre-bonded structure comprises an outer dielectric layer covering a central region of the substrate and an annular absorption layer covering an annular peripheral region of the substrate, wherein the annular absorption layer is adjacent to the outer dielectric layer.

Images