Chip stacking structure and packaging method thereof

Abstract

The invention provides a chip stacking structure and a packaging method thereof, the chip stacking structure comprises a first stacking layer and a second stacking layer bonded with the back surface of the first stacking layer, and the first stacking layer comprises a first substrate located on the front surface and a first rewiring layer located on the back surface on the longitudinal section of the first stacking layer; the first chip and the second chip lamination layer are sequentially arranged on the first substrate, and the first copper column is located on the first substrate; the second stack layer comprises a third chip stack layer and a fourth chip stack layer which are sequentially arranged on the first substrate, a second copper column located on the second substrate, and a second rewiring layer located on the back face of the second stack layer. And the second stacking layer is bonded with the first pair of stacking layers through the second rewiring layer, so that the second copper columns are bonded with the first copper columns, and the chip stacking structure is obtained. According to the chip stacking structure provided by the invention, the rewiring layer or the large bonding pad is introduced into the specific layer, and the chip stacking is carried out in a reasonable splitting and recombining manner, so that the processing difficulty is reduced, and the product yield is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a chip stacking structure and a packaging method thereof. Background Art

[0002] Chip stacking has been widely used in the field of advanced packaging, but there are still many technical difficulties and bottlenecks. There are two traditional stacking structures. One is the stacking of chips of the same or similar size. In this stacking structure, the upper chip will be offset by a certain distance when stacked, so that the I / O of the lower chip is exposed, and then the interconnection / function is achieved by wire bonding; the other is that a slightly smaller chip is stacked on a large chip, and the I / O of the lower chip is also exposed. The relatively advanced stacking in related technologies is chip stacking, and the I / O interconnection between chips is achieved by micro-through vias (TSV).

[0003] However, the stacking of multiple layers of chips pushes the chips to become thinner (the thinner the chip, the shallower the depth of the micro-via and the lower the difficulty of drilling; the thinner the chip, the more layers stacked at the same thickness; at the same time, the thinner the chip, the closer the conduction distance between the layers and the faster the response time). However, thinner chips mean that the wafer or chip has greater warping, and the difficulty of mounting and subsequent processing will increase, thus affecting the packaging yield. Summary of the invention

[0004] To this end, the present invention provides a chip stacking structure and a packaging method thereof. When multiple layers are stacked, larger pads or redistribution layers will appear in some intermediate layers. These specific layers are utilized and stacked in a modular form to weaken the adverse effects of layer-by-layer stacking, reduce process difficulty, and improve yield rate.

[0005] In a first aspect, the present application provides a chip stacking structure, which includes a first stacking layer and a second stacking layer bonded to the first stacking layer through the back side, wherein the first stacking layer includes, in its longitudinal section: a first substrate located on the front side of the first stacking layer, and a first redistribution layer located on the back side of the first stacking layer; a first surface of the first substrate is provided with a plurality of first solder pads, on which a first chip and a second chip stack are sequentially arranged, and a first filling layer around the first chip and the second chip stack; the second stacking layer includes, in its longitudinal section: a second substrate located on the front side of the second stacking layer, and a second redistribution layer located on the back side of the second stacking layer; a third surface of the second substrate is provided with a plurality of third solder pads, on which a third chip and a fourth chip stack are sequentially arranged, and a second filling layer around the third chip and the fourth chip stack; the second stacking layer is bonded to the first redistribution layer on the back side of the first stacking layer through the second redistribution layer on its back side.

[0006] Preferably, the second chip stack includes: a plurality of second chips stacked in sequence along the longitudinal direction, and the first stacking layer also includes: a plurality of first chip pads and first chip solder balls arranged on the front side of the first chip; a plurality of second through holes penetrating the second chip are arranged on each second chip; the first chip and the second chip stack are respectively connected to the first solder pads through the first chip solder balls and the second through holes on the front side of the second chip stack.

[0007] Preferably, the fourth chip stack includes: a plurality of fourth chips stacked in sequence along the longitudinal direction, and the second stacking layer also includes: a plurality of third chip pads and third chip solder balls arranged on the front side of the third chip; a plurality of fourth through holes penetrating the fourth chip are arranged on each fourth chip; the third chip and the fourth chip stack are respectively connected to the first pad through the third chip solder balls and the second through holes on the front side of the fourth chip stack.

[0008] Preferably, the chip stacking structure also includes: a first copper pillar extending longitudinally on the first surface of the first substrate; and a second copper pillar extending longitudinally on the third surface of the second substrate; the second stacking layer is bonded to the first redistribution layer on the back side of the first stacking layer through the second redistribution layer on the back side of the second stacking layer, so that the first copper pillar is bonded to the second copper pillar.

[0009] Preferably, the chip stacking structure further includes: in the first stacking layer, a third redistribution layer is arranged inside the first substrate; correspondingly, in the second stacking layer, a fourth redistribution layer is arranged inside the second substrate.

[0010] Preferably, the chip stacking structure also includes: a plurality of second solder pads located in the second surface of the first substrate, each of which is provided with a solder ball; and / or a plurality of fourth solder pads located in the fourth surface of the second substrate, each of which is provided with a solder ball.

[0011] Preferably, the first stacking layer also includes: a first through hole passing through the first chip, the first through hole being used to connect the first redistribution layer and the first chip pad on the front side of the first chip; a first substrate through hole passing through the first substrate, the two ends of the first substrate through hole being respectively connected to the first pad and the second pad, for forming an electrical connection between the first surface and the second surface of the first substrate; and a first pad through hole in the first substrate, the two ends of the first pad through hole being respectively connected to any first pad.

[0012] In a second aspect, the present application provides a packaging method for a chip stacking structure, the method comprising: completing the production of a first stacking layer and a second stacking layer respectively, wherein the first stacking layer comprises: a first substrate located on the front side of the first stacking layer, a first chip and a second chip stack sequentially arranged on the first substrate, a first copper pillar located on the first substrate, and a first redistribution layer located on the back side of the first stacking layer; the second stacking layer comprises: a second substrate located on the front side of the second stacking layer, a third chip and a fourth chip stack sequentially arranged on the second substrate, a second copper pillar located on the second substrate, and a second redistribution layer located on the back side of the second stacking layer; the second redistribution layer on the back side of the second stacking layer is bonded to the first redistribution layer on the back side of the first stacking layer, so that the first copper pillar is aligned with the second copper pillar, thereby obtaining the chip stacking structure.

[0013] Preferably, the completion of the production of the first stacking layer includes: providing a wafer, forming a plurality of first initial chips on the surface of the wafer; etching the first initial chip, forming a first through hole penetrating the first initial chip after filling, forming a first chip pad on the front side of the first initial chip and making a first chip solder ball on each first chip pad to obtain a first chip; providing a substrate, forming a third redistribution layer on a surface of the substrate, continuing to deposit substrate material on the third redistribution layer to form an initial substrate, forming a first pad on the first surface of the initial substrate to obtain a first substrate; forming a longitudinally extending first copper column on the first pad of the first substrate, connecting the first chip and the second chip stack in sequence on the first pad, wherein the first chip is connected to a portion of the first pad through the first chip solder ball, and the second chip stack is connected to a portion of the first pad through the second through hole therein; forming a first redistribution layer on the back side of the first chip and the back side of the second chip stack, respectively, and depositing an insulating material on the first redistribution layer to form a first filling layer; grinding and polishing the first filling layer to expose the first redistribution layer and the first copper column.

[0014] Preferably, completing the production of the second stacking layer includes: providing a wafer, forming a plurality of third initial chips on the surface of the wafer, forming a third chip pad on the front side of the third initial chip and making a third chip solder ball on each third chip pad to obtain a third chip; providing a substrate, forming a fourth redistribution layer on one surface of the substrate, continuing to deposit substrate material on the fourth redistribution layer to form an initial substrate, forming a third pad on one surface of the initial substrate to obtain a second substrate; forming a longitudinally extending second copper column on the third pad of the second substrate, connecting the third chip and the fourth chip stack in sequence on the third pad, wherein the third chip is connected to a portion of the third pad through the third chip solder ball, and the fourth chip stack is connected to a portion of the third pad through the fourth through hole therein; forming a second redistribution layer on the back side of the fourth chip stack, and depositing insulating material on the second redistribution layer to form a second filling layer; grinding and polishing the second filling layer to expose the second redistribution layer and the second copper column.

[0015] The chip stacking structure provided by the present invention introduces a redistribution layer or a large pad between specific layers of the chip, and uses a method of reasonably splitting and recombining the chips to stack the chips, thereby avoiding problems caused by chip warping, reducing processing difficulty, and improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a chip stacking structure provided in Example 1 of the present application;

[0017] Figure 2 A schematic diagram of a chip stacking structure provided in Example 2 of the present application;

[0018] Figures 3 to 14 A structural schematic diagram of the chip stacking structure packaging method provided in Example 3 of the present application.

[0019] Description of Reference Numerals

[0020] 10-chip stacking structure, 100-first stacking layer, 110-first substrate, 111-first pad 112-second pad, 113-solder ball, 115-first substrate through hole, 116-first pad through hole, 120-first copper pillar, 130-first chip, 131-first chip pad, 132 first chip solder ball, 133-first through hole, 140-first filling layer, 150-second chip stacking layer, 151-second through hole, 152-second through hole bump, 153 -Second chip, 160-first redistribution layer, 200-second stacked layer, 210-second substrate, 211-third solder pad, 212-fourth redistribution layer, 213-third solder pad through hole, 220-second copper pillar, 230-third chip, 231-third chip solder pad, 232-third chip solder ball, 240-fourth chip stack, 241-fourth through hole, 242-fourth through hole bump, 243-fourth chip, 250-second redistribution layer, 260-second filling layer. DETAILED DESCRIPTION

[0021] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] Example 1

[0023] Embodiment 1 of the present application provides a chip stacking structure, Figure 1 See the schematic diagram of the chip stacking structure provided in the application embodiment. Figure 1 The chip stacking structure 10 includes a first stacking layer 100 and a second stacking layer 200 bonded to the first stacking layer 100 by back bonding. The first stacking layer 100 includes:

[0024] A first substrate 110 is located on the front side of the first stacked layer 100, and a first redistribution layer 160 is located on the back side of the first stacked layer 100. A plurality of first pads 111 are arranged in the first surface S1 of the first substrate 110. A first chip 130 and a second chip stack 150 are arranged in sequence on the first pads 111, and a first filling layer 140 around the first chip 130 and the second chip stack 150; here, the first filling layer 140 is an insulating material for protecting the chip.

[0025] The front of the first chip 130 is provided with a plurality of first chip pads 131 and first chip solder balls 132, and the first chip 130 is connected to the first pad 111 through the first chip solder balls 132. The second chip stack 150 includes: a plurality of second chips 153 stacked in sequence in the longitudinal direction, and each second chip 153 is provided with a plurality of second through holes 151 penetrating the second chip 153, and the second chip stack 150 is connected to the first pad 111 through the second through holes 151 on the front of the second chip stack 150. In some embodiments, second through hole bumps (not shown in the figure) are provided at both ends of the second through hole 151, and the second chips 153 above and below are connected through the second through hole bumps on the second chip 153, and the second chip stack 150 is connected to the first pad 111 through the second through hole bumps at the bottom layer. Each second chip is aligned through the second through hole and is connected to other second chips through the second through hole bumps.

[0026] In the embodiment of the present application, the structure of the second stacked layer 200 is the same as that of the first stacked layer 100, wherein the second stacked layer 200 includes: a second substrate 210 located on the front side of the second stacked layer 200, and a second redistribution layer 250 located on the back side of the second stacked layer 200. Here, a plurality of third pads 211 are provided in the third surface S3 of the second substrate 210, and a third chip 230 and a fourth chip stack 240 are sequentially provided on the third pads 211, as well as a second filling layer 260 around the third chip 230 and the fourth chip stack 240.

[0027] Among them, the third chip 230 is provided with a plurality of third chip pads 231 and third chip solder balls 232 on the front side, and the third chip 230 is connected to the third pad 211 through the third chip solder balls 232. The fourth chip stack 240 includes: a plurality of fourth chips 243 stacked in sequence in the longitudinal direction, each of the fourth chips 243 is provided with a plurality of fourth through holes 241 penetrating the fourth chip 243, and the fourth chip stack 240 is connected to the third pad 211 through the fourth through holes 241 on the front side thereof. In some embodiments, fourth through hole bumps (not shown in the figure) may also be provided at both ends of the fourth through hole 241, and the fourth chips 243 above and below are connected through the fourth through hole bumps on the fourth chip 243, and the fourth chip stack 240 is connected to the third pad 211 through the fourth through hole bumps at the bottom layer. Each fourth chip is aligned through the fourth through hole, and is connected to other fourth chips through the fourth through hole bumps.

[0028] In the embodiment of the present application, the chip stacking structure 10 further includes: a first copper pillar 120 extending longitudinally on the first surface S1 of the first substrate 110, and a second copper pillar 220 extending longitudinally on the third surface S3 of the second substrate 210; Here, the first copper pillar 120 is disposed on the first pad 111, which can be Figure 1The first pad 111 shown in FIG. 1 may also be located on any one of the first pads, and the number of the first copper pillars 120 may be one or more. The second copper pillar 220 is disposed on the third pad 211 and may be Figure 1 The third pad shown in the figure may also be located on any one of the third pads. The number of the second copper pillars 220 may be one or more. It should be noted that in the embodiment of the present application, the number and position of the first copper pillars 120 and the second copper pillars 220 correspond to each other.

[0029] In the embodiment of the present application, the structures of the first stacking layer 100 and the second stacking layer 200 are completely the same, and the second stacking layer 200 is bonded to the first redistribution layer 160 on the back of the first stacking layer 100 through the second redistribution layer 250 on the back thereof, so that the first copper pillar 120 is bonded to the second copper pillar 220, thereby obtaining the chip stacking structure 10 provided in the embodiment of the present application. In some embodiments, the number of bondings between the first stacking layer 100 and the second stacking layer 200 can be multiple, forming a one-to-many or many-to-many bonding.

[0030] In some embodiments, the chip stacking structure may further include: a plurality of second pads located on the second surface of the first substrate, each of which is provided with a solder ball; and / or a plurality of fourth pads located on the fourth surface of the second substrate, each of which is provided with a solder ball. That is, pads and solder balls may be provided on the front of the first stacking layer and / or the second stacking layer according to actual scene requirements to complete I / O interconnection.

[0031] The embodiments of the present application use the application of introducing a redistribution layer or a large pad between specific layers to reasonably split and recombine the chips to stack them, thereby reducing the problems caused by chip warping, reducing processing difficulty, and improving product yield.

[0032] Example 2

[0033] Embodiment 2 of the present application provides a chip stacking structure, Figure 2 This is a schematic diagram of the chip stacking structure provided in Example 2 of the present application, see Figure 2 The chip stacking structure 10 includes a first stacking layer 100 and a second stacking layer 200 bonded to the first stacking layer 100 by back bonding. The first stacking layer 100 includes:

[0034] The first substrate 110 is located on the front side of the first stacked layer 100, and a plurality of first pads 111 are arranged in the first surface S1 of the first substrate 110. The first stacked layer further includes a metal copper column 120 located on the first surface S1 of the first substrate 110, one end of the metal copper column 120 is located on the first pad 111 of the first surface S1, and the other end extends longitudinally to the back side of the first stacked layer 100.

[0035] The first chip 130 and the second chip stack 150 are sequentially arranged on the first pad 111, as well as the first filling layer 140 around the first chip 130 and the second chip stack 150. Here, the substrate of the first chip 130 is not limited to silicon-based (Si, SiO, SiN, etc.), carbon-based, GaN, GaAs, etc. A plurality of first chip pads 131 and first chip solder balls 132 are arranged on the front of the first chip 130, and the first chip 130 is connected to the first pad 111 through the first chip solder balls 132. The second chip stack 150 includes: a plurality of second chips 153 stacked in sequence in the longitudinal direction, each second chip 153 includes a plurality of second through holes 151 penetrating the second chip 153, and second through hole bumps 152 are arranged at both ends of the second through hole 151, and the second chip stack 150 is connected to the first pad 111 through the bottom through hole bumps 152. Here, each second chip 153 is aligned through the second through-hole 151 and is connected to other second chips through the second through-hole bump 152 .

[0036] The first stack 100 further includes a first redistribution layer 160 on the back of the first stack 100 and on the back of the first chip 130 and the back of the second chip stack 150. Here, one end of the second through hole 151 in the second chip stack 150 is connected to the first pad, and the other end is connected to the first redistribution layer.

[0037] In the embodiment of the present application, the chip stacking structure 10 further includes: a plurality of second pads 112 located on the second surface S2 of the first substrate 110, each of which is provided with a solder ball 113; and / or a plurality of fourth pads located on the fourth surface of the second substrate, each of which is provided with a solder ball. Here, the second pads, the fourth pads and the solder balls can be provided as required, and the second pads and the solder balls can be provided only in the first stacking layer 100, or the fourth pads and the solder balls can be provided only in the second stacking layer 200, or the second pads, the fourth pads and the solder balls can be provided simultaneously in the first stacking layer 100 and the second stacking layer 200.

[0038] In the embodiment of the present application, the first stacked layer 100 also includes: a third redistribution layer 114 disposed inside the first substrate 110, where the third redistribution layer may be a multi-layer redistribution layer, which is not limited here. A first substrate through hole 115 is disposed in the first substrate 110 and passes through the first substrate 110, where the two ends of the first substrate through hole 115 are respectively connected to the first pad 111 and the second pad 112, for forming electrical connection between the first surface S1 and the second surface S2 of the first substrate 110. And a first pad through hole 116 in the first substrate 110, where the two ends of the first pad through hole 116 are respectively connected to any first pad 111, where the first pad through hole 116 is a semi-through hole structure in the first substrate. It can be understood that in the embodiment of the present application, in the first substrate, there is also a metal interconnection structure at the second pad 112. The first chip 130 further includes a first through hole 133 penetrating the first chip 130 . The first through hole 133 is used to connect the first redistribution wiring 160 layer on the back side of the first chip 130 and the first chip pad 131 on the front side of the first chip 130 .

[0039] In the embodiment of the present application, the second stacking layer includes: a second substrate 210 located on the front side of the second stacking layer 200, a plurality of third pads 211 are arranged in the third surface S3 of the second substrate 210, and a second copper pillar 220 extending longitudinally on the third surface S3 of the second substrate 210. In the embodiment of the present application, the second copper pillar 220 is arranged on the third pad 211, which can be the third pad shown in the figure, or it can be located on any one of the third pads. The number of the second copper pillars 220 can be one or more. It should be noted that in the embodiment of the present application, the number and position of the first copper pillars 120 and the second copper pillars 220 correspond to each other.

[0040] A third chip 230 and a fourth chip stack 240 are arranged on the third surface S3, and a second filling layer 260 around the third chip 230 and the fourth chip stack 240. The fourth chip stack 260 includes: a plurality of fourth chips 243 stacked in sequence in the longitudinal direction, each fourth chip 243 is provided with a plurality of fourth through holes 241 penetrating the fourth chip 243, fourth through hole bumps 242 are provided at both ends of the fourth through holes 241, and the fourth chips 243 above and below are connected through the fourth through hole bumps 242 on the fourth chip 243, and the fourth chip stack 240 is connected to the third pad 211 through the fourth through hole bumps 242 at the bottom layer. Each fourth chip is aligned through the fourth through hole and is connected to other fourth chips through the fourth through hole bumps.

[0041] The second stacking layer 200 also includes a second redistribution layer 250 on the back side of the second stacking layer 200. Here, the second redistribution layer 250 is located on the back side of the fourth chip stacking layer 240. One end of the fourth through hole in the fourth chip stacking layer is connected to the third pad, and the other end is connected to the second redistribution layer.

[0042] In the embodiment of the present application, the second filling layer 260 covers the back of the third chip 230, and a third pad through hole 213 is provided in the second substrate 210, and both ends of the third pad through hole 213 are respectively connected to any third pad 211, and here, the third pad through hole 213 is a semi-through hole structure in the second substrate. A fourth redistribution layer 212 is provided inside the second substrate 210. Here, the fourth redistribution layer can be a multi-layer redistribution layer, and it can be understood that a metal interconnection structure can also be included under the third pad 211.

[0043] Here, the material of the first through hole, the second through hole, the fourth through hole, the first substrate through hole, the first pad through hole and the third pad through hole is Al, W, Cu or a multi-layer metal or a multi-layer alloy or any combination thereof. The material of the first pad, the second pad, the third pad, the first chip pad and the third chip pad is not limited to a single metal such as Al, Sn, Pb, Ag, Cu, Au, Ni or a plurality of metal alloys or any combination thereof.

[0044] In the embodiment of the present application, the second stacking layer 200 is bonded to the first redistribution layer 160 on the back side of the first stacking layer 100 through the second redistribution layer 250 on the back side thereof to obtain the chip stacking structure 10. In some embodiments, the number of bonds between the first stacking layer and the second stacking layer can be multiple, forming a one-to-many or many-to-many bond.

[0045] Example 3

[0046] Embodiment 3 of the present application provides a packaging method for a chip stacking structure. Figures 3 to 14 For a schematic diagram of the packaging method provided in the embodiment of the present application, see Figures 3 to 14 , the method comprising:

[0047] Step 1: Complete the production of the first stacking layer and the second stacking layer respectively, wherein the first stacking layer includes:

[0048] A first substrate located on the front side of the first stacked layer, a first chip and a second chip stack sequentially arranged on the first substrate, a first copper pillar located on the first substrate, and a first redistribution layer located on the back side of the first stacked layer; the second stacked layer includes: a second substrate located on the front side of the second stacked layer, a third chip and a fourth chip stack sequentially arranged on the first substrate, a second copper pillar located on the second substrate, and a second redistribution layer located on the back side of the second stacked layer.

[0049] In the embodiment of the present application, the step 1 of completing the production of the first stacking layer includes the following steps:

[0050] Step S101: Provide a wafer, form a plurality of first initial chips on the surface of the wafer, thin the first initial chips, etch the first initial chips, form first through holes 133 penetrating the first initial chips after filling, form first chip pads 131 on the front of the first initial chips, and make first chip solder balls 132 on each first chip pad 131 to obtain first chips 130. Here, the first through holes 133 are formed with first chip pads 131.

[0051] Step S102: Provide a substrate, form a third redistribution layer 114 on a surface of the substrate, continue to deposit substrate material on the third redistribution layer 114 to form an initial substrate, and form a first pad 111 on the first surface S1 of the initial substrate to obtain a first substrate. Here, the third redistribution layer can be composed of multiple layers of redistribution layers, and the multiple layers of redistribution layers are formed in sequence according to design requirements. Before forming the first pad, it also includes etching the initial substrate and filling it to obtain a first substrate through hole 115 that penetrates the first substrate. In some embodiments, step S102 also includes completing the production of a metal interconnect structure and the production of a first pad through hole 116.

[0052] Step S103: A first copper pillar 120 extending longitudinally is formed on the first pad 111 of the first substrate 110, and a first chip 130 and a second chip stack 150 are sequentially connected on the first pad 111, wherein the first chip 130 is connected to a portion of the first pad 111 through a first chip solder ball 132, and the second chip stack 150 is connected to a portion of the first pad 111 through a second through hole 151 therein.

[0053] Here, the first copper pillar 120 can be formed by direct implantation or wire bonding, the first copper pillar 120 can be located on any first pad, and the number of the first copper pillars can be multiple. In the embodiment of the present application, the second chip stack 150 includes: a plurality of second chips 153 stacked in sequence along the longitudinal direction. The method for making the second chip 153 includes: method A: providing a second initial chip, thinning the second initial chip, etching the second initial chip according to a predetermined position, and forming a plurality of second through holes that penetrate the second initial chip in the second initial chip after filling, to obtain a second chip.

[0054] The method of connecting the second chip stack on the first pad includes: aligning the second through holes of the plurality of second chips obtained by method A, stacking them longitudinally in sequence by hybrid bonding to obtain the second chip stack, and mounting the second chip stack as a whole on the first pad. Alternatively, aligning the second through hole of a second chip obtained by method A with part of the first pad, then aligning the second through hole of the next second chip with the second through hole of the previous second chip and mounting, repeating the above process several times, and completing the connection between the second chip stack and the first pad.

[0055] Method B: Provide a second initial chip, thin the second initial chip, and then etch the second initial chip according to a predetermined position, form a plurality of second through holes that penetrate the second initial chip in the second initial chip after filling, and make second through hole bumps at both ends of each second through hole to obtain a second chip.

[0056] The method of connecting the second chip stack on the first pad includes: aligning the second through hole of a second chip obtained by method B with the second through hole bump of another second chip, stacking them longitudinally in sequence, obtaining the second chip stack, and mounting them on the first pad as a whole. Alternatively, aligning the second through hole bump of a second chip obtained by method B with part of the first pad, then aligning the second through hole of the next second chip with the second through hole bump of the previous second chip and mounting them, repeating the above process several times, and completing the connection between the second chip stack and the first pad.

[0057] Step S104: forming a first redistribution layer 160 on the back side of the first chip 130 and the back side of the second chip stack 150 respectively, and depositing an insulating material on the first redistribution layer 160 and forming a filling layer 140 after curing; grinding and polishing the filling layer 140 to expose the first redistribution layer 160 and the first copper pillar 120.

[0058] The process of completing the production of the second stacking layer 200 in step 1 includes the following steps:

[0059] Step S201: Provide a wafer, form a plurality of third initial chips on the surface of the wafer, form third chip pads 231 on the front of the third initial chip and make third chip solder balls 232 on each third chip pad 231 to obtain a third chip 230. Here, the pads are made after the third initial chip is thinned.

[0060] Step S202: providing a substrate, forming a fourth redistribution layer 260 on a surface of the substrate, continuing to deposit substrate material on the fourth redistribution layer 260 to form an initial substrate, and forming a third pad 211 on a surface of the initial substrate to obtain a second substrate 210. Here, the fourth redistribution layer is composed of multiple redistribution layers, and the multiple redistribution layers are formed in sequence according to design requirements. It can be understood that step S202 also includes forming metal interconnections in the initial substrate.

[0061] Step S203: A second copper pillar 220 extending longitudinally is formed on the third pad 211 of the second substrate 210, and a third chip 230 and a fourth chip stack 240 are sequentially connected on the third pad 211, wherein the third chip 230 is connected to a portion of the third pad 211 through a third chip solder ball 232, and the fourth chip stack 240 is connected to a portion of the third pad 211 through a fourth through hole 241 therein.

[0062] Here, the second copper pillar 220 can be formed by direct implantation or wire bonding, and the number and distribution of the second copper pillars are the same as those of the first copper pillars. The fourth chip stack 240 includes: a plurality of fourth chips 243 stacked in sequence along the longitudinal direction. The method for making the fourth chip includes: method C: providing a fourth initial chip, thinning the fourth initial chip, etching the fourth initial chip according to a predetermined position, and forming a plurality of fourth through holes that penetrate the fourth initial chip in the fourth initial chip after filling, to obtain a fourth chip.

[0063] The method of connecting the fourth chip stack on the third pad includes: aligning the fourth through holes of multiple fourth chips obtained by method C, stacking them longitudinally in sequence by hybrid bonding, obtaining the fourth chip stack, and mounting the fourth chip stack on the third pad as a whole. Alternatively, aligning the fourth through hole of a fourth chip obtained by method C with part of the third pad, then aligning the fourth through hole of the next fourth chip with the fourth through hole of the previous fourth chip and mounting, repeating the above process several times, and completing the connection between the fourth chip stack and the third pad.

[0064] Method D: Provide a fourth initial chip, thin the fourth initial chip and then etch the fourth initial chip according to a predetermined position, form a plurality of fourth through holes that penetrate the fourth initial chip in the fourth initial chip after filling, make fourth through hole bumps at both ends of each fourth through hole, and obtain a fourth chip.

[0065] The method of connecting the fourth chip stack on the third pad includes: aligning the fourth through hole of a fourth chip obtained by method D with the fourth through hole bump of another fourth chip, stacking them longitudinally in sequence, obtaining the fourth chip stack, and mounting the fourth chip stack on the third pad as a whole. Alternatively, aligning the fourth through hole bump of a fourth chip obtained by method D with part of the third pad, then aligning the fourth through hole of the next fourth chip with the fourth through hole bump of the previous fourth chip and mounting, repeating the above process several times, and completing the connection of the fourth chip stack on the third pad.

[0066] Step S204: forming a second redistribution layer 250 on the back side of the fourth chip stack 240, and depositing an insulating material on the second redistribution layer 250 to form a second filling layer 260 after curing; grinding and polishing the second filling layer 260 to expose the second redistribution layer 250 and the second copper pillar 220.

[0067] After completing the production of the first stacking layer 100 and the second stacking layer 200, step two is performed to bond the second redistribution layer 250 on the back side of the second stacking layer 200 to the first redistribution layer 160 on the back side of the first stacking layer 100. Here, the completed second stacking layer 200 is flipped and rotated, and then bonded to the back side of the first stacking layer 100 through the back side. During bonding, the first copper column and the second copper column need to be completely aligned to bond them. In some embodiments, the number of bonds between the first stacking layer and the second stacking layer can be multiple, forming a one-to-many or many-to-many bond.

[0068] In the embodiment of the present application, the bonding method of the first stacking layer 100 and the second stacking layer 200 is a conventional bonding method, such as conductive adhesive bonding, or a new bonding method such as hybrid bonding.

[0069] In some embodiments, the method may further include: Step 3: forming a plurality of second pads on the second surface of the first substrate, and forming solder balls on the second pads, and / or forming fourth solder balls on the fourth surface of the second substrate, and forming solder balls on the fourth pads. Here, solder balls are manufactured according to actual application scenarios to complete the manufacture of the chip stacking structure.

[0070] The above description is only the preferred embodiment of the present invention and is not intended to limit the present invention. Any technician familiar with the profession may make various changes, modifications, substitutions and variations to these embodiments without departing from the principle and purpose of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A chip stacking structure, characterized in that: The chip stacking structure comprises a first stacking layer and a second stacking layer bonded to the first stacking layer by backside bonding, wherein the first stacking layer comprises, in a longitudinal section thereof: A first substrate located on the front side of the first stacked layer, and a first redistribution layer located on the back side of the first stacked layer; a plurality of first pads are arranged in the first surface of the first substrate, a first chip and a second chip stack are arranged in sequence on the first pads, and a first filling layer around the first chip and the second chip stack is arranged; The second stacked layer comprises, in its longitudinal section: A second substrate is located on the front side of the second stacked layer, and a second redistribution layer is located on the back side of the second stacked layer; a plurality of third pads are arranged in the third surface of the second substrate, a third chip and a fourth chip stack are arranged in sequence on the third pads, and a second filling layer is arranged around the third chip and the fourth chip stack; The second stacking layer is bonded to the first redistribution layer on the back side of the first stacking layer through the second redistribution layer on the back side of the second stacking layer.

2. The chip stacking structure according to claim 1, characterized in that: The second chip stack comprises: a plurality of second chips stacked in sequence in a longitudinal direction, The first stacking layer further includes: a plurality of first chip pads and first chip solder balls disposed on the front side of the first chip; and a plurality of second through holes penetrating the second chip are disposed on each second chip; The first chip and the second chip stack are connected to the first pad through the first chip solder ball and the second through hole on the front side of the second chip stack respectively.

3. The chip stacking structure according to claim 2, characterized in that: The fourth chip stack comprises: a plurality of fourth chips stacked in sequence along the longitudinal direction, The second stacking layer further includes: a plurality of third chip pads and third chip solder balls disposed on the front side of the third chip; and a plurality of fourth through holes penetrating the fourth chip are disposed on each fourth chip; The third chip and the fourth chip stack are respectively connected to the first pad through the third chip solder balls and the second through holes on the front sides of the fourth chip stack.

4. The chip stacking structure according to claim 3, characterized in that: The chip stacking structure also includes: A first copper column extending longitudinally on the first surface of the first substrate; and a second copper column extending longitudinally on the third surface of the second substrate; The second stacking layer is bonded to the first redistribution layer on the back side of the first stacking layer through the second redistribution layer on the back side thereof, so that the first copper pillar is bonded to the second copper pillar.

5. The chip stacking structure according to claim 4, characterized in that: The chip stacking structure also includes: In the first stacked layer, a third redistribution layer is disposed inside the first substrate; Correspondingly, in the second stacking layer, a fourth redistribution layer is arranged inside the second substrate.

6. The chip stacking structure according to claim 5, characterized in that: The chip stacking structure also includes: A plurality of second pads located on the second surface of the first substrate, each of the second pads being provided with a solder ball; And / or, a plurality of fourth pads are located on the fourth surface of the second substrate, each of the fourth pads being provided with a solder ball.

7. The chip stacking structure according to claim 6, characterized in that: The first stacking layer also includes: A first through hole penetrating the first chip, the first through hole being used to connect the first redistribution layer and the first chip pad on the front side of the first chip; A first substrate through hole penetrating the first substrate, wherein two ends of the first substrate through hole are respectively connected to a first pad and a second pad, for forming an electrical connection between the first surface and the second surface of the first substrate; And a first pad through hole in the first substrate, wherein two ends of the first pad through hole are respectively connected to any first pad.

8. A packaging method for a chip stacking structure, characterized in that: The method comprises: The first stacking layer and the second stacking layer are respectively manufactured, wherein the first stacking layer comprises: A first substrate located on the front side of the first stacked layer, a first chip and a second chip stacked layer sequentially arranged on the first substrate, a first copper pillar located on the first substrate, and a first redistribution layer located on the back side of the first stacked layer; The second stacking layer comprises: a second substrate located on the front side of the second stacking layer, a third chip and a fourth chip stacked layer sequentially arranged on the second substrate, a second copper pillar located on the second substrate, and a second redistribution layer located on the back side of the second stacking layer; The second redistribution layer on the back side of the second stacking layer is bonded to the first redistribution layer on the back side of the first stacking layer, so that the first copper pillar is aligned with the second copper pillar to obtain the chip stacking structure.

9. The method according to claim 8, characterized in that The process of completing the production of the first stacking layer comprises: A wafer is provided, and a plurality of first initial chips are formed on the surface of the wafer; the first initial chips are etched, and a first through hole penetrating the first initial chips is formed after filling, a first chip pad is formed on the front side of the first initial chips, and a first chip solder ball is formed on each first chip pad to obtain a first chip; Providing a substrate, forming a third redistribution layer on a surface of the substrate, continuously depositing a substrate material on the third redistribution layer to form an initial substrate, and forming a first pad on a first surface of the initial substrate to obtain a first substrate; Forming a first copper column extending longitudinally on a first pad of the first substrate, and sequentially connecting the first chip and the second chip stack on the first pad, wherein the first chip is connected to a portion of the first pad through a first chip solder ball, and the second chip stack is connected to a portion of the first pad through a second through hole therein; A first redistribution layer is formed on the back side of the first chip and the back side of the second chip stack respectively, and an insulating material is deposited on the first redistribution layer to form a first filling layer; the first filling layer is ground and polished to expose the first redistribution layer and the first copper column.

10. The method according to claim 9, characterized in that Completing the second stacking layer includes: Providing a wafer, forming a plurality of third initial chips on the surface of the wafer, forming a third chip bonding pad on the front side of the third initial chip and making a third chip bonding ball on each third chip bonding pad to obtain a third chip; Providing a substrate, forming a fourth redistribution layer on one surface of the substrate, continuously depositing substrate material on the fourth redistribution layer to form an initial substrate, and forming a third pad on one surface of the initial substrate to obtain a second substrate; A second copper pillar extending longitudinally is formed on the third pad of the second substrate, and the third chip and the fourth chip stack are sequentially connected on the third pad, wherein the third chip is connected to a part of the third pad through a third chip solder ball, and the fourth chip stack is connected to a part of the third pad through a fourth through hole therein; A second redistribution layer is formed on the back side of the fourth chip stack, and an insulating material is deposited on the second redistribution layer to form a second filling layer; the second filling layer is ground and polished to expose the second redistribution layer and the second copper column.

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