Electronic device and manufacturing method thereof

Abstract

An electronic device and a manufacturing method thereof are provided. An electronic device includes a signal distribution structure having a top side and a bottom side; a first electronic component coupled to the top side of the signal distribution structure; a second electronic component coupled to the top side of the signal distribution structure; a conductive shielding member coupled to a top side of the signal distribution structure and positioned directly between the first electronic component and the second electronic component; an encapsulation material covering at least a portion of a top side of the signal distribution structure, at least a portion of lateral sides of the first and second electronic components, and at least a portion of a lateral side of the conductive shielding member; and an electromagnetic interference (EMI) shielding layer on the top side of the encapsulation material and the top side of the conductive shielding member, where the electromagnetic interference shielding layer is electrically coupled to the top side of the conductive shielding member. Various aspects of the present disclosure provide a semiconductor device including one or more conductive shielding members and an EMI shielding layer, and methods of making the same.

Description

[0001] This application is a divisional application of the invention application with an application date of May 15, 2017, a priority date of March 24, 2017, an application number of 201710337523.9, and an invention name of “Electronic device and manufacturing method thereof”. Technical Field

[0002] The invention relates to an electronic device and a manufacturing method thereof. Background Art

[0003] Current semiconductor devices and methods of manufacturing semiconductor devices are inadequate, for example resulting in a manufacturing process that is too time consuming and / or too expensive, resulting in semiconductor packages having unreliable connections and / or interconnect structures having suboptimal dimensions, etc. Further limitations and disadvantages of the conventional and traditional methods will become apparent to those skilled in the art by comparing the conventional and traditional methods with some aspects of the present invention as described with reference to the drawings in the remainder of this application. Summary of the invention

[0004] Various aspects of the present disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. As a non-limiting example, various aspects of the present disclosure provide a semiconductor device including one or more conductive shielding members and an EMI shielding layer and a method for manufacturing the same.

[0005] One aspect of the present invention is a method of manufacturing an electronic device, the method comprising: forming a conductive shielding member on a top side of a carrier; attaching a first electronic component to the top side of the carrier; attaching a second electronic component to the top side of the carrier, wherein the conductive shielding member is positioned directly laterally between the first electronic component and the second electronic component; forming an encapsulation material covering at least a portion of the top side of the carrier, at least a portion of a lateral side of the first electronic component, at least a portion of a lateral side of the second electronic component, and at least a portion of a lateral side of the conductive shielding member; forming a signal distribution structure on a respective bottom side of each of the encapsulation material, the first electronic component, the second electronic component, and the conductive shielding member; and forming an electromagnetic interference (EMI) shielding layer on the top side of the encapsulation material and on the top side of the conductive shielding member, wherein the EMI shielding layer is electrically coupled to the top side of the conductive shielding member. The method comprises removing at least a portion of the carrier before forming the signal distribution structure. In the method, the conductive shielding member is wall-shaped. The method includes forming at least a plurality of additional conductive shielding members on the top side of the carrier, wherein the conductive shielding member and the additional conductive shielding members are positioned in a row, and wherein the aforementioned forming of the electromagnetic interference shielding layer includes directly forming the electromagnetic interference shielding layer on the respective top sides of the conductive shielding member and each of the plurality of additional conductive shielding members. In the method, the conductive shielding member is solderless. In the method, the conductive shielding member is connected to the signal distribution structure without using solder, and the conductive shielding member is connected to the electromagnetic interference shielding layer without using solder. In the method, the aforementioned forming of the encapsulation material includes forming the encapsulation material to cover the top side of the first electronic component, the top side of the second electronic component, and the top side of the conductive shielding member. The method includes thinning the encapsulation material to expose at least the top side of the conductive shielding member before the aforementioned forming of the electromagnetic interference shielding layer. In the method, attaching the first electronic component includes attaching a first component terminal of the first electronic component to the top side of the carrier; attaching the second electronic component includes attaching a second component terminal of the second electronic component to the top side of the carrier; and the method includes removing the carrier, wherein after removing the carrier, respective bottom surfaces of each of the first component terminal, the second component terminal, the first conductive shielding member, and the encapsulation material are coplanar. In the method, the encapsulation material includes a plurality of lateral sides, each of the lateral sides being coplanar with respective lateral sides of the signal distribution structure; and forming the electromagnetic interference shielding layer includes forming the electromagnetic interference shielding layer on the lateral sides of the encapsulation material and on the lateral sides of the signal distribution structure.

[0006] Another aspect of the present invention is a method for manufacturing an electronic device, the method comprising: forming a conductive shielding member, the conductive shielding member comprising a bottom side seed layer and at least one conductive layer formed on the seed layer; installing a first component, which comprises a first bottom side component terminal; installing a second component, which comprises a second bottom side component terminal, wherein the conductive shielding member is directly positioned laterally between the first electronic component and the second electronic component; forming an encapsulation material, which covers at least a portion of a lateral side of the first electronic component, at least a portion of a lateral side of the second electronic component, and at least a portion of a lateral side of the conductive shielding member; forming a signal distribution structure on the respective bottom sides of each of the encapsulation material, the first electronic component, the second electronic component, and the conductive shielding member; and forming an electromagnetic interference (EMI) shielding layer on the top side of the encapsulation material and on the top side of the conductive shielding member, wherein the electromagnetic interference shielding layer is electrically coupled to the top side of the conductive shielding member. In the method, the aforementioned forming of the conductive shielding member includes forming the conductive shielding member on the top side of the carrier; the aforementioned installing the first component includes attaching the first bottom side component terminal to the carrier; the aforementioned installing the second component includes attaching the second bottom side component terminal to the carrier; and the aforementioned forming of the encapsulation material includes forming the encapsulation material, which covers at least a portion of the top side of the carrier. The method includes removing at least a portion of the carrier before the aforementioned forming of the signal distribution structure. In the method, the respective surfaces of each of the first component terminal, the second component terminal, the conductive shielding member, and the encapsulation material are coplanar. In the method, the seed layer is laterally surrounded by the encapsulation material. In the method, the conductive shielding member is solderless; the conductive shielding member is connected to the signal distribution structure without using solder; and the first conductive shielding member is connected to the electromagnetic interference shielding layer without using solder. In the method, the aforementioned forming of the encapsulation material includes forming the encapsulation material to cover the top side of the first electronic component, the top side of the second electronic component, and the top side of the conductive shielding member; and the method includes thinning the encapsulation material to expose at least the top side of the conductive shielding member before the aforementioned forming of the electromagnetic interference shielding layer. In the method, the encapsulation material includes a plurality of lateral sides, each of the lateral sides is coplanar with a respective lateral side of the signal distribution structure; and the aforementioned forming of the electromagnetic interference shielding layer includes surrounding all lateral sides of the encapsulation material and all lateral sides of the signal distribution structure with the electromagnetic interference shielding layer.

[0007] Another aspect of the present invention is an electronic device comprising a signal distribution structure having a top side and a bottom side; a first electronic component coupled to the top side of the signal distribution structure; a second electronic component coupled to the top side of the signal distribution structure; a conductive shielding member coupled to the top side of the signal distribution structure and positioned directly between the first electronic component and the second electronic component; an encapsulation material covering at least a portion of the top side of the signal distribution structure, at least a portion of the lateral sides of the first electronic component and the second electronic component, and at least a portion of the lateral sides of the conductive shielding member; and an electromagnetic interference (EMI) shielding layer on the top side of the encapsulation material and the top side of the conductive shielding member, wherein the EMI shielding layer is electrically coupled to the top side of the conductive shielding member. In the electronic device, there is no intermediate layer between the first electronic component and the signal distribution structure, and there is no intermediate layer between the second electronic component and the signal distribution structure. In the electronic device, the conductive shielding member includes a seed layer and a conductive layer formed on the seed layer; and the respective surfaces of each of the first electronic component, the second electronic component, the seed layer, and the encapsulation material are coplanar. In the electronic device, the conductive shielding member is solderless; the conductive shielding member is directly connected to the signal distribution structure without using solder; and the conductive shielding member is directly connected to the electromagnetic interference shielding layer without using solder. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A flow chart showing an exemplary method of fabricating a semiconductor device according to various aspects of the present invention.

[0009] Figure 2A-2I Cross-sectional views are shown illustrating various steps of an exemplary method of fabricating a semiconductor device and a semiconductor device fabricated thereby according to various aspects of the present invention.

[0010] Figure 3A Plan views of exemplary semiconductor devices according to various aspects of the present invention are shown.

[0011] Figure 3B Plan views of exemplary semiconductor devices according to various aspects of the present invention are shown. DETAILED DESCRIPTION

[0012] The following discussion presents these features by providing examples of various aspects of the present disclosure. Such examples are not limiting, and thus the scope of the various aspects of the present disclosure should not be limited to any particular features of the examples provided. In the following discussion, the words "for example," "for example," and "exemplary" are not limiting and are generally synonymous with "by way of example and not limitation," "for example and not limitation," and the like.

[0013] As used herein, "and / or" means any one or more of the items joined by "and / or" in a list. For example, "x and / or y" means any element in the set of three elements {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y." As another example, "x, y and / or z" means any element in the set of seven elements {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and / or z" means "one or more of x, y and z."

[0014] The terms used in this document are intended only for the purpose of describing specific examples and are not intended to limit the present disclosure. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. It will be further understood that when the terms "include", "comprise", "have", and the like are used in this specification, they specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0015] It will be appreciated that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited to these terms. These terms are merely used to distinguish one element from another. Thus, for example, a first element, a first member, or a first section discussed below may be referred to as a second element, a second member, or a second section without departing from the teachings of the present disclosure. Similarly, various spatial terms such as "above," "below," "side," and the like may be used in a relative manner to distinguish one element from another. However, it should be appreciated that members may be oriented in different ways, such as a semiconductor device may be turned sideways so that its "top" surface is horizontally oriented and its "side" surface is vertically oriented without departing from the teachings of the present disclosure.

[0016] It will be understood that the terms coupled, connected, attached and similar terms include both direct and indirect (i.e., with intermediate elements) couplings, connections, attachments unless expressly stated otherwise. For example, if element A is coupled to element B, element A may be indirectly coupled to element B through an intermediate signal distribution structure, or element A may be directly coupled to element B (e.g., directly bonded, directly welded, or attached by direct metal-to-metal bonding, etc.)...etc.

[0017] In the drawings of the present invention, the sizes (e.g., absolute and / or relative sizes) of structures, layers, regions, etc. may be exaggerated for clarity. However, such sizes are generally representative of exemplary embodiments and are not limiting. For example, if structure A is illustrated as being larger than region B, this is only to represent an exemplary embodiment, but structure A is generally not necessarily larger than structure B unless otherwise specified. In addition, in the drawings, similar element symbols represent similar elements throughout the discussion.

[0018] Various electronic devices transmit and / or receive electromagnetic waves. Unwanted electromagnetic waves may interfere with the operation of the electronic devices. Therefore, electronic device packages may be formed with electromagnetic interference (EMI) shielding. This EMI shielding may be formed to protect electronic devices outside the electronic device package from electromagnetic interference caused by electronic devices inside the package and / or to protect electronic devices inside the electronic device package from electromagnetic interference caused by electronic devices outside the package. In addition, the electronic device package may include one or more EMI shields to protect multiple electronic devices in the package from affecting each other, such as forming one or more EMI shielding compartments in the electronic device package.

[0019] Various aspects of the present invention provide a method for manufacturing an electronic device and an electronic device manufactured by the method, the method comprising: forming a conductive shielding member on the top side of a carrier; attaching a first electronic component to the top side of the carrier; attaching a second electronic component to the top side of the carrier, wherein the conductive shielding member is directly placed laterally between the first electronic component and the second electronic component; forming an encapsulation material that covers at least a portion of the top side of the carrier, at least a portion of the lateral side of the first electronic component, at least a portion of the lateral side of the second electronic component, and at least a portion of the lateral side of the conductive shielding member; forming a signal distribution structure on the respective bottom sides of each of the encapsulation material, the first electronic component, the second electronic component, and the conductive shielding member; and forming an electromagnetic interference (EMI) shielding layer on the top side of the encapsulation material and on the top side of the conductive shielding member, wherein the EMI shielding layer is electrically coupled to the top side of the conductive shielding member.

[0020] In various exemplary embodiments, the method may include removing at least a portion of the carrier prior to the aforementioned formation of the signal distribution structure. Also by way of example, the conductive shielding member is wall-shaped. For example, the method may include forming at least a plurality of additional conductive shielding members on the top side of the carrier, wherein the conductive shielding member and the additional conductive shielding members are placed in a row, and wherein the aforementioned formation of the EMI shielding layer includes forming the EMI shielding layer directly on the respective top sides of each of the conductive shielding member and the plurality of additional conductive shielding members. In an exemplary embodiment, the conductive shielding member may be solder-free. For example, the conductive shielding member may be connected to the signal distribution structure without using solder, and the conductive shielding member is connected to the EMI shielding layer without using solder. In addition, by way of example, forming an encapsulation material may include forming the encapsulation material to cover the top side of the first electronic component, the top side of the second electronic component, and the top side of the conductive shielding member. For example, before the aforementioned formation of the EMI shielding layer, the encapsulation material is thinned to expose at least the top side of the conductive shielding member. In an exemplary embodiment, the aforementioned attachment of the first electronic component includes attaching a first component terminal of the first electronic component to the top side of the carrier; the aforementioned attachment of the second electronic component includes attaching a second component terminal of the second electronic component to the top side of the carrier; the method may include removing the carrier, wherein after the aforementioned removal of the carrier, the respective bottom surfaces of each of the first component terminal, the second component terminal, the first conductive shielding member, and the encapsulation material are coplanar. In an exemplary embodiment, the encapsulation material may include a plurality of lateral sides, each lateral side being coplanar with a respective lateral side of the signal distribution structure; and the aforementioned formation of the EMI shielding layer may include forming the EMI shielding layer on the lateral sides of the encapsulation material and on the lateral sides of the signal distribution structure.

[0021] Various aspects of the present invention provide a method for manufacturing an electronic device and an electronic device made by the method, the method comprising: forming a conductive shielding member on the top side of a carrier, the conductive shielding member comprising a seed layer and at least one conductive layer formed on the seed layer; attaching a first component terminal of a first electronic component to the top side of the carrier; attaching a second component terminal of a second electronic component to the top side of the carrier, wherein the conductive shielding member is directly placed laterally between the first electronic component and the second electronic component; forming an encapsulation material that covers at least a portion of the top side of the carrier, at least a portion of the lateral side of the first electronic component, at least a portion of the lateral side of the second electronic component, and at least a portion of the lateral side of the conductive shielding member; removing at least a portion of the carrier from the bottom side of the encapsulation material; forming a signal distribution structure on the respective bottom sides of each of the encapsulation material, the first electronic component, the second electronic component, and the conductive shielding member; and forming an electromagnetic interference (EMI) shielding layer on the top side of the encapsulation material and on the top side of the conductive shielding member, wherein the EMI shielding layer is electrically coupled to the top side of the conductive shielding member.

[0022] In various exemplary embodiments, the respective surfaces of each of the first component terminal, the second component terminal, the conductive shielding member, and the encapsulation material are coplanar. Similarly, for example, the seed layer may be laterally surrounded by the encapsulation material. In an exemplary embodiment, the conductive shielding member may be solderless; the conductive shielding member may be connected to the signal distribution structure without using solder; and the first conductive shielding member is connected to the EMI shielding layer without using solder. In an exemplary embodiment, the aforementioned forming of the encapsulation material may include forming the encapsulation material to cover the top side of the first electronic component, the top side of the second electronic component, and the top side of the conductive shielding member; and the method may include thinning the encapsulation material to expose at least the top side of the conductive shielding member before the aforementioned forming of the EMI shielding layer. In an exemplary embodiment, the encapsulation material may include a plurality of lateral sides, each of the plurality of lateral sides being coplanar with a respective lateral side of the signal distribution structure; and the aforementioned forming of the EMI shielding layer may include surrounding all lateral sides of the encapsulation material and the signal distribution structure by the EMI shielding layer.

[0023] Various aspects of the present invention provide an electronic device and a method for manufacturing such an electronic device, the electronic device comprising: a first electronic component coupled to the top side of the signal distribution structure; a second electronic component coupled to the top side of the signal distribution structure; a conductive shielding member coupled to the top side of the signal distribution structure and placed directly between the first and second electronic components; an encapsulation material covering at least a portion of the top side of the signal distribution structure, at least a portion of the lateral sides of the first and second electronic components, and at least a portion of the lateral sides of the conductive shielding member; and an electromagnetic interference (EMI) shielding layer on the top side of the encapsulation material and on the top side of the conductive shielding member, wherein the EMI shielding layer is electrically coupled to the top side of the conductive shielding member.

[0024] In various exemplary embodiments, there may be no intermediate layer between the first electronic component and the signal distribution structure, and there may be no intermediate layer between the second electronic component and the signal distribution structure. In addition, for example, the conductive shielding member may include a seed layer and a conductive layer formed on the seed layer; and the respective surfaces of each of the first electronic component, the second electronic component, the seed layer, and the encapsulation material are coplanar. In exemplary embodiments, the conductive shielding member may be solderless; the conductive shielding member may be directly connected to the signal distribution structure without the use of solder; and the conductive shielding member may be directly connected to the EMI shielding layer without the use of solder.

[0025] Various aspects of the present invention provide methods for manufacturing semiconductor devices (or packages) and semiconductor devices (or packages) manufactured by the methods, the methods comprising: forming a seed layer on a carrier and forming one or more conductive shielding components (such as pillars, walls, fences, etc.) on the seed layer, attaching a semiconductor grain having a plurality of conductive pads to the carrier at opposite sides of the conductive shielding components, encapsulating the conductive shielding components and the semiconductor grains in an encapsulation material, forming a signal distribution structure electrically connected to the plurality of conductive pads, forming a conductive interconnect structure on the signal distribution structure and forming an electromagnetic interference (EMI) shielding layer on a surface of the encapsulation body.

[0026] Various aspects of the invention also provide a semiconductor device (or package) and a method for manufacturing the same, which includes one or more conductive shielding components (such as pillars, walls, fences, etc.); a semiconductor grain formed on the opposite side of the conductive shielding component and having a plurality of conductive pads; an encapsulation material that encapsulates the conductive shielding component and the semiconductor grain; a signal distribution structure that is electrically connected to the plurality of conductive pads; a conductive interconnect structure that is attached to the signal distribution structure; and an electromagnetic interference (EMI) shielding layer on the surface of the encapsulation material.

[0027] According to various aspects of the invention, a conductive shielding structure (such as a column, a wall, a fence, etc.) is formed between a plurality of semiconductor grains; and an EMI shielding layer is formed on the surface of the encapsulation material and is electrically connected to the conductive shielding structure, thereby shielding electromagnetic waves generated by electronic components (such as semiconductor grains, etc.) of the electronic device package to prevent such electromagnetic waves from being emitted to the outside of the electronic device package, shielding electromagnetic waves transmitted from devices outside the electronic device package to prevent such electromagnetic waves from penetrating into the electronic device package, and shielding electromagnetic waves generated by electronic components of the electronic device package to prevent such electromagnetic waves from reaching other electronic components of the electronic device package.

[0028] Figure 1 A flow chart showing an exemplary method of fabricating a semiconductor device according to various aspects of the present invention. Figure 2A-2I A plurality of cross-sectional views are shown illustrating various steps of an exemplary method of manufacturing a semiconductor device according to various aspects of the present invention. For example, Figure 2A-2I Display according to Figure 1 The following discussion will also refer to the cross-sectional view of an exemplary semiconductor device during or after the manufacturing process of the exemplary method 1000. Figure 1 and Figure 2A-2I It should be noted that the following discussion sometimes refers to Figure 3A and 3B ,and Figure 3A and 3B Plan views of exemplary semiconductor devices (eg, various aspects of exemplary conductive shielding members, etc.) are shown.

[0029] refer to Figure 1 , an exemplary method 100 for manufacturing a semiconductor device may include: (S1) forming one or more conductive shielding members on a carrier; (S2) attaching electronic components to the carrier; (S3) encapsulating; (S4) removing the carrier; (S5) forming a signal distribution structure; (S6) performing back grinding; (S7) forming an interconnect structure; (S8) singulation; and (S9) forming an electromagnetic interference (EMI) shielding layer.

[0030] refer to Figure 1 and Figure 2A , 2B 2C, at block (or step, stage, process, etc.) S1, the method 1000 may include forming one or more conductive shielding members on a carrier. For example, block S1 may include receiving a carrier 10. For example, block S1 may include receiving the carrier 10 from an upstream manufacturing process, receiving the carrier 10 from a supplier at a different regional location, etc.

[0031] The carrier 10 may include any of a variety of features, and the examples provided herein are non-limiting. For example, the carrier 10 may include a carrier for a single semiconductor device (or package) (which may also be referred to herein as a substrate), or, for example, the carrier 10 may include a wafer or panel on which any number of semiconductor devices (or packages) may be formed. For example, the carrier 10 may include a semiconductor (such as silicon...etc.) wafer or panel. For example, the carrier 10 may also include a glass wafer or panel, a metal wafer or panel, a ceramic wafer or panel, a plastic wafer or panel...etc. It should be noted that although the discussion of block diagram S1 includes forming the conductive shielding member on the carrier 10, the carrier 10 may also be a carrier on which the conductive shielding member has been formed when it is received.

[0032] For example, block S1 may include forming one or more conductive shielding members 110 on the carrier 10. The conductive shielding members 110 may include any of a variety of shapes or features. Figure 3A As shown in , the exemplary conductive shielding member 110' may include a wall shape (or form). Although the exemplary wall-shaped conductive shielding member 110' is shown as extending entirely across the carrier 10 from a first side to an opposite side (or, for example, a portion of the carrier is dedicated to a specific semiconductor device package), the conductive shielding member 110' may extend between two adjacent sides (e.g., in a straight line, in a semicircular manner, in a triangular manner... etc.), the conductive shielding member 110' may extend only to one side of the carrier 10, the conductive shielding member 110' may not extend to the side of the carrier (e.g., be entirely placed within the periphery of the carrier 10, be placed to surround one or more electronic components... etc.)... etc. Although only one exemplary wall-shaped conductive shielding member 110' is shown in Figure 3A In an embodiment, multiple conductive shield members may be formed, for example, all of the conductive shield members may have the same general shape or any combination of shapes discussed herein.

[0033] Further examples of conductive shielding members (or multiple conductive shielding members) are shown in Figure 3B Example 300b includes a plurality of cylindrical (or rod-shaped) conductive shield members 110" arranged in a row (eg, spaced closely enough to block EMI in a frequency range (or wavelength range) of interest). Figure 3A Like the wall-shaped conductive shielding member 100' of the example 300a, the conductive shielding member 110" may be configured in a row (or pattern) that directly (or indirectly) extends between two opposite sides of the carrier 10 (or, for example, a portion of the carrier is dedicated to a specific semiconductor device package), configured in a row (or pattern) that extends between two adjacent sides (for example, in a straight line, in a semicircular manner, in a triangular manner... etc.), configured in a row (or pattern) that does not extend to the side of the carrier (for example, is entirely placed within the periphery of the carrier 10, is placed to surround one or more electronic components... etc.)... etc. Although not shown, in the exemplary configuration there are lateral gaps between the conductive shielding members 110", for example, conductive traces may be directly formed between adjacent conductive shielding members 110" to interconnect electronic components on opposite sides of the conductive shielding members 110".

[0034] In various exemplary embodiments, the one or more conductive shielding members 110 may have a cylindrical, truncated cone, elliptical, square, rectangular, upright or vertically curved shape, etc. (e.g., in a horizontal plane or radial cross section, in a vertical plane or longitudinal cross section, etc.). For example, the conductive shielding member 110 may also include a flat top, a concave top, or a convex top. Therefore, the scope of the present invention should not be limited to any particular shape or pattern of conductive shielding members.

[0035] The one or more conductive shielding members 110 may include any one or more of various conductive materials (e.g., copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, or equivalents thereof, etc.), but the scope of the present invention should not be limited thereto. In an exemplary embodiment, the one or more conductive shielding members 110 may include copper (e.g., pure copper, copper with some impurities, etc.), copper alloys, etc. In an exemplary embodiment, the conductive shielding member 110 may also include one or more capping layers on the top. In an exemplary embodiment, the conductive shielding member 110 may be solderless. In addition, the conductive shielding member 110 may ultimately be connected to the signal distribution structure 155 (discussed herein) and to the EMI shielding layer 170 without using solder, wire bonding, etc.

[0036] Block diagram S1 may include forming the conductive shielding member 110 in various ways (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present invention is not limited thereto.

[0037] exist Figure 2A In the example 200a shown, block diagram S1 includes forming a seed layer 111 (or multiple seed layers) on the carrier 10. For example, the seed layer 111 may cover the entire top surface of the carrier 10. It should be noted that the seed layer 111 may also be referred to as an underbump metallization (UBM) seed layer herein (for example, in one case, a UBM structure is formed thereon). For example, the seed layer 111 may include any of a variety of conductive materials. For example, the seed layer 111 may include copper. For example, the seed layer 111 may also include one or more layers of any of a variety of metals (such as silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, etc.). Block diagram S1 may include forming the seed layer 111 using any of a variety of techniques (for example, sputtering or other physical vapor deposition (PVD) techniques, chemical vapor deposition (CVD), electroless plating, electroplating, etc.).

[0038] like Figure 2B In the example 200b shown, block S1 includes forming a mask 20 (or template) on the seed layer 111 to define one or more regions (or volumes) in which the one or more conductive shielding members 110 are formed. For example, the mask 20 may include a photoresist (PR) material or other material (e.g., an organic dielectric material, an inorganic dielectric material, etc.), which may be patterned to cover other regions except for the region on which the one or more conductive shielding members 110 are formed. For example, block S1 may include forming the conductive shielding member 110 on the seed layer 111 exposed by the mask 20 (e.g., by electroplating, etc.).

[0039] Although not shown, before forming the conductive shielding member 110, an under bump metallization (UBM) structure including one or more UBM layers may be formed, for example, the under bump metallization (UBM) structure may be formed on the region of the seed layer 111 exposed through the mask 20. In this example, the one or more UBM layers may include any of various materials (e.g., titanium, chromium, aluminum, titanium / tungsten, titanium / nickel, copper, alloys of the aforementioned materials, equivalents of the aforementioned materials, etc.). The one or more UBM layers may be formed on the seed layer 111 in any of various ways (e.g., electroplating, electroless plating, sputtering, CVD, PVD, ALD, etc.).

[0040] like Figure 2C In the example 200c shown, after forming the conductive shielding member 110, block diagram S1 may include stripping or removing the mask 20 (e.g., chemical stripping, ashing, etc.). In addition, block diagram S1 may include removing at least a portion of the seed layer 111 (e.g., at least the portion not covered by the conductive shielding member 110 (e.g., by chemical etching, etc.)). It should be noted that during the aforementioned removal (or etching) of the seed layer 111, the side edge portion of the seed layer 111 under the conductive shielding member 110 may also be removed (or etched). For example, the aforementioned removal (or under-etching) may cause an undercut under the conductive shielding member 110 (and / or if there is a UBM structure). For example, in an exemplary embodiment, in which both the UBM structure and the respective conductive shield member 110 are formed on the same seed layer, the etching of the aforementioned seed layer may cause undercuts under the UBM structure and / or under the conductive shield member 110 formed thereon. For example, in an exemplary embodiment, in which the conductive shield member 110 is formed on the seed layer, the etching of the aforementioned seed layer may cause undercuts under the conductive shield member 110.

[0041] refer to Figure 1 and Figure 2D In the example 200d, at block S2, the example method includes attaching the electronic component to the carrier. Block S2 may include performing the aforementioned attachment in any of a variety of methods, and the present invention provides non-limiting examples.

[0042] The electronic components 121 and 122 (or any electronic components discussed in the present invention) may include features of any of various types of electronic components. For example, all or any of the electronic components 121 and 122 (or any electronic components discussed in the present invention) may include passive electronic components (e.g., resistors, capacitors, inductors, antenna elements, etc.), integrated passive devices (IPDs), etc. For another example, all or any of the electronic components 121 and 122 may include active electronic components (e.g., semiconductor dies, transistors, etc.). For example, all or any of the electronic components 121 and 122 may include processing dies, microprocessing dies, microcontroller dies, co-processor dies, general-purpose processor dies, application-specific integrated circuit dies, programmable and / or discrete logic dies, memory dies, wired and / or wireless transceiver dies, RF circuits, wireless baseband system-on-chip (SoC) processor dies, sensing circuits, combinations of the foregoing, equivalents, etc.

[0043] The example first electronic component 121 may include a first component terminal 121a, and the second electronic component 122 may include a second component terminal 122a. Because the example electronic components 121 and 122 are shown and discussed as semiconductor dies, the component terminals 121a and 122a may also be referred to herein as die pads 121a and 122a.

[0044] For example, block S2 may include attaching (or coupling) the electronic components 121 and 122 to the carrier 10 in any of a variety of ways, and the present invention provides non-limiting examples. For example, block S2 may include using adhesives, vacuum pressure, etc. to perform the aforementioned attachment.

[0045] In an exemplary embodiment, block diagram S2 may include forming an adhesive layer or adhesive (not shown) on the carrier 10 and / or on the electronic components 121 and 122. For example, the adhesive layer may include an adhesive paste layer, a liquid adhesive layer, a pre-made double-sided tape or film (e.g., a die attach tape), a printed adhesive, etc. For example, the adhesive layer may partially or completely cover the top side of the carrier 10. For example, the adhesive layer may also or alternatively partially or completely cover the bottom side of the electronic components 121 and 122 (e.g., covering the component terminals 121a and 122a, the dielectric material between the component terminals 121a and 122a, etc.).

[0046] Block diagram S2 may include forming the aforementioned adhesive layer in any of a variety of ways. For example, block diagram S2 may include forming the adhesive layer by applying a pre-made film or a thin film of the adhesive layer to the carrier 10 and / or to the electronic components 121 and 122, printing the adhesive layer on the carrier 10 and / or on the electronic components 121 and 122, spin coating the adhesive layer on the carrier 10 and / or on the electronic components 121 and 122, immersing the carrier 10 and / or the electronic components 121 and 122 in an adhesive, spraying the adhesive layer on the carrier 10 and / or on the electronic components 121 and 122, etc.

[0047] In an exemplary embodiment, at least the component terminals 121a and 122a of the electronic components 121 and 122 may be placed in contact with an adhesive layer (or adhesive member) and thereby coupled to the carrier 10. In various exemplary cases, the component terminals 121a and 122a (e.g., all or part of the lateral sides thereof) may be embedded in the adhesive layer, may be placed only on the top surface of the adhesive layer, etc. For example, in an exemplary case, wherein the adhesive layer (or adhesive member) or a portion of the adhesive layer (or adhesive member) is vertically between the carrier 10 and the component terminals 121a and 122a, there is a vertical displacement between the bottom end of the conductive shielding member 110 (or under the seed layer) and the bottom end of the component terminals 121a and 122a. As another example, in an exemplary case, in which the adhesive layer (or adhesive) is not vertically between the carrier 10 and the component terminals 121a and 122a, there is no vertical displacement between the bottom end of the conductive shielding member 110 (or under the seed layer) and the bottom end of the component terminals 121a and 122a and / or they may be coplanar.

[0048] Block diagram S2 may include placing the electronic components 121 and 122 on the carrier 10 in any of a variety of ways (eg, using an automated pick-and-place system, manual placement, performing any combination of automated and manual placement, etc.).

[0049] like Figure 3A and 3B As shown, the electronic components 121 and 122 may be positioned on the carrier 10 and on the conductive shielding structure 110 (eg Figure 3A 110' and Figure 3B 110 ”). Therefore, the conductive shielding structure 110 traverses the area between the electronic components 121 and 122 to provide lateral EMI shielding between the electronic components 121 and 122.

[0050] Although only two electronic components 121 and 122 are shown, any number of electronic components is possible. Also, although only two sides of the conductive shielding structure 110 are provided, for example, to form two shielding regions, any number of the aforementioned shielding regions is possible. For example, as discussed herein, the conductive shielding structure 110 can be formed by any of a variety of patterns to form any or a variety of shapes, sizes, and numbers of shielding regions.

[0051] It should be noted that although the figures show the component terminals 121a and 122a (e.g., die pads, etc.) recessed into the first and second electronic components 121 and 122 (e.g., semiconductor dies, etc.), such recessing is not required. For example, the component terminals 121a and 122a can be formed to protrude from the bottom surfaces (e.g., active surfaces, etc.) of the first and second electronic components 121 and 122. More generally, the component terminals 121a and 122a can be formed to protrude from the bottom surfaces of the electronic components 121 and 122. In addition, although not shown, a dielectric layer (or passivation layer) can be formed to cover the surrounding lateral sides and / or surrounding areas of the bottom sides of the component terminals 121a and 122a.

[0052] Next reference Figure 1 and Figure 2E In the example structure 200e of FIG. 1 , the example method 1000 in block S3 may include forming an encapsulation material. For example, block S3 may include covering the top side 10 of the carrier (and / or an adhesive layer thereon, if an adhesive layer is present), the sides (e.g., top side, lateral side, etc.) of the electronic components 121 and 122, and the sides (e.g., top side, lateral side, etc.) of the conductive shield member 110 in an encapsulation material 130. In addition, the encapsulation material 130 may cover any portion of the bottom side of the electronic components 121 and 122 (e.g., component terminals 121a and 122a, dielectric layer, etc.), any portion of which is not covered by the carrier 10 (or adhesive layer, if present). It should be noted that any side (eg, top side, lateral side, bottom side, etc.) or any portion of the one or more electronic components 121 and 122 may be left uncovered by the encapsulation material 130 .

[0053] Block diagram S3 may include forming the encapsulation material 130 by any of a variety of methods, and the present invention provides non-limiting examples. For example, block diagram S3 may include using one or more of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, paste printing, film-assisted molding, glob top molding, flooding, etc. to form the encapsulation material 130. For another example, block diagram S3 may include using one or more of spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma assisted chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc. to form the encapsulation material 130.

[0054] The encapsulation material 130 may include one or more of various encapsulation materials, and the present invention provides non-limiting examples. For example, the encapsulation material 130 may include any of various encapsulation or molding materials (e.g., resin, polymer, polymer composite, polymer with filler, epoxy resin, epoxy resin with filler, epoxy acrylic with filler, silicone resin, combination of the foregoing materials, equivalents of the foregoing materials, etc.). For another example, the encapsulation material 130 may include any of a variety of dielectric materials, for example, inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations of the foregoing materials, equivalents of the foregoing materials, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide-triazine (BT), molding materials, heat-curable epoxy molding compounds, room temperature curable glob-top molding compounds, phenolic resins, epoxy resins, silicones, acrylic polymers, combinations of the foregoing materials, equivalents of the foregoing materials, etc.).

[0055] It should be noted that the encapsulation material 130 may be initially formed to a desired thickness, but may be thinned after formation (e.g., thinned while still covering the electronic components 121 and 122, thinned to expose the top surface of one or more of the electronic components 121 and 122, etc.). If the aforementioned thinning is performed, the aforementioned thinning may be performed in any block diagram of the example method 1000 (e.g., in block diagram S6, etc.).

[0056] Next reference Figure 1 and Figure 2FIn the example structure 200f, in block diagram S4, the example method may include flipping (or turning over) the encapsulated structure 200e and removing the carrier 10 (and the adhesive layer, if present). In the example embodiment, although there is no Figure 2F , a second carrier (or tool structure) can be coupled to the encapsulation material 130 (e.g., on a side opposite to the carrier 10, etc.), and then the carrier 10 (and adhesive layer, if present) can be removed. Although various examples presented herein show the entire carrier 10 being removed, in various other example embodiments, only a portion of the carrier 10 is removed (e.g., having holes formed therein to provide electrical connections to the conductive shielding member 110 and the component terminals 121a and 122a).

[0057] Block S4 may include removing the carrier 10 (and the adhesive layer, if present) or a portion of the carrier 10 by any of a variety of methods, non-limiting examples of which are provided herein. For example, block S4 may include applying energy (e.g., heat energy, laser energy, etc.) to the adhesive layer and / or the carrier 10 to release the adhesive layer. Furthermore, for example, block S4 may include peeling, sheering, pulling the carrier 10 from the encapsulation material 130, the conductive shielding member 110, and the electronic components 121 and 122. Furthermore, for example, block S4 may include grinding (or grinding) and / or chemically etching the carrier 10 and / or the adhesive layer.

[0058] It should be noted that in various exemplary cases, a portion of the component terminals 121a and 122a, a portion of the electronic components 121 and 122a, a portion of the conductive shielding member 110, and / or a portion of the encapsulation material 130 directly adjacent to the carrier 10 (or adhesive layer) may be removed (e.g., planarized, etc.). For example, after removing the carrier 10 (and adhesive, if present), all of the aforementioned component terminals 121a and 122a, electronic components 121 and 122, conductive shielding member 110, and encapsulation material 130 may be coplanar. In exemplary cases, block diagram S4 may also include removing some or all of the seed layer 111'. For example, although Figure 2F The example 200 f shows that after the removal of the carrier 10 , at least a portion of the seed layer 111 ′ remains, but in other exemplary embodiments, the entire seed layer 111 a may be removed.

[0059] It should be noted that the removal of the carrier 10 (and the adhesive layer, if present) may expose the side of the encapsulation material 130 previously covered by the carrier 10 (or adhesive layer), and may also expose the side of the component terminals 121a and 122a previously covered by the carrier 10 (and adhesive layer) (e.g., the side facing the carrier 10, the lateral side embedded in the adhesive layer, etc.). It should be noted that, depending on the geometry of the electronic components 121 and 122 and / or the component terminals 121a and 122a, the removal of the carrier 10 (and the adhesive layer, if present) may also expose portions of the electronic components 121 and 122 other than the component terminals 121a and 122a.

[0060] Next reference Figure 1 and Figure 2G In the exemplary structure 200g of FIG. 1 , the exemplary method 1000 in block diagram S5 includes forming a signal distribution structure 155 on the encapsulation material 130 and on the electronic components 121 and 122 (and / or component terminals 121a and 122a). Figure 2G-2I The exemplary signal distribution structure 155 in illustrative embodiment includes a plurality of dielectric layers 150 (eg, a first dielectric layer 151 including a first hole 153 and a second dielectric layer 152 including a second hole 154) and a conductive layer 140. However, the signal distribution structure 155 may include any number of dielectric layers and conductive layers.

[0061] Block diagram S5 may include forming the signal distribution structure 155 in any of a variety of ways, and the present invention provides non-limiting examples. For example, block diagram S5 may share any or all features of similar block diagrams (and / or formed structures) disclosed in US patent application No. 14 / 823,689, entitled “Semiconductor Package and Method of Manufacturing Thereof”, filed on August 11, 2016, all of which are hereby incorporated herein by reference in their entirety.

[0062] For example, block S5 may include forming and patterning one or more dielectric layers and one or more conductive layers to form the signal distribution structure 155. It should be noted that the signal distribution structure 155 may also be referred to as a redistribution layer, a redistribution layer stack, a redistribution structure, an interposer, etc.

[0063] For example, block S5 may include forming the signal distribution structure 155 having any number of dielectric layers and conductive layers (e.g., signal distribution layers, redistribution layers, liner layers, conductive vias, under bump metallization, land layers, etc.). In an exemplary embodiment, block S5 may include forming the signal distribution structure 155 including a first dielectric layer 151, a conductive layer 140 (e.g., conductive vias, liner or land layers, trace layers, etc.), and a second dielectric layer 152, wherein the first dielectric layer 151 includes one or more first holes 153 and the second dielectric layer 152 includes one or more second holes 154. Block S5 (or block S7, etc.) may also include forming an under bump metallization (UBM) structure 159 (or layer), for example, formed in the second hole 154 and / or on the second dielectric layer 152 and around the second hole 154.

[0064] For example, block diagram S5 may include using any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma assisted chemical vapor deposition (PECVD), plasma vapor deposition (PVD), thin film lamination, evaporation, etc.) to form the first dielectric layer 151. The examples provided in the present invention are not limiting.

[0065] The first dielectric layer 151 may include one or more layers of any variety of dielectric materials, for example, inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations of the foregoing materials, equivalents of the foregoing materials, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide-triazine (BT), molding materials, phenolic resins, epoxy resins, silicones, acrylic polymers, combinations of the foregoing materials, equivalents of the foregoing materials, etc.), but the examples provided by the present invention are not limiting.

[0066] For example, block diagram S5 may also include patterning the first dielectric layer 151, such as forming a first hole 153 in the first dielectric layer 151, which exposes the component terminals 121a and 122a of the electronic components 121 and 122. For example, block diagram S5 may include ablating the first hole 153 (for example, using laser ablation, using mechanical ablation, using chemical ablation (or etching)... etc.). For another example, block diagram S5 may include initially forming the first dielectric layer 151 (for example, deposition... etc.), which has the desired first hole 153 (for example, using a mask and / or printing process... etc.). Although shown from a vertical side, the first hole 153 may have an inclined side, for example, having a narrower end toward the component terminals 121a and 122a, and a wider end away from the component terminals 121a and 122a. For example, the sloped side can facilitate forming a conductive structure (eg, a conductive via, a conductive layer, an under bump metallization layer, a conductive interconnect structure . . . , etc.) therein.

[0067] Block diagram S5 may include forming the first conductive layer 140 (e.g., conductive via layer, pad or land layer, trace layer, etc.) by any of a variety of methods, and the present invention provides non-limiting examples. For example, block diagram S5 may include forming the first conductive layer 140 using any one or more of a variety of processes (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), molecular layer deposition (ALD), plasma vapor deposition (PVD), printing, screen printing, lithography, etc.), but the examples provided by the present invention are not limiting. For example, block diagram S5 may include forming the first conductive layer 140 (for example) containing conductive vias in the first holes 153 of the first dielectric layer 151 on the top sides of the component terminals 121a and 122a of the electronic components 121 and 122. As another example, block S5 may include forming traces on the first dielectric layer 151 (and / or in a via formed therein). For example, the traces may extend laterally from the conductive via.

[0068] As with any conductive layer discussed herein, block S5 may include forming one or more seed layers as part of the process of forming the first conductive layer 140 (e.g., before electroplating the first conductive layer 140, etc.). For example, although not shown in Figure 2G In the block diagram S5, one or more seed layers may be formed on the top surface of the component terminals 121a and 122a, on the sidewalls of the first hole 153 through the first dielectric layer 151, on the top surface of the first dielectric layer 151, and so on.

[0069] The first conductive layer 140 may also be referred to herein as a pad, a through hole, a trace, a connection pad, a wiring pad layer, a conductive layer, a trace layer, a redistribution layer, etc. The first conductive layer 140 may include any variety of materials (for example, copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, a combination of the foregoing materials, an alloy of the foregoing materials, an equivalent of the foregoing materials, etc.), but the examples provided by the present invention are not limiting.

[0070] For example, block diagram S5 may include forming a second dielectric layer 152 on the first dielectric layer 151 (or a portion thereof) and / or on the first conductive layer 140 (or a portion thereof). For example, block diagram S5 may include forming the second dielectric layer 152 by any of a variety of methods, such as the methods discussed herein in connection with the first dielectric layer 151. For example, block diagram S5 may include forming the second dielectric layer 152 by the same method as the method for forming the first dielectric layer 151, or by a different method. For example, the second dielectric layer 152 may include any of the features discussed herein in connection with the first dielectric layer 151. For example, the second dielectric layer 152 may be formed of the same dielectric material as the first dielectric layer 151, or may be formed of a different dielectric material.

[0071] Similar to the first dielectric layer 151, block S5 may include patterning the second dielectric layer 152 in any of a variety of ways. For example, block S5 may include forming a second hole 154 in the second dielectric layer 152 to expose pads, lands, traces of the first conductive layer 140, such as for establishing electrical contact with other conductive layers, with under bump metallization layers, with interconnect structures (e.g., formed in block S7, etc.). As discussed herein with respect to the first hole 153, the second hole 154 may have a slanted side, for example, with a narrower end toward the component terminals 121a and 122a, and a wider end away from the component terminals 121a and 122a. For example, the slanted side may facilitate the formation of various conductive structures (e.g., under bump metallization layers, conductive interconnect structures, conductive vias, conductive layers, etc.) in the second hole 154.

[0072] It should be noted that the block diagram S5 may include forming the signal distribution structure 155 to have any number of conductive layers and / or dielectric layers, such as one or more conductive layers, one or more dielectric layers, etc. It should also be noted that the configuration of the signal distribution structure 155 shown in the various figures of the present invention is only used as an example and is not limiting. For example, the signal distribution structure 155 (or its conductive layer) may directly vertically or indirectly (e.g., vertically and horizontally, etc.) pass through the signal distribution structure 155 to provide an electrical path, such as between the first electronic component 121, the second electronic component 122 and / or the conductive shielding member 110 (or other components) to other components on the opposite side of the signal distribution structure 155 or from other components on the opposite side of the signal distribution structure 155 to the first electronic component 121, the second electronic component 122 and / or the conductive shielding member 110 (or other components). For another example, the signal distribution structure 155 (or its conductive layer) may provide a lateral (or horizontal) electrical path through the signal distribution structure 155, such as between the first electronic component 121 and the second electronic component 122, between the first electronic component 121 and the conductive shielding member 110, between the second electronic component 122 and the conductive shielding member 110, between other components and the first electronic component 121, between the second electronic component 122 and any or all of the conductive shielding member 110... and so on.

[0073] In various exemplary embodiments, for example, block diagram S5 may also include forming one or more under-bump metallization (UBM) structures 159 (or layers) on the first conductive layer 140 and / or on the second dielectric layer 152 (e.g., on a portion of the second dielectric layer 152 and around the second hole 154 in the second dielectric layer 152, through which the conductive layer 140 is exposed...etc.). For example, block diagram S5 may include forming the UBM structure 159 to have one or more metal layers conductively connected to an attachment (or formation) of an interconnect structure (e.g., conductive balls, conductive pillars or rods...etc.), such as formed and / or attached in block diagram S7. For example, the UBM structure 159 may be exposed at the top surface of the signal distribution structure 155 (e.g., as in Figure 2G The UBM structures 159 may also be referred to herein as lands or pads.

[0074] Block diagram S5 may include forming the UBM structure 159 by any of a variety of methods, the present invention provides non-limiting examples. In an exemplary embodiment, block diagram S5 may include forming a UBM seed layer of the UBM structure 159 on the second dielectric layer 152 and / or on the portion of the conductive layer 140 exposed by the second hole 154 in the second dielectric layer 152 (e.g., a pad or connection pad, a trace, etc.). For example, the UBM seed layer may include any of a variety of conductive materials (e.g., copper, gold, silver, metal, etc.). The UBM seed layer can be formed by any of a variety of methods (e.g., sputtering, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular layer deposition (ALD), plasma vapor deposition, etc.).

[0075] For example, block diagram S5 may include forming a mask (or template) on the UBM seed layer to define an area (or volume) in which one or more additional UBM layers (or other interconnect structures) of the UBM structure 159 are formed. For example, the mask may include a photoresist (PR) material or other material that can be patterned to cover areas other than the area on which the UBM layer (and / or other interconnect structure) is formed. For example, block diagram S5 may include forming one or more UBM layers on the UBM seed layer exposed through the mask. The UBM layer may include any of a variety of materials (e.g., titanium, chromium, aluminum, titanium / tungsten, titanium / nickel, copper, alloys of the foregoing materials, etc.). Block diagram S5 may include forming the UBM layer on the UBM seed layer by any of a variety of methods, or without using a UBM seed layer (e.g., electroplating, sputtering, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular layer deposition (ALD), plasma vapor deposition, etc.).

[0076] It should be noted that in various exemplary embodiments, the UBM structure 159 may not be formed. For example, as discussed below, the conductive interconnect structure 160 may be directly attached to the conductive layer 140 without any intermediate layers.

[0077] Generally speaking, block diagram S5 may include forming a signal distribution structure 155 (or an interposer). Therefore, the scope of the disclosure herein should not be limited to the features of any particular signal distribution structure or to the features of any particular method of forming a signal distribution structure.

[0078] Next reference Figure 1 and Figure 2H In the example structure 200h, the example method 1000 in block diagram S6 may include thinning (or planarizing) the assembly (e.g. Figure 2GThe block diagram S6 may include performing the aforementioned thinning (or planarization) (e.g., backside thinning) in any of a variety of methods, and the present invention provides non-limiting examples. It should be noted that the aforementioned thinning may be performed in any of the various block diagrams of the exemplary method 1000.

[0079] For example, block S6 may include thinning (e.g., mechanical grinding, chemical etching, shaving or shearing, stripping, combinations thereof, etc.) the encapsulation material 130 to a desired thickness. For example, the side of the encapsulation material 130 opposite the side facing the signal distribution structure 155 may be the primary focus of such grinding. The aforementioned side is shown in Figure 2H At the bottom side of the assembly 200h.

[0080] For example, block S6 may also include thinning (e.g., mechanical grinding, chemical etching, stripping, any combination thereof, etc.) the conductive shielding member 110. Figure 2H In the exemplary embodiment 200h shown in FIG. 1 , block S6 includes performing thinning in a method that results in the coplanarity of the encapsulation material 130 and the conductive shielding member 110, for example, leaving the back sides of the electronic components 121 and 122 covered by the encapsulation material 130. Thus, at least the end surface (and / or at least the top of the lateral side surface) of the conductive shielding member 110 is exposed from (at) the surface of the encapsulation material 130. It should be noted that although Figure 2H The exemplary embodiment 200 h shows that the backsides of the electronic components 121 and 122 are covered by the encapsulation material 130 , however, one or both of the backsides may be exposed by (at) the surface of the encapsulation material 130 .

[0081] In various exemplary embodiments, block diagrams S1-S9 (and / or resulting structures) may share any or all features with substantially similar blocks (and / or resulting structures) shown in U.S. patent application Ser. No. 14 / 823,689, filed on August 11, 2016, entitled “Semiconductor Package and Method of Fabrication Thereof,” the entire contents of which are incorporated herein by reference in their entirety for all purposes.

[0082] Next reference Figure 1 and Figure 2H In the exemplary structure 200h, the exemplary method 1000 in block diagram S7 may include forming one or more conductive interconnect structures. Block diagram S7 may include forming the aforementioned interconnect structures in any of a variety of methods, and the present invention provides non-limiting examples.

[0083] As discussed herein, the second dielectric layer 152 may include second holes 154 through which electrical connections are made to the conductive layer 140. Also, as discussed above, the UBM structure 159 may be formed in and / or around the second holes 154. For example, block diagram S7 may include forming the conductive interconnect structure 160 on the conductive layer 140 (e.g., via individual holes 154 through the second dielectric layer 152) and / or on a portion of the second dielectric layer 152 (e.g., around individual holes 154 through the second dielectric layer 152). For example, block diagram S7 may include forming the conductive interconnect structure 160 directly on the first conductive layer 140 or directly on the UBM structure 159.

[0084] The conductive interconnect structure 160 (e.g., package interconnect structure, module interconnect structure, etc.) may include any of a variety of features. For example, the conductive interconnect structure 160 may include conductive balls or bumps (e.g., solder balls or bumps, wafer bumps, solid core or copper core solder balls, etc.). For example, in an exemplary embodiment, solder balls or bumps are included, and the aforementioned solder balls or bumps may include tin, silver, lead, Sn-Pb, Sn 37 -Pb, Sn 95 The conductive interconnect structure 160 may include conductive posts or rods, conductive wires, connection pads, etc., for example, any conductive material discussed herein (e.g., gold trees, conductive adhesives, etc.).

[0085] The conductive interconnect structure 160 may be constructed in any or various configurations. For example, the conductive interconnect structure 160 may be constructed as a ball grid array configuration, a land grid array configuration, etc. For example, the conductive interconnect structure 160 may be configured around a periphery of the semiconductor package (e.g., around the area (or outline) occupied by the first electronic component 121 and / or the second electronic component 122). For example, the conductive interconnect structure 160 may also be configured as a column / row matrix array (e.g., wherein at least a portion of the matrix / array is within the area (or outline) occupied by the first electronic component 121 and / or the second electronic component 122).

[0086] Block diagram S7 may include forming (or attaching) the aforementioned conductive interconnect structure 160 by any of a variety of methods, and the present invention provides non-limiting examples. For example, block diagram S7 may include forming (or attaching) the aforementioned conductive interconnect structure 160 by ball dropping, bumping, metal plating, pasting and reflow, etc. For example, block diagram S7 may include dropping a conductive ball on the conductive layer 140 (e.g., directly on the conductive layer, directly on the UBM structure 159 formed on the conductive layer 140, etc.). In an exemplary embodiment, block diagram S7 may include dotting volatile flux on the UBM structure 159, dropping a conductive ball (or bump) 160 on the flux, and then providing a reflow temperature ranging from 150 degrees C to 250 degrees C (e.g., volatilizing and removing the flux). For example, block S7 may share any or all features of block S1 (eg, the forming of the conductive shielding member 110 ).

[0087] Although not shown, for example, block diagram S7 may also include forming (or attaching) additional components (e.g., passive components, active components, etc.) laterally between the conductive interconnect structures 160. In an exemplary embodiment, the aforementioned components may have a height that is less than the height of the conductive interconnect structures 160. For example, the aforementioned components may have a smaller height than the solder ball conductive interconnect structure 160, a smaller height than the solid core (e.g., copper core, etc.) of the solder ball conductive interconnect structure 160, etc. In such an embodiment, when the conductive interconnect structure 160 is attached to another substrate or component, the conductive interconnect structure 160 may provide a spacing to maintain a gap for the aforementioned components.

[0088] Next reference Figure 1 and Fig.2I In the example structure 200i of FIG. 1 , in block diagram S8 , the example method 1000 may include singulating an electronic package from a wafer or panel or other connected electronic packages. Block diagram S8 may include performing the singulation in any of a variety of ways, and the present invention provides non-limiting examples.

[0089] For example, as discussed herein, any or all of the blocks of the exemplary method 1000 may be performed at a wafer or panel level, such as to form multiple electronic devices (or packages) simultaneously. For example, the wafer or panel may then be singulated into individual packages. For example, the singulation may be performed by any one or more of mechanical cutting (e.g., sawing, dicing, grinding, cutting, etc.), energy cutting (e.g., laser cutting, plasma cutting, etc.), chemical cutting (e.g., etching, dissolving, etc.), etc. In an exemplary embodiment, the singulation may form coplanar lateral side surfaces of the electronic device (or package). For example, one or more lateral side surfaces of the encapsulation material 130 and the signal distribution structure 155 (e.g., the first dielectric layer 151, the second dielectric layer 152, and / or the conductive layer 140) may be coplanar on one or more lateral sides of the singulated electronic device (or package) 200i.

[0090] In addition, in an exemplary configuration, one or more sides of the conductive shielding member 110 extend to lateral sides of the singulated electronic device, and block S8 may also include cutting through one or more portions of the conductive shielding member 110. For example, the aforementioned cutting may cause the lateral sides of the conductive shielding member 110 to have exposed sides, and the exposed sides are coplanar with the lateral sides of the encapsulation material 130 and / or with the lateral sides of the signal distribution structure 155.

[0091] It should be noted that the singulation may be optionally performed after block S9. In this case, the lateral side surfaces may be left uncovered by the EMI shielding layer 170 discussed below, or the EMI shielding layer 170 may be formed on the lateral side surfaces and / or on a portion of the bottom surface after singulation.

[0092] Next reference Figure 1 and Fig.2I In the example structure 200i, in block diagram S9, the example method 1000 may include singulating an electronic package from a wafer or panel or other connected electronic packages. Block diagram S8 may include performing the aforementioned singulation in any of a variety of methods, and the present invention provides non-limiting examples.

[0093] For example, block diagram S9 may include forming an electromagnetic interference (EMI) shielding layer 170 on the top and lateral surfaces of the encapsulation body 130 and / or on the top surface (or any exposed surface) of the conductive shielding member 110 exposed from the encapsulation body 130. For example, block diagram S8 may also include forming the EMI shielding layer 170 on the lateral side surfaces of the encapsulation body 130 and on the lateral side surfaces of the signal distribution structure 155 (e.g., the lateral side surfaces of the first dielectric layer 151, the lateral side surfaces of the second dielectric layer 152, the lateral side surfaces of the second dielectric layer 152, the lateral side surfaces of the conductive layer 140 if exposed, etc.).

[0094] For example, the EMI shielding layer 170 may be directly formed on at least one top surface of each of the one or more conductive shielding members 110, and thus electrically connected to the aforementioned conductive shielding members 110. In an exemplary embodiment, the EMI shielding layer 170 and the conductive shielding members 110 may be electrically connected to ground (or other constant-potential conductors). The EMI shielding layer 170 may shield electromagnetic waves generated by the electronic components 121 and 122 (or any component in the encapsulation material 130) to prevent the aforementioned electromagnetic waves from being emitted to the outside, and may shield electromagnetic waves transmitted from the outside to prevent the aforementioned electromagnetic waves from penetrating the electronic device to the electronic components 121 and 122. In addition, the conductive shielding member 110 may prevent EMI from occurring between the first electronic component 121 and the second electronic component 122.

[0095] For example, block diagram S9 may include forming the EMI shielding layer 170 on the encapsulation body 130 by coating a conductive paste containing conductive metal powder (for example, by spray coating, sputtering, etc.), by spraying or vapor depositing conductive paint, by using any or all of the steps discussed herein related to forming the conductive layer 140, etc., but the scope of the present invention should not be limited to this.

[0096] In summary, various aspects of the present invention provide semiconductor devices and methods for manufacturing semiconductor devices. As non-limiting examples, various aspects of the present invention provide semiconductor devices and methods for manufacturing the same including one or more conductive shielding members and EMI shielding layers. Although the foregoing has been described with reference to certain aspects and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt specific circumstances or materials to the teachings of the present invention without departing from the scope of the present invention. Therefore, the purpose of the present invention is not to be limited to the specific examples disclosed, but the present invention will include all examples that fall within the scope of the attached patent application.

Claims

1. An electronic device, comprising: a signal distribution structure having a top side and a bottom side; a first electronic component coupled to the top side of the signal distribution structure; a second electronic component coupled to the top side of the signal distribution structure; a conductive shielding member coupled to the top side of the signal distribution structure and positioned directly between the first electronic component and the second electronic component; an encapsulation material covering at least a portion of the top side of the signal distribution structure, at least a portion of a lateral side of the first electronic component, at least a portion of a lateral side of the second electronic component, and at least a portion of a lateral side of the conductive shielding member; as well as An electromagnetic interference shielding layer is on a top side of the encapsulation material and on a top side of the conductive shielding member, wherein the electromagnetic interference shielding layer is electrically coupled to the top side of the conductive shielding member.

2. The electronic device of claim 1, wherein no intermediate layer is between the first electronic component and the signal distribution structure, and no intermediate layer is between the second electronic component and the signal distribution structure.

3. The electronic device of claim 1, wherein: The conductive shielding member includes a seed layer and a conductive layer formed on the seed layer; and Respective surfaces of each of the first electronic component, the second electronic component, the seed layer, and the encapsulation material are coplanar.

4. The electronic device of claim 1, wherein: The conductive shield member is solder-free; The conductive shielding member is directly connected to the signal distribution structure without using solder; and The conductive shielding member is directly connected to the EMI shielding layer without using solder.

5. The electronic device of claim 1, wherein respective surfaces of each of the first electronic component, the second electronic component, the conductive shielding member, and the encapsulating material are coplanar.

6. The electronic device of claim 1, wherein a respective surface of at least one of the first electronic component, the second electronic component, the conductive shielding member, and the encapsulating material is a polished surface.

7. The electronic device of claim 1, wherein: The conductive shielding member includes a seed layer and a conductive layer formed on the seed layer; and A bottom surface of the conductive layer of the conductive shield member is higher than the bottom surfaces of the first electronic component and the second electronic component.

8. The electronic device of claim 1, wherein the encapsulating material covers all lateral sides of the conductive shield member and covers all lateral sides and a top side of the first electronic component and the second electronic component.

9. The electronic device of claim 1, wherein the EMI shielding layer covers lateral sides of the encapsulation material and lateral sides of the signal distribution structure.

10. An electronic device comprising: a signal distribution structure having a signal distribution structure top side and a signal distribution structure bottom side, and at least a first signal distribution structure conductive layer; a first electronic component coupled to the top side of the signal distribution structure and comprising a first component terminal, a first portion of the first conductive layer being formed directly on the first component terminal; a second electronic component coupled to the top side of the signal distribution structure and comprising a second component terminal, a second portion of the first conductive layer being formed directly on the second component terminal; a conductive shielding member coupled to the top side of the signal distribution structure and disposed directly between the first electronic component and the second electronic component; an encapsulation material covering at least a portion of the top side of the signal distribution structure, at least a portion of a lateral side of the first electronic component, at least a portion of a lateral side of the second electronic component, and at least a portion of a lateral side of the conductive shield member; as well as An electromagnetic interference shielding layer is on a top side of the encapsulation material and on a top side of the conductive shielding member, wherein the electromagnetic interference shielding layer is electrically coupled to the top side of the conductive shielding member.

11. The electronic device of claim 10, wherein no intervening layers are between a bottom side of the first electronic component and the signal distribution structure, and no intervening layers are between a bottom side of the second electronic component and the signal distribution structure.

12. The electronic device of claim 10, wherein: The conductive shielding member comprises a conductive shielding member seed layer and a conductive shielding member conductive layer, wherein the conductive shielding member conductive layer is directly plated on the conductive shielding member seed layer; A top end of the conductive shield member conductive layer is coplanar with a top side of the encapsulation material; as well as Respective surfaces of each of the first electronic component, the second electronic component, the conductive shield member seed layer, and the encapsulation material are coplanar.

13. The electronic device of claim 10, wherein: The conductive shielding member comprises a conductive shielding member seed layer and a conductive shielding member conductive layer, the conductive shielding member conductive layer being directly plated on the conductive shielding member seed layer; and The bottom end of the conductive layer of the conductive shielding member is vertically higher than the bottom side of the first electronic component.

14. The electronic device of claim 10, wherein no portion of the EMI shielding layer is directly between the signal distribution structure and the encapsulation material.

15. An electronic device comprising: a signal distribution structure having a signal distribution structure top side and a signal distribution structure bottom side, and at least a first signal distribution structure conductive layer; a first electronic component coupled to the signal distribution structure top side and comprising a first component terminal coupled to the first signal distribution structure conductive layer, the first component terminal being on a bottom side of the first electronic component; a second electronic component coupled to the signal distribution structure top side and including a second component terminal coupled to the first signal distribution structure conductive layer, the second component terminal being on a bottom side of the second electronic component; a conductive shielding member coupled to the top side of the signal distribution structure and disposed directly between the first electronic component and the second electronic component, wherein a bottom side of the conductive shielding member is vertically higher than a bottom side of the first electronic component; an encapsulation material covering at least a portion of a top side of the signal distribution structure, at least a portion of lateral sides of the first and second electronic components, and at least a portion of lateral sides of the conductive shielding member; as well as An electromagnetic interference shielding layer is on a top side of the encapsulation material and on a top side of the conductive shielding member, wherein the electromagnetic interference shielding layer is directly coupled to the top side of the conductive shielding member.

16. The electronic device of claim 15, wherein the conductive shielding member comprises a seed layer, the seed layer being directly coupled to a top side of the signal distribution structure.

17. The electronic device of claim 16, wherein the encapsulation material laterally surrounds the seed layer.

18. The electronic device of claim 15, wherein the encapsulating material laterally surrounds the entire conductive shield member.

19. The electronic device of claim 18, wherein the encapsulating material comprises a molding material molded around the conductive shield member.

20. The electronic device of claim 15, wherein the signal distribution structure comprises a dielectric layer deposited directly on the first component terminal and directly on the second component terminal.

21. The electronic device of claim 20, wherein the dielectric layer is deposited directly on the conductive shield member.

22. The electronic device of claim 15, wherein a top side of the conductive shielding member is coplanar with a top side of the encapsulating material.

23. An electronic device comprising: a signal distribution structure having a signal distribution structure top side and a signal distribution structure bottom side, and at least a first signal distribution structure conductive layer; a first electronic component coupled to the signal distribution structure top side and comprising a first component terminal coupled to the first signal distribution structure conductive layer via a solder-free and adhesive-free connection; a second electronic component coupled to the signal distribution structure top side and comprising a second component terminal coupled to the first signal distribution structure conductive layer via a solder-free and adhesive-free connection; a conductive shielding member coupled to the top side of the signal distribution structure by a solder-free and adhesive-free connection and disposed directly between the first electronic component and the second electronic component; an encapsulation material covering at least a portion of a top side of the signal distribution structure, at least a portion of lateral sides of the first and second electronic components, and at least a portion of lateral sides of the conductive shielding member; as well as An electromagnetic interference shielding layer is on a top side of the encapsulation material and on a top side of the conductive shielding member, wherein the electromagnetic interference shielding layer is coupled to the top side of the conductive shielding member.

24. The electronic device of claim 23, wherein the signal distribution structure comprises a signal distribution structure dielectric layer deposited directly on the first component terminal, directly on the second component terminal, and directly on the conductive shielding member.

25. The electronic device of claim 24, wherein no intermediate layer is between the signal distribution structure dielectric layer and the first electronic component, and no intermediate layer is between the signal distribution structure dielectric layer and the second electronic component.

26. The electronic device of claim 23, wherein the conductive shielding member comprises a plurality of metal layers laterally surrounded by the encapsulating material.

27. The electronic device of claim 26, wherein the multi-layer metal layer comprises an electroplating seed layer and an electroplating metal layer.

28. The electronic device of claim 23, comprising a second conductive shield member coupled to the top side of the signal distribution structure and disposed directly between the first electronic component and the second electronic component. 29 . The electronic device of claim 23 , wherein the signal distribution structure comprises a plurality of dielectric layers, wherein the plurality of dielectric layers are sequentially constructed on the first electronic component, the second electronic component, the conductive shielding member, and the encapsulation material.

30. An electronic device comprising: a signal distribution structure comprising a signal distribution structure top side and a signal distribution structure bottom side, and a signal distribution structure conductive layer; a first electronic component coupled to the top side of the signal distribution structure and comprising a first interconnect, a first portion of the signal distribution structure conductive layer being formed directly on the first interconnect; a second electronic component coupled to the top side of the signal distribution structure and comprising a second interconnect, a second portion of the signal distribution structure conductive layer being formed directly on the second interconnect; a conductive shielding member coupled to a top side of the signal distribution structure and disposed directly between the first electronic component and the second electronic component; an encapsulation material covering at least a portion of a top side of the signal distribution structure, at least a portion of lateral sides of the first and second electronic components, and at least a portion of lateral sides of the conductive shielding member; An electromagnetic interference shielding layer is on a top side of the encapsulation material and on a top side of the conductive shielding member, wherein the electromagnetic interference shielding layer is electrically coupled to the top side of the conductive shielding member.

31. The electronic device of claim 30, wherein no portion of the encapsulating material is vertically below a lowermost end of the first interconnect.

32. The electronic device of claim 30, wherein: the conductive shielding member comprising a conductive shielding member seed layer and a conductive shielding member conductive layer, the conductive shielding member conductive layer being placed directly on the conductive shielding member seed layer; and A bottom end of the conductive layer of the conductive shield member is vertically higher than a bottom side of the first interconnect.

33. The electronic device of claim 30, wherein no portion of the EMI shielding layer is directly between the signal distribution structure and the encapsulation material.

34. The electronic device of claim 30, wherein the encapsulating material comprises a molded material that is molded integrally around and laterally around the conductive shield member.

35. The electronic device of claim 30, wherein: The signal distribution structure includes a plurality of signal distribution structure lateral sides extending between the signal distribution structure top side and the signal distribution structure bottom side; and The conductive shielding member extends laterally between two adjacent lateral sides of the lateral side of the signal distribution structure.

36. The electronic device of claim 30, wherein: The signal distribution structure includes a plurality of signal distribution structure lateral sides extending between the signal distribution structure top side and the signal distribution structure bottom side; and The conductive shielding member is one of a plurality of conductive shielding members, the plurality of conductive shielding members forming a shielding pattern, the shielding pattern extending laterally between two adjacent lateral sides of the lateral side of the signal distribution structure.

37. The electronic device of claim 30, wherein the first interconnect is disposed at a bottom side of the first electronic component and does not protrude from the bottom side of the first electronic component.

38. An electronic device comprising: a signal distribution structure comprising a signal distribution structure top side and a signal distribution structure bottom side, and a signal distribution structure conductive layer; a first electronic component coupled to the signal distribution structure top side and comprising a first interconnect coupled to the signal distribution structure conductive layer, the first interconnect disposed on a bottom side of the first electronic component; a second electronic component coupled to the signal distribution structure top side and comprising a second interconnect coupled to the signal distribution structure conductive layer, the second interconnect disposed on a bottom side of the second electronic component; a conductive shielding member coupled to the signal distribution structure top side and disposed directly between the first electronic component and the second electronic component, wherein the conductive shielding member includes a seed layer, the seed layer coupled directly to the signal distribution structure top side; an encapsulation material covering at least a portion of a top side of the signal distribution structure, at least a portion of lateral sides of the first and second electronic components, and at least a portion of lateral sides of the conductive shielding member, wherein the encapsulation material laterally surrounds the seed layer; as well as An electromagnetic interference shielding layer is on a top side of the encapsulation material and on a top side of the conductive shielding member, wherein the electromagnetic interference shielding layer is electrically coupled to the top side of the conductive shielding member.

39. The electronic device of claim 38, wherein a bottom side of the conductive shield member is vertically higher than a bottom side of the first interconnect.

40. The electronic device of claim 38, wherein the encapsulating material laterally surrounds the entirety of the conductive shield member.

41. The electronic device of claim 38, wherein the encapsulating material comprises a molding material molded laterally around the entirety of the conductive shield member.

42. The electronic device of claim 38, wherein a top side of the conductive shielding member is coplanar with a top side of the encapsulating material.

43. The electronic device of claim 38, wherein: The signal distribution structure comprises a plurality of signal distribution structure lateral sides extending between the signal distribution structure top side and the signal distribution structure bottom side; and The conductive shielding member is one of a plurality of conductive shielding members, the plurality of conductive shielding members forming a shielding pattern, the shielding pattern extending laterally between two adjacent lateral sides of the lateral side of the signal distribution structure.

44. An electronic device comprising: a signal distribution structure comprising a signal distribution structure top side and a signal distribution structure bottom side, and a signal distribution structure conductive layer; a first electronic component coupled to the signal distribution structure top side and comprising a first interconnect coupled to the signal distribution structure conductive layer; a second electronic component coupled to the signal distribution structure top side and comprising a second interconnect coupled to the signal distribution structure conductive layer; a conductive shielding member coupled to the top side of the signal distribution structure by a solder-free and adhesive-free connection and disposed directly between the first electronic component and the second electronic component; an encapsulation material covering at least a portion of a top side of the signal distribution structure, at least a portion of lateral sides of the first and second electronic components, and at least a portion of lateral sides of the conductive shielding member; as well as An electromagnetic interference shielding layer is on a top side of the encapsulation material and on a top side of the conductive shielding member, wherein the electromagnetic interference shielding layer is electrically coupled to the top side of the conductive shielding member.

45. The electronic device of claim 44, wherein the signal distribution structure comprises a signal distribution structure dielectric layer deposited directly on the first interconnect, directly on the second interconnect, and directly on the conductive shielding member.

46. ​​The electronic device of claim 44, wherein no portion of the encapsulating material is vertically below a lowermost end of the first interconnect.

47. The electronic device of claim 44, wherein the conductive shielding member comprises a plurality of metal layers, the encapsulating material laterally surrounding the plurality of metal layers.

48. The electronic device of claim 44, wherein the signal distribution structure comprises a signal distribution structure dielectric layer deposited directly on the first interconnect, directly on the second interconnect, and directly on the conductive shielding member.

49. The electronic device of claim 44, wherein: The signal distribution structure includes a plurality of signal distribution structure lateral sides extending between the signal distribution structure top side and the signal distribution structure bottom side; and The conductive shielding member is one of a plurality of conductive shielding members forming a shielding pattern extending between two adjacent lateral sides of the lateral side of the signal distribution structure.

50. A method of manufacturing an electronic device, the method comprising: A first structure is provided, the first structure comprising: A signal distribution structure, the signal distribution structure comprising a signal distribution structure top side, a signal distribution structure bottom side, a signal distribution structure lateral side, and a signal distribution structure conductive layer; a first electronic component coupled to the signal distribution structure top side and comprising a first interconnect coupled to the signal distribution structure conductive layer; a second electronic component coupled to the signal distribution structure top side and comprising a second interconnect coupled to the signal distribution structure conductive layer; a conductive shielding member coupled to the top side of the signal distribution structure and disposed directly between the first electronic component and the second electronic component, wherein the conductive shielding member comprises: a conductive shielding member bottom side, the conductive shielding member bottom side coupled to the signal distribution structure top side; a top side of the conductive shield member; as well as a lateral side of the conductive shield member; as well as an encapsulation material covering at least a portion of a top side of the signal distribution structure, at least a portion of a lateral side of the first electronic component, at least a portion of a lateral side of the second electronic component, and at least a portion of a lateral side of the conductive shield member; and After providing the first structure: An electromagnetic interference shielding layer is formed on the top side of the encapsulation material and on the conductive shielding member top side, wherein the electromagnetic interference shielding layer includes a bottom side coupled to the conductive shielding member top side.

51. The method of claim 50, wherein forming the electromagnetic interference shielding layer comprises forming the electromagnetic interference shielding layer to contact a lateral side of the signal distribution structure.

52. The method of claim 50, wherein providing the first structure comprises connecting a bottom side of the conductive shield member and a top side of the signal distribution structure with solderless connections.

53. The method of claim 50, wherein providing the first structure comprises: forming the encapsulating material; and After the encapsulation material is formed, the substrate is coupled to the first electronic component.

54. The method of claim 50, wherein providing the first structure comprises: providing an initial structure comprising the first electronic component, the second electronic component, the conductive shielding member, and the encapsulating material; and After the initial structure is formed, a next structure is formed, wherein the next structure includes the signal distribution structure coupled to the initial structure.

55. The method of claim 50, wherein providing the first structure comprises plating at least a portion of the conductive shield member.

56. The method of claim 50, wherein providing the first structure comprises forming a plurality of additional conductive shielding members, wherein: The conductive shielding member and the additional conductive shielding member are arranged in a row; and The aforementioned forming of the electromagnetic interference shielding layer includes directly forming the electromagnetic interference shielding layer on the top side of the conductive shielding member and on the respective top side of each of the additional conductive shielding members.

57. The method of claim 50, wherein the aforementioned forming of the electromagnetic interference shielding layer includes forming the electromagnetic interference shielding layer on multiple lateral sides of the encapsulation material and on multiple lateral sides of the signal distribution structure without forming any of the electromagnetic interference shielding layer directly between the encapsulation material and the signal distribution structure.

58. The method of claim 50, wherein: The encapsulation material includes a lateral side, the lateral side being coplanar with the lateral side of the signal distribution structure; and The forming of the electromagnetic interference shielding layer includes forming a continuous metal layer on the lateral side of the encapsulation material and on the lateral side of the signal distribution structure.

59. The method of claim 50, wherein providing the first structure comprises: forming the conductive shielding member on a top side of a carrier; coupling a bottom side of the first electronic component to the top side of the carrier; coupling a bottom side of the second electronic component to the top side of the carrier; as well as The encapsulation material is formed to cover at least a portion of the top side of the carrier.

60. The method of claim 50, wherein forming the EMI shielding layer comprises forming the EMI shielding layer directly on lateral sides of the signal distribution structure but not directly on a top side of the signal distribution structure and a bottom side of the signal distribution structure.

61. The method of claim 50, wherein: The conductive shield member is solder-free; Providing the first structure includes coupling the conductive shielding member and the top side of the signal distribution structure to each other without using solder or adhesive; and The forming of the EMI shielding layer includes coupling the bottom side of the EMI shielding layer and the top side of the conductive shielding member to each other without using solder or adhesive.

62. The method of claim 50, wherein said providing said first structure comprises thinning said encapsulating material to expose said conductive shielding member top side while leaving a respective top side of each of said first electronic component and said second electronic component covered by said encapsulating material.

63. A method of manufacturing an electronic device, the method comprising: A first structure is provided, the first structure comprising: A signal distribution structure, the signal distribution structure comprising a signal distribution structure top side, a signal distribution structure bottom side, a signal distribution structure lateral side and a signal distribution structure conductive layer; a first electronic component coupled to the signal distribution structure top side and comprising a first interconnect coupled to the signal distribution structure conductive layer; a second electronic component coupled to the signal distribution structure top side and comprising a second interconnect coupled to the signal distribution structure conductive layer; a conductive shielding member coupled to the top side of the signal distribution structure and disposed directly between the first electronic component and the second electronic component, wherein the conductive shielding member comprises: a conductive shielding member bottom side coupled to the signal distribution structure top side through at least one intermediate material; a top side of the conductive shield member; as well as a lateral side of the conductive shield member; as well as an encapsulation material covering at least a portion of a top side of the signal distribution structure, at least a portion of a lateral side of the first electronic component, at least a portion of a lateral side of the second electronic component, and at least a portion of a lateral side of the conductive shielding member; and After providing the first structure: An electromagnetic interference shielding layer is formed on the top side of the conductive shielding member.

64. The method of claim 63, wherein providing the first structure comprises thinning the encapsulation material to expose the top side of the conductive shielding member while leaving the top side of the first electronic component and the top side of the second electronic component covered by the encapsulation material.

65. The method of claim 63, wherein the encapsulation material laterally surrounds at least a portion of the first interconnect and at least a portion of the second interconnect.

66. The method of claim 63, wherein the conductive shield member comprises a solid wall that spans laterally across an entire lateral side of the first electronic component and spans laterally across an entire lateral side of the second electronic component.

67. The method of claim 63, wherein said forming of said electromagnetic interference shielding layer comprises forming said electromagnetic interference shielding layer on a top side of said encapsulation material and on lateral sides of said encapsulation material without forming any of said electromagnetic interference shielding layer directly vertically between said encapsulation material and said signal distribution structure.

68. The method of claim 63, wherein: The conductive shield member is solder-free; and The aforementioned forming of the electromagnetic interference shielding layer includes forming the electromagnetic interference shielding layer connected to the top side of the conductive shielding member in a solder-free and adhesive-free manner.

69. The method of claim 63, wherein the first interconnect is coupled to a bottom side of the first electronic component.

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