Semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device and a method for manufacturing the same are provided. The semiconductor memory device includes a memory pad on a substrate; a lower electrode on the memory pad and including a trench defined by a bottom and sidewalls of the lower electrode; a lower support pattern including a first portion in the trench and a second portion on an upper surface of the lower electrode; an upper support pattern on an upper surface of the lower support pattern; a capacitor dielectric film on the lower electrode, the lower support pattern, and the upper support pattern; and an upper electrode on the capacitor dielectric film.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0141822 filed on October 23, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention generally relates to a semiconductor memory device and a method for manufacturing the semiconductor memory device. Background Art

[0003] Recently, as semiconductor memory devices have become larger in capacity and more highly integrated, design rules have been reduced. This trend also appears in dynamic random access memory (DRAM), which is one type of semiconductor memory device. In order for a DRAM device to work, each cell requires a certain level or more of capacitance.

[0004] In order to increase the capacitance, a scheme of increasing the aspect ratio (height-width ratio) of the lower electrode of the capacitor or increasing the contact area between the lower electrode and the dielectric film of the capacitor is being studied. When the aspect ratio of the lower electrode of the capacitor is increased, a support member that can support the lower electrode of the capacitor is used to prevent the lower electrode from tilting or bending. Summary of the invention

[0005] A technical object that the present disclosure aims to achieve is to provide a semiconductor memory device with improved product reliability.

[0006] Another technical object that the present disclosure aims to achieve is to provide a method for manufacturing a semiconductor memory device with improved product reliability.

[0007] The purpose according to the present disclosure is not limited to the purpose mentioned above. Other purposes and advantages according to the present disclosure that are not mentioned can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the purposes and advantages according to the present disclosure can be achieved using the methods shown in the claims or their combinations.

[0008] According to an embodiment of the present disclosure, a semiconductor memory device includes: a storage pad on a substrate; a lower electrode on the storage pad and including a groove; a lower supporting pattern including a first portion at least partially filling the groove and a second portion on an upper surface of the lower electrode; an upper supporting pattern on an upper surface of the lower supporting pattern; a capacitor dielectric film on the lower electrode, the lower supporting pattern and the upper supporting pattern; and an upper electrode on the capacitor dielectric film.

[0009] According to an embodiment of the present disclosure, a semiconductor memory device includes: a storage pad on a substrate; a lower electrode on the storage pad and including a groove; a lower supporting pattern at least partially filling the groove and extending along an upper surface of the lower electrode and along an outer wall of a top of the lower electrode; a capacitor dielectric film on the lower electrode and the lower supporting pattern; and an upper electrode on the capacitor dielectric film.

[0010] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes: sequentially forming an etch stop film and a mold film on a substrate; forming a lower electrode hole (i.e., an opening) extending through the etch stop film and the mold film; forming a lower electrode, the lower electrode extending along the lower electrode hole and including a groove; forming a lower support pattern, the lower support pattern at least partially filling the groove and extending along an upper surface of the mold film; forming an upper support pattern on the lower support pattern; removing the mold film to expose a portion of the lower electrode, a portion of the lower support pattern, and a portion of the upper support pattern; forming a capacitor dielectric film extending along the exposed portion of the lower electrode, the exposed portion of the lower support pattern, and the exposed portion of the upper support pattern; and forming an upper electrode on the capacitor dielectric film. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the accompanying drawings, in which like reference numerals (when used) indicate corresponding elements throughout the several views, and in which: Figure 1 is a schematic plan view for illustrating a semiconductor memory device according to some embodiments; Figure 2 It is along Figure 1 The line II intercepts Figure 1 An illustrative schematic cross-sectional view of a semiconductor memory device shown in; Figures 3 to 10 are schematic cross-sectional views depicting intermediate structures corresponding to intermediate steps of an example method for fabricating a semiconductor memory device according to some embodiments; Fig.11 is a schematic cross-sectional view for illustrating a semiconductor memory device according to some embodiments; Fig.12 and Fig.13 is a schematic cross-sectional view of an intermediate structure corresponding to an intermediate step of an example method for fabricating a semiconductor memory device according to some embodiments; Fig.14 is a schematic cross-sectional view for illustrating a semiconductor memory device according to some embodiments; Fig.15is a schematic cross-sectional view of an intermediate structure corresponding to an intermediate step of an example method for fabricating a semiconductor memory device according to some embodiments; Figures 16 to 18 is a schematic diagram for illustrating a semiconductor memory device according to some embodiments; Fig.19 is a schematic layout diagram (ie, a top view) for illustrating a semiconductor memory device according to some embodiments; Fig. 20 is a schematic perspective view for illustrating a semiconductor memory device according to some embodiments; Fig.21 It is along Fig.19 The lines CC and DD in Fig.19 A schematic cross-sectional view of a semiconductor memory device shown in FIG. Fig. 22 is a schematic layout diagram for illustrating a semiconductor memory device according to some embodiments; and Fig.23 is a schematic perspective view of a semiconductor memory device for illustrating some embodiments. DETAILED DESCRIPTION

[0012] Figure 1 is a schematic plan view for illustrating an example semiconductor memory device according to some embodiments. Figure 2 It is along Figure 1 The line II intercepts Figure 1 An exemplary schematic cross-sectional view of a semiconductor memory device is shown in FIG.

[0013] Reference Figure 1 and Figure 2 , a semiconductor memory device according to some embodiments includes a substrate 100 , a memory pad 104 , and a capacitor structure 300 .

[0014] The substrate 100 may include bulk silicon or SOI (silicon on insulator). Alternatively, the substrate 100 may be a silicon substrate, or may include materials other than silicon such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, etc. However, the present disclosure is not limited thereto. In the following description, an example in which the substrate 100 is implemented as a silicon substrate will be described.

[0015] The interlayer insulating film 102 is disposed on the substrate 100. For example, the interlayer insulating film 102 may include at least one of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and combinations thereof, but the embodiment is not limited thereto. The interlayer insulating film 102 may be a single layer or multiple layers.

[0016] The storage contact 103 and the storage pad 104 are arranged on the substrate 100. The storage contact 103 and the storage pad 104 are arranged in the interlayer insulating film 102. The storage pad 104 is arranged on the storage contact 103. The storage pad 104 can be connected to the substrate 100 via the storage contact 103. As used herein, the term "connection" (and its variations, or similar terms such as "contact") is intended to refer to the physical connection and / or electrical connection between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. The storage pad 104 can be electrically connected to a conductive area formed on or in the substrate 100.

[0017] The etching stop film 105 may be disposed on the interlayer insulating film 102. The etching stop film 105 may not cover at least a portion of the upper surface of the storage pad 104 so as to expose the at least a portion of the upper surface of the storage pad 104. The term "covering" (and its variations, or similar terms) as used herein is intended to broadly refer to an element, structure or layer directly on or above another element, structure or layer, or there are one or more other intermediate elements, structures or layers between them. In addition, the term "exposing" (and its variations, or similar terms) may be used herein to describe the relationship between elements and / or to refer to an intermediate process in manufacturing a semiconductor device, but may not require that a specific element be exposed in a completed device. Similarly, the term "unexposed" may be used to describe the relationship between elements and / or to refer to an intermediate process in manufacturing a semiconductor device, but may not require that a specific element be unexposed in a completed device. The etching stop film 105 may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon carbonate (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon oxycarbonitride (SiOCN). For example, silicon carbonate (SiCO) refers to a film including silicon (Si), carbon (C), and oxygen (O), but does not indicate the ratio between the contents of silicon (Si), carbon (C), and oxygen (O).

[0018] The capacitor structure 300 may be disposed on the memory pad 104. The capacitor structure 300 may include a lower electrode 310, a capacitor dielectric film 320, an upper electrode 330, and an upper plate electrode 340.

[0019] The lower electrode 310 may be disposed on the memory pad 104. The lower electrode 310 may extend through the etch stop film 105 in a vertical direction D3 perpendicular to the upper surface of the substrate 100 to be electrically connected to the memory pad 104.

[0020] The lower electrode 310 may be arranged in a honeycomb structure. That is, the lower electrode 310 may be located at the center and the vertex of the hexagon, respectively. The lower electrode 310 may be arranged to be spaced apart from each other at equal intervals in the first direction D1. The lower electrode 310 may be repeatedly arranged along each of the first direction D1 and the second direction D2. Hereinafter, the first direction D1 and the second direction D2 are directions parallel to the upper surface of the substrate 100. The second direction D2 is a direction perpendicular to the first direction D1. The third direction D3 may be a vertical direction perpendicular to the upper surface of the substrate 100. The upper surface, the lower surface, the upper portion, and the lower portion are defined based on the third direction D3.

[0021] The lower electrode 310 extends in an elongated (i.e., longitudinal) manner in the third direction D3. The lower electrode 310 may have a cylindrical shape, but the embodiment is not limited thereto. The lower electrode 310 includes a bottom 311 extending horizontally along the upper surface of the storage pad 104 and a vertical portion 312 extending from the bottom 311 in the third direction D3. The length of the vertical portion 312 in the direction in which the vertical portion 312 extends (i.e., the third direction D3) may be greater than the length of the bottom 311 in the direction in which the bottom 311 extends; that is, the lower electrode 310 may be formed as a high aspect ratio (or height-to-width ratio) structure. The groove 310t may be defined by the bottom 311 and the vertical portion 312 of the lower electrode 310. The groove 310t extends from the upper surface 310us of the lower electrode 310 toward the substrate 100. When viewed in a top view, the upper surface 310us of the lower electrode 310 may have a circular ring shape. The upper surface 310 us of the lower electrode 310 is an upper surface of the vertical portion 312 .

[0022] In some embodiments, for example, the thickness of a portion of the lower electrode 310 defining the bottom surface of the trench 310t (e.g., the thickness of the bottom portion 311 in the third direction D3) may be substantially the same as the thickness of a portion of the lower electrode 310 defining the sidewall of the trench 310t (e.g., the width of the vertical portion 312 in the first direction D1). The thickness of a portion of the lower electrode 310 defining the sidewall of the trench 310t (e.g., the width of the vertical portion 312 in the first direction D1) may be substantially constant along the third direction D3.

[0023] In some embodiments, the width of the trench 310t in a direction parallel to the upper surface of the substrate 100 (e.g., the first direction D1 or the second direction D2) may be constant or decrease as the trench 310t extends in the third direction D3 toward the substrate 100. The thickness of a portion of the lower electrode 310 defining the sidewall of the trench 310t (e.g., the width of the vertical portion 312 in the first direction D1) may be constant or decrease as the vertical portion 312 extends toward the substrate 100.

[0024] The lower electrode 310 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), or a conductive metal oxide (e.g., iridium oxide or niobium oxide). However, the present disclosure is not limited thereto. In a semiconductor memory device according to some embodiments, the lower electrode 310 may include titanium nitride (TiN). Alternatively, in a semiconductor memory device according to some embodiments, the lower electrode 310 may include niobium nitride (NbN).

[0025] The first supporting pattern 210, the second supporting pattern 220, the lower supporting pattern 230, and the upper supporting pattern 240 may be sequentially disposed (e.g., stacked in the third direction D3) on the etch stop film 105. The first supporting pattern 210 may be spaced apart from the etch stop film 105 in the third direction D3. The second supporting pattern 220 may be spaced apart from the first supporting pattern 210 in the third direction D3. The lower supporting pattern 230 may be spaced apart from the second supporting pattern 220 in the third direction D3. The upper supporting pattern 240 may be disposed on the lower supporting pattern 230.

[0026] The number of the supporting patterns 210, 220, 230, and 240 supporting the lower electrode 310 may vary. For example, only the lower supporting pattern 230 and the upper supporting pattern 240 may support the lower electrode 310. The relationship between the thickness of the first supporting pattern 210 in the third direction D3, the thickness of the second supporting pattern 220 in the third direction D3, the thickness of the lower supporting pattern 230 in the third direction D3, and the thickness of the upper supporting pattern 240 in the third direction D3 may vary. The relationship between the interval between the etching stop film 105 and the first supporting pattern 210, the interval between the first supporting pattern 210 and the second supporting pattern 220, and the interval between the second supporting pattern 220 and the lower supporting pattern 230 may vary.

[0027] The first support pattern 210, the second support pattern 220, the lower support pattern 230, and the upper support pattern 240 may be sequentially spaced apart from each other and may be disposed on the sidewall of the lower electrode 310. Each of the first support pattern 210, the second support pattern 220, the lower support pattern 230, and the upper support pattern 240 may contact a portion of the sidewall of the lower electrode 310. The first support pattern 210, the second support pattern 220, the lower support pattern 230, and the upper support pattern 240 may connect adjacent lower electrodes 310 to each other. In the accompanying drawings, the three lower electrodes 310 are shown as being connected to each other via the first support pattern 210, the second support pattern 220, the lower support pattern 230, and the upper support pattern 240. However, the present disclosure is not limited thereto.

[0028] The lower support pattern 230 includes a first portion 231 and a second portion 232. The lower support pattern 230 has an integral structure. That is, the first portion 231 and the second portion 232 are integral with each other to directly contact each other without an internal boundary therebetween (i.e., the lower support pattern 230 is formed as a homogeneous structure including the first portion 231 and the second portion 232).

[0029] The first portion 231 fills the trench 310t of the lower electrode 310. For example, the first portion 231 may fill the entire trench 310t of the lower electrode 310. The term "fill" (and its variations, or similar terms) as may be used herein is intended to broadly refer to completely filling a defined space (e.g., the trench 310t) or partially filling a defined space; that is, the defined space need not be completely filled, but may, for example, be partially filled or have a void or other space running therethrough.

[0030] The second portion 232 is connected to the first portion 231. The second portion 232 is disposed on the upper surface 310us of the lower electrode 310. The second portion 232 extends along the upper surface 310us of the lower electrode 310. The second portion 232 may contact the upper surface 310us of the lower electrode 310. The second portion 232 may extend in a direction parallel to the upper surface of the substrate 100 (e.g., the first direction D1 or the second direction D2).

[0031] The upper surface 232us of the second portion 232 may include a protruding portion in a direction (i.e., the third direction D3) opposite to the direction toward the substrate 100 (i.e., away from the substrate 100). For example, the upper surface 232us of the second portion 232 overlapping the lower electrode 310 in the third direction D3 may protrude in the third direction D3. The term "overlap" (and its variations, or similar terms) as used herein is intended to broadly refer to a first element intersecting at least a portion of a second element in a vertical direction (i.e., the third direction D3), but does not require that the first element and the second element be completely aligned with each other in a horizontal plane (i.e., in the first direction D1 or the second direction D2).

[0032] In some embodiments, the second portion 232 extends along the outer wall of the top of the lower electrode 310. The second portion 232 may contact the outer wall of the top of the lower electrode 310. The second portion 232 surrounds the top of the lower electrode 310. With respect to the upper surface of the substrate 100 as a reference surface, the lowermost surface 232ls of the second portion 232 is located at a vertical height lower than the vertical height of the upper surface 310us of the lower electrode 310. With respect to the upper surface of the substrate as a reference surface, the portion of the lower surface 232ls of the second portion 232 that does not overlap with the lower electrode 310 in the third direction D3 is located at a vertical height lower than the vertical height of the upper surface 310us of the lower electrode 310.

[0033] The upper support pattern 240 may be disposed on the upper surface of the lower support pattern 230 (i.e., the upper surface 232us of the second portion 232). The upper support pattern 240 contacts the upper surface of the lower support pattern 230. The upper support pattern 240 extends along the lower support pattern 230, so the lower surface of the upper support pattern 240 may be non-planar. The upper surface 240us of the upper support pattern 240 may be flat (i.e., planar).

[0034] Each of the first supporting pattern 210, the second supporting pattern 220, the lower supporting pattern 230, and the upper supporting pattern 240 may include a material different from that of the lower electrode 310. Each of the first supporting pattern 210, the second supporting pattern 220, the lower supporting pattern 230, and the upper supporting pattern 240 may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon carbonate (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon oxycarbonitride (SiOCN).

[0035] In some embodiments, the lower supporting pattern 230 and the upper supporting pattern 240 may include the same material. For example, each of the lower supporting pattern 230 and the upper supporting pattern 240 may include silicon carbon nitride (SiCN). In some other embodiments, the lower supporting pattern 230 and the upper supporting pattern 240 may include different materials.

[0036] The through holes PH may be defined between the lower electrodes 310 adjacent to each other. The through holes PH may be spaced apart from each other in the first direction D1 and the second direction D2. Figure 1 ), the through hole PH may be formed in a circular shape and may be defined between three adjacent lower electrodes 310. A portion of the side surface of each of the three lower electrodes 310 may be exposed through the through hole PH. However, the present disclosure is not limited thereto, and the through hole PH may be defined between a plurality of lower electrodes 310 and may be formed in various shapes. The through hole PH may extend through the first support pattern 210, the second support pattern 220, the lower support pattern 230, and the upper support pattern 240. The through hole PH may expose the etching stop film 105.

[0037] The capacitor dielectric film 320 may be disposed on the lower electrode 310, the first support pattern 210, the second support pattern 220, the lower support pattern 230, and the upper support pattern 240. The capacitor dielectric film 320 may extend along contours of the lower electrode 310, the upper and lower surfaces of the first support pattern 210, the upper and lower surfaces of the second support pattern 220, the lower and side surfaces of the lower support pattern 230, and the upper and side surfaces of the upper support pattern 240. The capacitor dielectric film 320 may fill at least a portion of the through hole PH.

[0038] The capacitor dielectric film 320 may include, for example, a high dielectric constant (high-k) material (including silicon oxide, silicon nitride, silicon oxynitride, and metal), but the embodiment is not limited thereto. The capacitor dielectric film 320 is shown as being formed as a single film. However, this is only for ease of illustration, and the present disclosure is not limited thereto.

[0039] The upper electrode 330 may be disposed on the capacitor dielectric film 320. The upper electrode 330 may extend along the outline of the capacitor dielectric film 320. The upper plate electrode 340 may be disposed on the upper electrode 330. The upper electrode 330 may be disposed between the capacitor dielectric film 320 and the upper plate electrode 340. The upper electrode 330 and the upper plate electrode 340 may fill the through hole PH, the space between the etch stop film 105 and the first supporting pattern 210, the space between the first supporting pattern 210 and the second supporting pattern 220, and the space between the second supporting pattern 220 and the lower supporting pattern 230.

[0040] The upper electrode 330 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), or a conductive metal oxide (e.g., iridium oxide or niobium oxide). However, the present disclosure is not limited thereto.

[0041] The upper plate electrode 340 may include, for example, at least one of an element semiconductor material film and a compound semiconductor material film. The upper plate electrode 340 may contain doped n-type impurities or p-type impurities.

[0042] In a semiconductor memory device according to some embodiments, the lower support pattern 230 fills the inner space (i.e., the groove 310t) defined by the lower electrode 310. In addition, in a semiconductor memory device according to some embodiments, the lower support pattern 230 may surround the top of the lower electrode 310. The term "surrounding" (and its variations, or similar terms) as used herein is intended to broadly refer to an element, structure, or layer surrounding, extending, encapsulating, surrounding, or enclosing another element, structure, or layer on all sides, but interruptions or gaps may also exist. Thus, for example, a material layer having a void or gap therein may still "surround" another layer that it surrounds. Thus, the lower electrode 310 may be prevented from tilting and bending. Thus, the reliability of the semiconductor memory device may be improved.

[0043] Figures 3 to 10 are schematic cross-sectional views depicting intermediate structures corresponding to intermediate steps of an example method for fabricating a semiconductor memory device according to some embodiments. For reference, Figures 3 to 10 It is along Figure 1 The line II in Figure 1 A cross-sectional view of an illustrative semiconductor memory device shown in FIG. For ease of description, the following description is mainly based on Figures 3 to 10 Combined with the above Figure 1 and Figure 2 The differences in the descriptions explained.

[0044] Reference Figure 3 , a storage contact 103 and a storage pad 104 may be formed in an interlayer insulating film 102 on a substrate 100. An etching stopper film 105 may be formed on the interlayer insulating film 102 and the storage pad 104.

[0045] Subsequently, a first mold film 205, a first support film 210p, a second mold film 215, a second support film 220p, and a third mold film 225 are formed in the following order (i.e., sequentially formed) on the etch stop film 105. The first support film 210p may include a material having an etching selectivity with respect to each of the first mold film 205 and the second mold film 215. The second support film 220p may include a material having an etching selectivity with respect to each of the second mold film 215 and the third mold film 225. Each of the first to third mold films 205, 215, and 225 may have a single-layer structure or a multi-layer structure including a plurality of different films.

[0046] Reference Figure 4, a lower electrode hole 310h extending through the etch stop film 105, the first mold film 205, the first support film 210p, the second mold film 215, the second support film 220p, and the third mold film 225 in the third direction D3 may be formed. A portion of the upper surface of the memory pad 104 may be exposed through the lower electrode hole 310h. In some embodiments, the lower electrode hole 310h may have a constant horizontal width. In some other embodiments, the lower electrode hole 310h may have a tapered shape in which the horizontal width decreases as the lower electrode hole 310h extends from its top to the bottom.

[0047] Reference Figure 5 , can be in the lower electrode hole 310h (see Figure 4 ) is formed on the sidewall and bottom of the third mold film 225. The lower electrode film 310p may be formed on the third mold film 225 and may at least partially fill the lower electrode hole 310h. The lower electrode film 310p may cover a portion of the upper surface of the memory pad 104 exposed by the lower electrode hole 310h and may cover the third mold film 225. For example, the lower electrode film 310p may be formed by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma enhanced ALD (PEALD).

[0048] The lower electrode film 310p may be formed along the lower electrode hole 310h and the upper surface of the third mold film 225. The lower electrode film 310p may be formed to fill the lower electrode hole 310h. The lower electrode film 310p may be formed along the contour of the lower electrode hole 310h. As the deposition of the lower electrode film 310p proceeds, the lower electrode film 310p may be formed on the inner wall defining the lower electrode hole 310h to fill the lower electrode hole 310h. In this case, an empty space IS may be formed inside the lower electrode film 310p. The empty space IS may define the inner wall of the lower electrode film 310p. The lower electrode film 310p may fill a portion of the lower electrode hole 310h.

[0049] In some embodiments, the width of the empty space IS in a direction parallel to the upper surface of the substrate 100 (eg, the first direction D1 or the second direction D2 ) may be substantially constant along the third direction D3 .

[0050] For example, a portion of the bottom surface of the lower electrode film 310p defining the empty space IS may have substantially the same thickness in the third direction D3 as a portion of the sidewall of the lower electrode film 310p defining the empty space IS in the first direction D1.

[0051] Reference Figure 5 and Figure 6 , the top of the lower electrode film 310p may be removed to form the lower electrode 310. For example, the top of the lower electrode film 310p may be removed by an etch-back process.

[0052] When the top of the lower electrode film 310p is removed, the empty space IS may be exposed so that the groove 310t may be formed. The groove 310t may be formed from the upper surface 310us (see FIG. 3 ) of the lower electrode 310 in the third direction D3. Figure 2 ) extends toward the substrate 100.

[0053] Reference Figure 7 , the top of the third mold film 225 may be removed. Therefore, the top of the lower electrode 310 may not be covered by the third mold film 225 to be exposed. With respect to the upper surface of the substrate 100 as a reference surface, the upper surface 310us of the lower electrode 310 may be located at a height higher than the upper surface 225us of the third mold film 225.

[0054] Reference Figure 8 , the lower support film 230p may be formed to fill the groove 310t and cover the third mold film 225 and the top of the lower electrode 310. The lower support film 230p may cover the upper surface 225us of the third mold film 225. Since the top of the lower electrode 310 is not covered by the third mold film 225 to be exposed, the upper surface 230pus of the lower support film 230p covering the lower electrode 310 (i.e., overlapping the lower electrode 310) may be convex and thus non-flat. The upper surface 230pus of the lower support film 230p may be converted later to Figure 2 The upper surface 230us of the lower support pattern 230 ( Figure 2 middle).

[0055] Reference Fig. 9 , an upper supporting film 240p may be formed on the lower supporting film 230p. The upper supporting film 240p may cover the lower supporting film 230p. Although the lower surface of the upper supporting film 240p is non-planar to correspond to the contour of the upper surface 230pus of the lower supporting film 230p, the upper surface 240pus of the upper supporting film 240p may be flat. The upper surface 240pus of the upper supporting film 240p may be subsequently converted to Figure 2 The upper surface 240us of the upper support pattern 240 ( Figure 2 middle).

[0056] Reference Fig. 9 and Fig.10, a through hole PH extending through the first mold film 205, the first support film 210p, the second mold film 215, the second support film 220p, the third mold film 225, the lower support film 230p, and the upper support film 240p may be formed. The outer walls of some of the lower electrodes 310 adjacent to each other in the first direction D1 and a portion of the upper surface of the etching stop film 105 may be exposed through the through hole PH. Therefore, the first support pattern 210, the second support pattern 220, the lower support pattern 230, and the upper support pattern 240 may be formed. The portions of the first support film 210p, the second support film 220p, the lower support film 230p, and the upper support film 240p that are not etched but remain may become the first support pattern 210, the second support pattern 220, the lower support pattern 230, and the upper support pattern 240, respectively.

[0057] The first mold film 205, the second mold film 215, and the third mold film 225 exposed through the through hole PH may be removed. For example, the first mold film 205, the second mold film 215, and the third mold film 225 may be removed by a wet etching process. Thus, the lower electrode 310, the first support pattern 210, the second support pattern 220, the lower support pattern 230, and the upper support pattern 240 may be exposed.

[0058] Reference Figure 2 , a capacitor dielectric film 320 may be formed along the exposed lower electrode 310, the first supporting pattern 210, the second supporting pattern 220, the lower supporting pattern 230, and the upper supporting pattern 240. The capacitor dielectric film 320 may be formed on the upper and lower surfaces of the first supporting pattern 210, the upper and lower surfaces of the second supporting pattern 220, the side surface of the lower supporting pattern 230, the upper and side surfaces of the upper supporting pattern 240, and the upper surface of the etch stop film 105.

[0059] An upper electrode 330 may be formed on the capacitor dielectric film 320. An upper plate electrode 340 may be formed on the upper electrode 330. While forming the upper plate electrode 340, a portion of the upper electrode 330 may be patterned to correspond to the size of the upper plate electrode 340. The upper electrode 330 and the upper plate electrode 340 may fill the space between the etch stop film 105 and the first supporting pattern 210, the space between the first supporting pattern 210 and the second supporting pattern 220, the space between the second supporting pattern 220 and the lower supporting pattern 230, and the through hole PH.

[0060] Fig.11 is a schematic diagram for illustrating a semiconductor memory device according to some embodiments. For reference, Fig.11 It is along Figure 1 The line II in Figure 1For ease of description, the following description is mainly based on Fig.11 Use with above Figure 1 and Figure 2 The differences in the descriptions explained.

[0061] Reference Fig.11 In a semiconductor memory device according to some embodiments, a first thickness t1 of a portion of the lower electrode 310 defining a bottom surface of the groove 310t (e.g., a thickness of the bottom 311 in the third direction D3) may be different from a second thickness t2 of a portion of the lower electrode 310 defining a sidewall of the groove 310t (e.g., a width of the vertical portion 312 in the first direction D1), and the first thickness t1 may be greater than the second thickness t2.

[0062] In some embodiments, the width of the groove 310t in a direction parallel to the upper surface of the substrate 100 (e.g., the first direction D1 or the second direction D2) may not be constant along the third direction D3. For example, as the groove 310t extends toward the substrate 100 in the third direction D3, the width of the groove 310t in a direction parallel to the upper surface of the substrate 100 may increase and then decrease. The second thickness t2 of the portion of the lower electrode 310 defining the sidewall of the groove 310t (e.g., the width of the vertical portion 312 in the first direction D1) may decrease and then increase as the vertical portion 312 extends toward the substrate 100.

[0063] Fig.12 and Fig.13 is a schematic diagram of an intermediate structure corresponding to an intermediate step of an example method for manufacturing a semiconductor memory device according to some embodiments. For reference, Fig.12 and Fig.13 It is along Figure 1 II line intercepted Figure 1 A cross-sectional view of a semiconductor memory device shown in FIG. Fig.12 Involved Figure 4 For the convenience of description, the following description is mainly based on Fig.12 and Fig.13 Use with above Figures 1 to 11 The differences in the descriptions explained.

[0064] Reference Fig.12 , the width of the empty space IS defined in the lower electrode film 310p in a direction parallel to the upper surface of the substrate 100 (e.g., the first direction D1 or the second direction D2) may not be substantially constant along the third direction D3. For example, the width of the empty space IS defined in the lower electrode film 310p in a direction parallel to the upper surface of the substrate 100 (e.g., the first direction D1 or the second direction D2) may increase and then decrease as the empty space IS extends toward the substrate 100.

[0065] For example, the thickness of a portion of the lower electrode film 310 p defining the bottom surface of the empty space IS may be greater than the thickness of a portion of the lower electrode film 310 p defining the sidewall of the empty space IS.

[0066] Fig.12 The lower electrode film 310p in Figure 5 The shape of the empty space IS (eg, having a non-uniform width in a direction parallel to the upper surface of the substrate 100) may be due to Fig.12 The lower electrode film 310p is Figure 5 The fact that the lower electrode film 310p in the semiconductor memory device is thick.

[0067] Reference Fig.12 and Fig.13 , the top of the lower electrode film 310p may be removed to form the lower electrode 310. When the top of the lower electrode film 310p is removed, the empty space IS may be exposed to form the trench 310t.

[0068] Then, you can execute Figures 6 to 13 Therefore, it is possible to form Fig.11 The semiconductor memory device shown in .

[0069] Fig.14 is a schematic diagram for illustrating a semiconductor memory device according to some embodiments. For reference, Fig.14 It is along Figure 1 The line II in Figure 1 For ease of description, the following description is mainly based on Fig.14 Use with above Figure 1 and Figure 2 The differences in the descriptions explained.

[0070] Reference Fig.14 In the semiconductor memory device according to some embodiments, the lower surface 232ls of the second portion 232 may be coplanar with the upper surface 310us (in the third direction D3) of the lower electrode 310. The lower support pattern 230 may fill the groove 310t of the lower electrode 310 and may extend along the upper surface 310us of the lower electrode 310. Although not shown, the lower support pattern 230 may not extend along the outer wall of the lower electrode 310.

[0071] Fig.15 is a schematic diagram of an intermediate structure corresponding to an intermediate step of a method of manufacturing a semiconductor memory device according to some embodiments. For reference, Fig.15 It is along Figure 1 The II line is intercepted Figure 1 A cross-sectional view of a semiconductor memory device shown in FIG. Fig.15 Involved Figure 6 For the convenience of description, the following description is mainly based on Fig.15 Use with above Figures 1 to 10 and Fig.14 The differences in the descriptions explained.

[0072] Reference Fig.15 , can be done without Figure 7 The lower support film 230p is formed under the manufacturing process of the present invention. The upper surface 310us of the lower electrode 310 may be coplanar with the upper surface 225us of the third mold film 225. The lower support film 230p may cover the lower electrode 310 and the third mold film 225. The lower surface 230pls of the lower support film 230p may be coplanar with the upper surface 310us of the lower electrode 310. The lower surface 230pls of the lower support film 230p may be converted into the lower support pattern 230 ( Fig.14 The lower surface of 232ls ( Fig.14 middle).

[0073] Then, you can execute Figures 9 to 13 Therefore, it is possible to form Fig.14 The semiconductor memory device shown in .

[0074] Figures 16 to 18 is a schematic diagram of a semiconductor memory device according to some embodiments. For reference, Fig.16 is a schematic layout diagram (ie, a top view) for illustrating a semiconductor memory device according to some embodiments. Fig.17 It is along Fig.16 The line AA in Fig.16 A cross-sectional view of a semiconductor memory device shown in FIG. Fig.18 It is along Fig.16 The line BB in Fig.16 A cross-sectional view of a semiconductor memory device shown in FIG. For ease of description, the following description is mainly based on Figures 16 to 18 Use with above Figures 1 to 15 The differences in the descriptions explained.

[0075] In the drawings of the semiconductor memory device according to some embodiments, an example of the semiconductor memory device is implemented as a dynamic random access memory (DRAM). However, the present disclosure is not limited thereto.

[0076] Reference Figures 16 to 18 , a semiconductor memory device according to some embodiments may include a plurality of cell active regions ACT.

[0077] Each cell active region ACT may be defined by a cell device isolation film 108 formed in the substrate 100. As the design rule of semiconductor memory devices decreases, as Fig.16 As shown in , the unit active area ACT may extend in the form of a strip extending diagonally or obliquely. For example, the unit active area ACT may extend in a fourth direction D4. Hereinafter, the fourth direction D4 is a direction parallel to the upper surface of the substrate 100 and between the first direction D1 and the second direction D2 (i.e., intersecting the first direction D1 and the second direction D2).

[0078] A plurality of gate electrodes extending in the first direction D1 and across the cell active area ACT may be arranged. The plurality of gate electrodes may extend in parallel with each other. For example, the plurality of gate electrodes may be used as a plurality of word lines WL. The word lines WL may be spaced apart from each other at equal intervals in the second direction D2. The width of the word line WL or the interval between the word lines WL in the second direction D2 may be determined according to a design rule.

[0079] Each cell active region ACT may be divided into three parts by two word lines WL extending in the first direction D1. The cell active region ACT may include a storage connection region 106b and a bit line connection region 106a. The bit line connection region 106a may be located in the middle portion of the cell active region ACT, and the storage connection region 106b may be located at the end of the cell active region ACT.

[0080] For example, the bit line connection region 106a may be a region connected to the bit line BL, and the storage connection region 106b may be a region connected to the capacitor structure 300. In other words, the bit line connection region 106a may be used as a common drain region, and the storage connection region 106b may be used as a source region. Each word line WL and the bit line connection region 106a and the storage connection region 106b adjacent thereto may constitute a transistor.

[0081] A plurality of bit lines BL extending in a second direction D2 orthogonal to the extension direction of the word line WL may be provided on the word line WL. The plurality of bit lines BL may extend in parallel with each other. The bit lines BL may be spaced apart from each other in the first direction D1 at equal intervals. The width of the bit line BL in the first direction D1 or the interval between the bit lines BL may be determined according to a design rule.

[0082] A semiconductor memory device according to some embodiments may include various contact arrangements formed on a cell active area ACT, which may include, for example, a direct contact DC, a buried contact BC, and a landing pad (also called a connection pad, a landing pad, or a bonding pad) LP.

[0083] In this regard, the direct contact DC may refer to a contact that electrically connects the cell active area ACT to the bit line BL. The term "direct contact" as used herein is not intended to imply that there must be a direct physical connection and / or electrical connection between the bit line BL and the corresponding cell active area ACT; that is, an intermediate element may exist between the bit line BL and the cell active area ACT. The buried contact BC may refer to a contact that connects the cell active area ACT to the lower electrode 310 of the capacitor structure 300. Due to the arrangement structure, the contact area size between the buried contact BC and the cell active area ACT will be small. Therefore, a conductive landing pad LP may be introduced to increase the contact area size of the buried contact BC with the cell active area ACT and increase the contact area size of the buried contact BC with the lower electrode 310.

[0084] The landing pad LP may be between the cell active region ACT and the buried contact BC, and may be between the buried contact BC and the lower electrode 310. In the semiconductor memory device according to some embodiments, the landing pad LP may be between the buried contact BC and the lower electrode 310. Increasing the contact area size by introducing the landing pad LP may allow a reduction in contact resistance between the cell active region ACT and the lower electrode 310 of the capacitor structure 300.

[0085] The direct contact DC may be connected to the bit line connection region 106a. The buried contact BC may be connected to the storage connection region 106b. Since the buried contacts BC are respectively disposed at two opposite ends of the cell active region ACT, the landing pad LP may be adjacent to each of the two opposite ends of the cell active region ACT and partially overlap with the buried contact BC. In other words, the buried contact BC may be formed to overlap with a portion of each of the cell active region ACT and the cell device isolation film 108 disposed between the adjacent word lines WL and between the adjacent bit lines BL.

[0086] The word line WL may have a buried structure in the substrate 100. The word line WL may extend across a portion of the cell active area ACT between the direct contact DC or the buried contact BC. As shown in the figure, two word lines WL may extend across one cell active area ACT. Because the cell active area ACT extends in the fourth direction D4, the angle defined between the word line WL and the cell active area ACT may be less than 90 degrees.

[0087] The direct contacts DC may be arranged symmetrically. The buried contacts BC may be arranged symmetrically. Therefore, the direct contacts DC may be arranged in a straight line along each of the first direction D1 and the second direction D2. The buried contacts BC may be arranged in a straight line along each of the first direction D1 and the second direction D2. Unlike the direct contacts DC and the buried contacts BC, the landing pads LP may be arranged in a zigzag manner in the second direction D2 in which the bit lines BL extend. In addition, the landing pads LP may be arranged in the first direction D1 in which the word lines WL extend so as to overlap with the same side of the corresponding bit lines BL. For example, the landing pads LP arranged in the first row in the first direction may overlap with the left side portions of the corresponding bit lines BL, respectively. The landing pads LP arranged in the second row in the first direction may overlap with the right side portions of the corresponding bit lines BL.

[0088] A semiconductor memory device according to some embodiments may include a plurality of cell gate structures 110 , a plurality of bit line structures 140ST, a plurality of storage contacts 120 , a plurality of storage pads 160 , a plurality of bit line contacts 146 , and a capacitor structure 300 .

[0089] The cell device isolation film 108 may be formed in the substrate 100. The cell device isolation film 108 may have a shallow trench isolation (STI) structure having excellent device isolation capability. The cell device isolation film 108 may define a cell active region ACT in the memory cell region.

[0090] like Fig.16 As shown in , the cell active region ACT defined by the cell device isolation film 108 may have an elongated island shape including a short axis and a long axis. The cell active region ACT may have an inclined shape such that the cell active region ACT has an angle of less than 90 degrees with respect to the word line WL formed in the cell device isolation film 108. In addition, the cell active region ACT may have an inclined shape such that the cell active region ACT has an angle of less than 90 degrees with respect to the bit line BL formed on the cell device isolation film 108.

[0091] The cell device isolation film 108 may include, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. However, the present disclosure is not limited thereto. The cell device isolation film 108 is shown as being formed as an insulating film. However, this is only for ease of illustration. The present disclosure is not limited thereto. The cell device isolation film 108 may be formed as an insulating film or multiple insulating films according to the spacing between adjacent cell active regions ACT.

[0092] The upper surface of the cell device isolation film 108 and the upper surface of the substrate 100 are shown to be coplanar with each other in the third direction D3. However, this is only for the convenience of illustration. The present disclosure is not limited thereto.

[0093] The cell gate structure 110 may be formed in the substrate 100 and the cell device isolation film 108. The cell gate structure 110 may extend across the cell device isolation film 108 and the cell active region ACT defined by the cell device isolation film 108 in the first direction D1.

[0094] The cell gate structure 110 may be formed on the substrate 100 and the cell device isolation film 108. The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate capping pattern 113, and a cell gate capping conductive film 114.

[0095] In this regard, the cell gate electrode 112 may function as a word line WL. Unlike what is shown, the cell gate structure 110 may not include the cell gate capping conductive film 114; that is, the cell gate capping conductive film 114 may be optionally provided.

[0096] Although not shown, the cell gate trench 115 may have a relatively deep portion in the cell device isolation film 108 and a relatively shallow portion in the cell active region ACT. The bottom surface of the word line WL may be curved. That is, the depth of a portion of the cell gate trench 115 in the cell device isolation film 108 may be greater than the depth of a portion of the cell gate trench 115 in the cell active region ACT.

[0097] The cell gate insulating film 111 may extend along the sidewall and the bottom surface of the cell gate trench 115. The cell gate insulating film 111 may extend along the outline of at least a portion of the cell gate trench 115.

[0098] For example, the cell gate insulating film 111 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a dielectric constant higher than that of silicon oxide, but the embodiment is not limited thereto. The high dielectric constant material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof. The present disclosure is not limited thereto.

[0099] The cell gate electrode 112 may be disposed on the cell gate insulating film 111. The cell gate electrode 112 may fill a portion of the cell gate trench 115. The cell gate capping conductive film 114 may extend along an upper surface of the cell gate electrode 112.

[0100] The cell gate electrode 112 may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a conductive metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The cell gate electrode 112 may include, for example, at least one of TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrO, RuO, and combinations thereof. However, the present disclosure is not limited thereto.

[0101] The cell gate capping conductive film 114 may include, but is not limited to, one of polycrystalline silicon, polycrystalline silicon germanium, amorphous silicon, and amorphous silicon germanium.

[0102] The cell gate capping pattern 113 may be disposed on the cell gate electrode 112 and the cell gate capping conductive film 114. The cell gate capping pattern 113 may fill a portion of the cell gate trench 115 remaining after forming the cell gate electrode 112 and the cell gate capping conductive film 114. The cell gate insulating film 111 is shown to extend along the sidewall of the cell gate capping pattern 113. However, the present disclosure is not limited thereto.

[0103] For example, the cell gate capping pattern 113 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon carbon oxynitride, and combinations thereof, but the embodiment is not limited thereto.

[0104] An upper surface of the cell gate capping pattern 113 is shown to be coplanar with an upper surface of the cell device isolation film 108 in the third direction D3. However, the present disclosure is not limited thereto.

[0105] Although not shown, an impurity doped region may be formed on at least one side of the cell gate structure 110. The impurity doped region may be a source / drain region of a transistor. The impurity doped region may be formed in each of the storage connection region 106b and the bit line connection region 106a.

[0106] The bit line structure 140ST may include a cell conductive line 140 and a cell line capping film 144. The cell conductive line 140 may be disposed on the cell device isolation film 108 and the substrate 100 in which the cell gate structure 110 is formed. The cell conductive line 140 may cross the cell device isolation film 108 and the cell active area ACT defined by the cell device isolation film 108. The cell conductive line 140 may be formed to cross the cell gate structure 110. In this regard, the cell conductive line 140 may serve as a bit line BL.

[0107] The cell conductor 140 may include, for example, at least one of a semiconductor material doped with impurities, a conductive metal silicide, a conductive metal nitride, a conductive metal oxide, a two-dimensional (2D) material, a metal, and a metal alloy, but the embodiment is not limited thereto. In a semiconductor memory device according to some embodiments, the two-dimensional material may be a metal material and / or a semiconductor material. The two-dimensional material (2D material) may include a two-dimensional allotrope or a two-dimensional compound. For example, the 2D material may include graphene, molybdenum disulfide (MoS 2 ), molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) and tungsten disulfide (WS 2 ) at least one of. However, the present disclosure is not limited thereto. In other words, the above two-dimensional materials are listed only as examples. The two-dimensional materials that can be included in the semiconductor memory device of the present disclosure are not limited to the above materials.

[0108] The unit conductive line 140 is shown as being formed as a single film. However, this is only for ease of illustration, and the present disclosure is not limited thereto. That is, unlike what is shown, the unit conductive line 140 may include a stack of a plurality of conductive films made of a conductive material.

[0109] The cell line capping film 144 may be disposed on the cell conductive line 140. The cell line capping film 144 may extend in the second direction D2 along the upper surface of the cell conductive line 140. For example, the cell line capping film 144 may include at least one of a silicon nitride film, a silicon oxynitride film, a silicon carbonitride film, and a silicon carbon oxynitride film, but the embodiment is not limited thereto.

[0110] In the semiconductor memory device, the cell line capping film 144 may include a silicon nitride layer. The cell line capping film 144 is shown as being formed as a single film. However, this is only for ease of illustration, and the present disclosure is not limited thereto.

[0111] The bit line contact 146 may be formed between the cell conductive line 140 and the substrate 100. The cell conductive line 140 may be disposed on the bit line contact 146.

[0112] The bit line contact 146 may be between the cell conductive line 140 and the substrate 100. The cell conductive line 140 may be disposed on the bit line contact 146. The bit line contact 146 may be formed between the bit line connection region 106a of the cell active region ACT and the cell conductive line 140. The bit line contact 146 may be connected to the bit line connection region 106a.

[0113] The bit line contact 146 may electrically connect the cell conductive line 140 and the substrate 100 to each other. In this regard, the bit line contact 146 may function as a direct contact DC. For example, the bit line contact 146 may include at least one of a semiconductor material doped with impurities, a conductive metal silicide, a conductive metal nitride, a conductive metal oxide, a metal, and a metal alloy, but the embodiment is not limited thereto.

[0114] In a portion of the cell conductive line 140 where the bit line contact 146 is formed, the bit line spacer 150 may be formed on the substrate 100 and the cell device isolation film 108. The bit line contact 150 may be disposed on the sidewalls of the cell conductive line 140, the cell line capping film 144, and the bit line contact 146. In a portion of the cell conductive line 140 where the bit line contact 146 is not formed, the bit line spacer 150 may be disposed on the cell insulating film 135. The bit line spacer 150 may be disposed on the sidewalls of the cell conductive line 140 and the cell line capping film 144.

[0115] The cell insulating film 135 may be formed on the substrate 100 and the cell device isolation film 108. More specifically, the cell insulating film 135 may be disposed on a region of the substrate 100 where the bit line contact 146 is not formed and on the cell device isolation film 108. The cell insulating film 135 may be between the substrate 100 and the cell conductive line 140, and between the cell device isolation film 108 and the cell conductive line 140.

[0116] The unit insulating film 135 may be formed as a single film. Fig.17 and Fig.18 As shown in , the unit insulating film 135 can be formed into a multilayer film structure including a first unit insulating film 136 and a second unit insulating film 137 on the first unit insulating film 136. For example, the first unit insulating film 136 may include a silicon oxide film. The second unit insulating film 137 may include a silicon nitride layer. However, the present disclosure is not limited thereto. In other examples, unlike what is shown, the unit insulating film 135 may include three or more insulating films.

[0117] The storage contact 120 may be located between the cell conductive lines 140 adjacent to each other in the first direction D1. The storage contact 120 may overlap with the portion of the substrate 100 and the cell device isolation film 108 disposed between the adjacent cell conductive lines 140. The storage contact 120 may be connected to the storage connection region 106b of the cell active region ACT. In this regard, the storage contact 120 may function as a buried contact BC. In addition, the storage contact 120 may function as a Figures 1 to 15 The storage contact 103 in.

[0118] The storage contact 120 may include, for example, at least one of a semiconductor material doped with impurities, a conductive metal silicide, a conductive metal nitride, a conductive metal carbide, a conductive metal carbonitride, a conductive metal oxide, a metal, and a metal alloy.

[0119] The storage pad 160 may be disposed on the storage contact 120. The storage pad 160 may be electrically connected to the storage contact 120. In this regard, the storage pad 160 may function as a landing pad LP. In addition, the storage pad 160 may function as a Figures 1 to 15 The storage pad 104 is provided in the embodiment of the present invention.

[0120] The storage pad 160 may overlap a portion of the upper surface of the bit line structure 140ST in the third direction D3. For example, the storage pad 160 may include at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy, but the embodiment is not limited thereto.

[0121] The pad isolation insulating film 180 may be formed on the memory pad 160 and the bit line structure 140ST. For example, the pad isolation insulating film 180 may be on the cell line capping film 144. The pad isolation insulating film 180 may define the memory pad 160 into each of a plurality of isolated regions.

[0122] The pad isolation insulating film 180 does not cover the upper surface of the storage pad 160. The pad isolation insulating film 180 may fill the pad isolation recess. The pad isolation recess may electrically isolate adjacent storage pads 160 from each other. For example, the upper surface of the storage pad 160 may be coplanar with the upper surface of the pad isolation insulating film 180 in the third direction D3.

[0123] The pad isolation insulating film 180 includes an insulating material and can electrically insulate adjacent memory pads from each other among the plurality of memory pads 160. For example, the pad isolation insulating film 180 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon oxynitride silicon film, and a carbon nitride silicon film. However, the present disclosure is not limited thereto.

[0124] The etch stop film 105 may be disposed on the storage pad 160 and the pad isolation insulating film 180. The capacitor structure 300 may be disposed on the storage pad 160. The capacitor structure 300 may be electrically connected to the storage pad 160. The capacitor structure 300 may be Figure 2 , Fig.11 and Fig.17 The capacitor structure 300 is shown in FIG.

[0125] Fig.19 is a schematic layout diagram (ie, a top view) for illustrating a semiconductor memory device according to some embodiments. Fig. 20 is a schematic perspective view for illustrating a semiconductor memory device according to some embodiments. Fig.21 It is along Fig.19 The lines CC and DD in Fig.19 Schematic cross-sectional view of a semiconductor memory device shown in FIG.

[0126] Reference Figures 19 to 21 , a semiconductor memory device according to some embodiments includes a substrate 100, a plurality of first conductive lines 420, a channel layer 430, a gate electrode 440, a gate insulating film 450, and a capacitor structure 300. The semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer 430 extends from the substrate 100 along a vertical direction (ie, a third direction D3).

[0127] The lower insulating layer 412 may be disposed on the substrate 100 and between the substrate 100 and the plurality of first conductive lines 420. The plurality of first conductive lines 420 may be disposed on the lower insulating layer 412 and may be spaced apart from each other in the first direction D1 and extend longitudinally in the second direction D2. A plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 to fill the spaces between adjacent first conductive lines 420 in the plurality of first conductive lines 420. The plurality of first insulating patterns 422 may extend in the second direction D2. The upper surfaces of the plurality of first insulating patterns 422 may be located at the same vertical height as the upper surfaces of the plurality of first conductive lines 420; that is, the upper surfaces of the plurality of first insulating patterns 422 and the upper surfaces of the plurality of first conductive lines 420 may be coplanar in the third direction D3. Each of the plurality of first conductive lines 420 may be used as a bit line.

[0128] Each of the plurality of first conductive lines 420 may include at least one of a semiconductor material doped with impurities, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, and a combination thereof. For example, each of the plurality of first conductive lines 420 may include polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, etc. doped with impurities. x 、RuO x and combinations thereof, but not limited thereto. Each of the plurality of first conductive lines 420 may include a single layer or multiple layers made of the above materials. In some embodiments, each of the plurality of first conductive lines 420 may include graphene, carbon nanotubes, or combinations thereof.

[0129] The channel layer 430 may have a matrix shape in which the channels are spaced apart from each other in each of the first direction D1 and the second direction D2 and are respectively arranged on the plurality of first conductive lines 420. Each channel in the channel layer 430 may have a first width according to the first direction D1 and a first vertical dimension according to the third direction D3, and the first vertical dimension may be greater than the first width. In this regard, the third direction D3 may intersect the first direction D1 and the second direction D2, and may be, for example, a direction perpendicular to the upper surface of the substrate 100. For example, the first vertical dimension may be about 2 to about 10 times the first width. However, the present disclosure is not limited thereto. The bottom of each channel in the channel layer 430 may be used as a third source / drain region (not shown), and the top of each channel in the channel layer 430 may be used as a fourth source / drain region (not shown). A portion of each channel in the channel layer 430 between the third source / drain region and the fourth source / drain region may be used as a channel region (not shown).

[0130] In some embodiments, the channel layer 430 may include an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr xZn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga y O or a combination thereof, but the embodiment is not limited thereto. The channel layer 430 may include a single layer or multiple layers made of an oxide semiconductor. In some examples, the channel layer 430 may have a band gap energy greater than that of silicon. For example, the channel layer 430 may have a band gap energy of about 1.5 electron volts (eV) to about 5.6 eV. For example, when the channel layer 430 has a band gap energy of about 2.0 eV to 4.0 eV, the channel layer 430 may have optimal channel performance. For example, the channel layer 430 may be formed of polycrystalline or amorphous, but is not limited thereto. In some embodiments, the channel layer 430 may include graphene, carbon nanotubes, or a combination thereof.

[0131] The gate electrode 440 may extend in the first direction D1 and may be formed on both sidewalls of each channel in the channel layer 430. The gate electrode 440 may include a first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 and a second sub-gate electrode 440P2 facing the second sidewall of the channel layer 430 opposite to the first sidewall. Since one channel in the channel layer 430 is between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, the semiconductor memory device may have a dual-gate transistor structure. However, the technical spirit of the present disclosure is not limited thereto. The second sub-gate electrode 440P2 may be omitted, so only the first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 may be formed, so that the semiconductor memory device may implement a single-gate transistor structure. The description of the material of the gate electrode 440 may be the same as the description of the unit gate electrode 112.

[0132] The gate insulating film 450 surrounds the sidewall of each channel in the channel layer 430 (ie, extends around the sidewall of each channel in the channel layer 430), and may be interposed between each channel in the channel layer 430 and the gate electrode 440. For example, Fig.19, the entire sidewall of each channel in the channel layer 430 may be surrounded by the gate insulating film 450, and a portion of the sidewall of the gate electrode 440 may contact the gate insulating film 450. In other embodiments, the gate insulating film 450 may extend in the extension direction (i.e., the first direction D1) of the gate electrode 440, and only two sidewalls facing the gate electrode 440 among all the sidewalls of each channel in the channel layer 430 may contact the gate insulating film 450. In some embodiments, the gate insulating film 450 may be implemented as a silicon oxide film, a silicon oxynitride film, a film made of a high dielectric constant material having a dielectric constant higher than that of the silicon oxide film, or a combination thereof.

[0133] The plurality of second insulating patterns 432 may extend in the second direction D2 and may be respectively disposed on the plurality of first insulating patterns 422. Each channel in the channel layer 430 may be between two adjacent second insulating patterns 432 in the plurality of second insulating patterns 432. In addition, the first buried layer 434 and the second buried layer 436 may be between two adjacent second insulating patterns 432 and in the space between two adjacent channels in the channel layer 430. The first buried layer 434 may be in the bottom of the space between the two adjacent channels in the channel layer 430. The second buried layer 436 may at least partially fill the remaining portion of the space between the two adjacent channels in the channel layer 430 and may be disposed on the first buried layer 434. The upper surface of the second buried layer 436 may be coplanar with the upper surface of the channel layer 430 in the third direction D3, and the second buried layer 436 may cover the upper surface of the gate electrode 440. Alternatively, each of the plurality of second insulating patterns 432 and each of the plurality of first insulating patterns 422 may constitute a continuous material layer and thus may be integral. Alternatively, the second buried layer 436 and the first buried layer 434 may constitute a continuous material layer and thus may be integral.

[0134] Each capacitor contact 460 may be disposed on a respective channel in the channel layer 430. Each capacitor contact 460 may be vertically overlapped with each channel in the channel layer 430. Therefore, the capacitor contacts 460 may be arranged in a matrix form in which the capacitor contacts 460 are spaced apart from each other in each of the first direction D1 and the second direction D2. The capacitor contacts 460 may include polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO doped with impurities. x 、RuO xThe upper insulating layer 462 may surround (ie, extend around) a sidewall of each capacitor contact 460 , and may be disposed on the plurality of second insulating patterns 432 and the second buried layer 436 .

[0135] The etch stop film 105 may be disposed on the upper insulating layer 462. The capacitor structure 300 may be disposed on the etch stop film 105. Each of the etch stop film 105 and the capacitor structure 300 may be respectively Figure 2 , Fig.11 and Fig.17 The etch stop film 105 and the capacitor structure 300 are shown in FIG.

[0136] In the illustrative embodiment, the lower electrode 310 may be vertically overlapped with the capacitor contact 460. The lower electrodes 310 may be arranged in a matrix shape in which the lower electrodes 310 are spaced apart from each other in each of the first direction D1 and the second direction D2. Optionally, a landing pad (not shown) may be further provided between the capacitor contact 460 and the lower electrode 310 so that the lower electrodes 310 may be arranged in a hexagonal shape.

[0137] Fig. 22 is a schematic layout diagram (ie, a top view) for illustrating a semiconductor memory device according to some embodiments. Fig.23 is a schematic perspective view of a semiconductor memory device for illustrating some embodiments.

[0138] Reference Fig. 22 and Fig.23 , a semiconductor memory device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420A, a channel structure 430A, a contact gate electrode 440A, a plurality of second conductive lines 442A, and a capacitor structure 300. The semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor (VCT).

[0139] A plurality of active regions AC may be defined in the substrate 100 by a first device isolation pattern 412A and a second device isolation pattern 414A. A channel structure 430A may be disposed in each active region AC. The channel structure 430A may include a first active pillar 430A1 and a second active pillar 430A2 extending in a vertical direction (i.e., a third direction D3) and a connection portion 430L connected to the bottom of the first active pillar 430A1 and the bottom of the second active pillar 430A2. A first source / drain region SD1 may be disposed in the connection portion 430L. A second source / drain region SD2 may be disposed in the top of each of the first active pillar 430A1 and the second active pillar 430A2. Each of the first active pillar 430A1 and the second active pillar 430A2 may form an independent unit memory cell.

[0140] A plurality of first wires 420A may extend in a direction intersecting with a plurality of active regions AC. For example, a plurality of first wires 420A may extend in a second direction D2. One of the plurality of first wires 420A may be disposed on the connection portion 430L and between the first active pillar 430A1 and the second active pillar 430A2. A first wire 420A may be disposed on the first source / drain region SD1. Another first wire 420A adjacent to the first wire 420A may be disposed between two channel structures 430A. A first wire 420A of the plurality of first wires 420A may be used as a common bit line commonly included in two unit memory cells corresponding to the first active pillar 430A1 and the second active pillar 430A2, respectively, and the first active pillar 430A1 and the second active pillar 430A2 are disposed on both sides of the first wire 420A.

[0141] One contact gate electrode 440A may be located between two channel structures 430A adjacent to each other in the second direction D2. For example, the contact gate electrode 440A may be between a first active pillar 430A1 included in a channel structure 430A and a second active pillar 430A2 of a channel structure 430A adjacent to the first active pillar 430A1. One contact gate electrode 440A may be shared by a first active pillar 430A1 and a second active pillar 430A2 disposed on two (opposite) sidewalls thereof. A gate insulating film 450A may be between the contact gate electrode 440A and the first active pillar 430A1 and between the contact gate electrode 440A and the second active pillar 430A2. A plurality of second conductive wires 442A may extend in the first direction D1. Each of the plurality of second conductive wires 442A may be on the upper surface of the respective contact gate electrode 440A. Each of the plurality of second conductive wires 442A may be used as a word line of a semiconductor memory device.

[0142] The capacitor contact 460A may be disposed on the channel structure 430A. The capacitor contact 460A may be on the second source / drain region SD2. The capacitor structure 300 may be on the capacitor contact 460A. The capacitor structure 300 may be implemented as Figure 2 , Fig.11 and Fig.17 The capacitor structure 300 is shown in FIG.

[0143] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments, but can be implemented in various different forms. It will be appreciated by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive in all aspects, but illustrative.

Claims

1. A semiconductor memory device, comprising: a storage pad, on a base; a lower electrode on the storage pad and including a groove defined by a bottom and sidewalls of the lower electrode; a lower support pattern including a first portion in the groove and a second portion on an upper surface of the lower electrode and contacting the first portion; an upper supporting pattern on an upper surface of the lower supporting pattern; a capacitor dielectric film on the lower electrode, the lower supporting pattern and the upper supporting pattern; as well as Upper electrode, on the capacitor dielectric film.

2. The semiconductor memory device according to claim 1, wherein The lower supporting pattern and the upper supporting pattern include the same material.

3. The semiconductor memory device according to claim 1, wherein: The lower supporting pattern and the upper supporting pattern include different materials.

4. The semiconductor memory device according to claim 1, wherein: An upper surface of the second portion of the lower supporting pattern includes a protruding portion facing away from the substrate.

5. The semiconductor memory device according to claim 1, wherein: A first thickness of a portion of the lower electrode defining the bottom surface of the groove in a third direction perpendicular to the upper surface of the substrate is different from a second thickness of a portion of the lower electrode defining the sidewall of the groove in a first direction parallel to the upper surface of the substrate.

6. The semiconductor memory device according to claim 1, wherein: With respect to the upper surface of the substrate, a lowermost surface of the second portion of the lower supporting pattern is lower than an upper surface of the lower electrode in a third direction perpendicular to the upper surface of the substrate.

7. The semiconductor memory device according to claim 1, wherein: The lowermost surface of the second portion of the lower supporting pattern is coplanar with the upper surface of the lower electrode in a third direction perpendicular to the upper surface of the substrate.

8. The semiconductor memory device according to claim 1, wherein: The lower supporting pattern and the lower electrode include different materials.

9. The semiconductor memory device according to claim 1, wherein: As the groove extends toward the substrate in a third direction perpendicular to the upper surface of the substrate, the width of the groove in a first direction parallel to the upper surface of the substrate increases and then decreases.

10. A semiconductor memory device comprising: a storage pad, on a base; a lower electrode on the storage pad and including a groove defined by a bottom and sidewalls of the lower electrode; a lower support pattern extending in the groove and along the upper surface of the lower electrode and along an outer wall of the top of the lower electrode in a first direction parallel to the upper surface of the substrate; a capacitor dielectric film on the lower electrode and the lower support pattern; as well as Upper electrode, on the capacitor dielectric film.

11. The semiconductor memory device according to claim 10, wherein: The lower supporting pattern includes silicon carbonitride.

12. The semiconductor memory device according to claim 10, wherein: An upper surface of the lower supporting pattern includes a protruding portion that is away from the substrate in a third direction perpendicular to the upper surface of the substrate.

13. The semiconductor memory device according to claim 10, wherein: As the trench extends toward the substrate in a third direction perpendicular to the upper surface of the substrate, the width of the trench in the first direction decreases or is constant.

14. The semiconductor memory device according to claim 10, wherein: As the trench extends toward the substrate in a third direction perpendicular to the upper surface of the substrate, the width of the trench in the first direction increases and then decreases.

15. The semiconductor memory device according to claim 10, further comprising: The upper supporting pattern extends in a first direction on an upper surface of the lower supporting pattern.

16. The semiconductor memory device according to claim 10, further comprising: bit line structure, on the substrate; and a cell gate structure in the substrate and intersecting the bit line structure, The storage pad is on the side surface of the bit line structure and is electrically connected to the substrate.

17. The semiconductor memory device according to claim 10, further comprising: Support pattern, on the side wall of the lower electrode.

18. A method for manufacturing a semiconductor memory device, the method comprising: sequentially forming an etch stop film and a mold film on a substrate; forming a lower electrode hole extending through the etch stop film and the mold film in a third direction perpendicular to the upper surface of the substrate; forming a lower electrode extending along the sidewall in a third direction and on the bottom of the lower electrode hole and including a groove defined by the bottom and the sidewall of the lower electrode; forming a lower supporting pattern that at least partially fills the groove and extends along an upper surface of the mold film in a first direction parallel to an upper surface of the substrate; forming an upper supporting pattern on the lower supporting pattern; removing the mold film to expose a portion of the lower electrode, a portion of the lower supporting pattern, and a portion of the upper supporting pattern; forming a capacitor dielectric film on the exposed portion of the lower electrode, the exposed portion of the lower supporting pattern, and the exposed portion of the upper supporting pattern; as well as An upper electrode is formed on the capacitor dielectric film.

19. The method according to claim 18, further comprising: After forming the lower electrode, a portion of the mold film is etched to expose the top of the lower electrode, Wherein, forming the lower supporting pattern includes forming the lower supporting pattern on the exposed top of the lower electrode.

20. The method according to claim 18, wherein: The lower supporting pattern and the upper supporting pattern include the same material.

Images