Optical co-packaging structure, preparation method thereof and optical equipment

Abstract

The invention discloses an optical co-packaging structure, a preparation method thereof and optical equipment, and is suitable for the technical field of semiconductors, and the optical co-packaging structure comprises a packaging substrate, an adapter plate, an optical chip and a first chip. The adapter plate is arranged on the packaging substrate and electrically connected with the packaging substrate, the adapter plate comprises an electric chip, and the electric chip is embedded in the adapter plate. The optical chip is arranged on the side, away from the packaging substrate, of the adapter plate, and the optical chip and the electric chip are arranged in a stacked mode and electrically connected. The first chip is arranged on the side, away from the packaging substrate, of the adapter plate and is electrically connected with the optical chip and the electric chip. According to the technical scheme of the invention, the overall performance of the optical co-packaging structure is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to an optical co-packaging structure and a preparation method thereof, and an optical device. Background Art

[0002] With the development of semiconductor technology, co-packaged optics (CPO) technology has become a new research hotspot. However, in the 3D optical co-package structure, there are problems such as a large height difference between the computing chip or switching chip and the optical engine, and a certain delay in signal transmission. These problems have an adverse effect on the overall performance of the optical co-package structure. Summary of the invention

[0003] The present application provides an optical co-packaging structure and a preparation method thereof, and an optical device, aiming to improve the overall performance of the optical co-packaging structure.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, an optical co-packaging structure is provided, which includes a packaging substrate, an adapter board, an optical chip and a first chip. The adapter board is arranged on the packaging substrate and is electrically connected to the packaging substrate. The adapter board includes an electrical chip, and the electrical chip is embedded in the adapter board. The optical chip is arranged on a side of the adapter board away from the packaging substrate, and the optical chip and the electrical chip are stacked and electrically connected to the electrical chip. The first chip is arranged on a side of the adapter board away from the packaging substrate, and is electrically connected to the optical chip and the electrical chip.

[0006] The optical co-packaging structure provided in the embodiment of the present application includes a packaging substrate, an adapter board electrically connected to the packaging substrate, an optical chip and a first chip arranged on a side of the adapter board away from the packaging substrate, wherein the adapter board is embedded with an electric chip, the electric chip and the optical chip are stacked and electrically connected to form an optical engine, and the first chip is electrically connected to the optical chip, thereby realizing electrical communication between the first chip, the optical chip and the electric chip. In the optical co-packaging structure, the structure in which the electric chip is embedded in the adapter board and stacked with the optical chip reduces the area occupied by the optical engine on the packaging substrate, thereby reducing the area of ​​the optical co-packaging structure, improving the integration of the optical co-packaging structure, and reducing the connection distance between the optical chip and the electric chip, thereby reducing signal delay and improving signal integrity, thereby improving the overall performance of the optical co-packaging structure.

[0007] In some embodiments, the optical co-packaging structure further includes a rewiring layer, which is disposed on a side of the adapter plate away from the packaging substrate. The optical chip is disposed on a side of the rewiring layer away from the packaging substrate, and the optical chip is electrically connected to the electrical chip through the rewiring layer. The first chip is disposed on a side of the rewiring layer away from the packaging substrate, and the first chip is electrically connected to the optical chip and the electrical chip through the rewiring layer.

[0008] In some embodiments, the adapter plate further includes a connection structure, and the connection structure is embedded in the adapter plate. The optical co-packaging structure further includes a rewiring layer, and the rewiring layer is arranged on a side of the adapter plate away from the packaging substrate. The rewiring layer includes a first conductive structure and a second conductive structure, and the first conductive structure is electrically connected to the connection structure, and the second conductive structure is electrically connected to the connection structure and the electrical chip. The first chip is arranged on a side of the rewiring layer away from the packaging substrate and is electrically connected to the first conductive structure, and the optical chip is arranged on a side of the rewiring layer away from the packaging substrate and is electrically connected to the second conductive structure.

[0009] In some embodiments, the optical chip is provided with an optical interface on a side away from the first chip. The optical co-packaging structure further includes a heat dissipation cover, which is provided on the packaging substrate and at least covers the adapter board, the first chip and the optical chip, and exposes the optical interface.

[0010] On the other hand, the present application also provides a method for preparing an optical co-packaging structure, the preparation method comprising: electrically connecting an adapter plate to a packaging substrate, the adapter plate comprising an electrical chip, and the electrical chip being embedded in the adapter plate. Electrically connecting a first chip and an optical chip to the adapter plate, the first chip being located on a side of the adapter plate away from the packaging substrate and being electrically connected to the electrical chip, the optical chip being located on a side of the adapter plate away from the packaging substrate, the optical chip being stacked with the electrical chip, and being electrically connected to the electrical chip.

[0011] The method for preparing the optical co-packaging structure provided in the embodiment of the present application electrically connects the adapter structure with the embedded electric chip to the packaging substrate, and then arranges the first chip and the optical chip on the side of the adapter away from the packaging substrate, and both are electrically connected to the electric chip, thereby realizing the electrical connection between the first chip, the optical chip and the electric chip. The optical chip and the electric chip are stacked to form a vertically interconnected optical engine. Since the electric chip is embedded in the adapter, the area occupied by the optical engine on the packaging substrate is reduced, thereby reducing the area of ​​the optical co-packaging structure and improving the integration of the optical co-packaging structure. In addition, the connection distance between the optical chip and the electric chip is reduced, thereby reducing signal delay and improving signal integrity, thereby improving the overall performance of the optical co-packaging structure.

[0012] In some embodiments, before electrically connecting the adapter board to the packaging substrate, an adapter board is formed, including forming a plurality of third conductive structures on a carrier, wherein the surface of the carrier includes a first area and a second area, the plurality of third conductive structures are located in the first area, the electrical chip is disposed in the second area, and a filling layer is formed on the surface of the carrier, the filling layer is located between the plurality of third conductive structures, and between the third conductive structures and the electrical chip.

[0013] In some embodiments, after forming the adapter board, the preparation method further includes forming a rewiring layer on the adapter board, the rewiring layer being electrically connected to the plurality of third conductive structures and the electrical chip. Electrically connecting the first chip and the optical chip to the adapter board includes electrically connecting the first chip and the optical chip to the rewiring layer, the first chip being located on a side of the rewiring layer away from the packaging substrate, the first chip being electrically connected to the optical chip and the electrical chip through the rewiring layer. The optical chip is located on a side of the rewiring layer away from the packaging substrate, the optical chip being electrically connected to the electrical chip through the rewiring layer.

[0014] In some embodiments, the surface of the carrier also includes a third area, and before forming the filling layer, the above preparation method also includes forming a connection structure in the third area. After forming the adapter board, the above preparation method also includes forming a rewiring layer on the adapter board, the rewiring layer includes a first conductive structure and a second conductive structure, the first conductive structure is electrically connected to the connection structure, and the second conductive structure is electrically connected to the connection structure and the electrical chip. Electrically connecting the first chip and the optical chip to the adapter board includes electrically connecting the first chip and the optical chip to the rewiring layer, the first chip is located on a side of the rewiring layer away from the packaging substrate and is electrically connected to the first conductive structure, and the optical chip is located on a side of the rewiring layer away from the packaging substrate and is electrically connected to the second conductive structure.

[0015] In some embodiments, the optical chip is provided with an optical interface. After the first chip and the optical chip are electrically connected to the adapter board, the above-mentioned preparation method also includes setting a heat dissipation cover on the packaging substrate, and the heat dissipation cover at least covers the adapter board, the first chip and the optical chip, and exposes the optical interface.

[0016] On the other hand, the present application also provides an optical device, which includes the optical co-packaging structure mentioned above, and a circuit board, wherein the optical co-packaging structure is arranged on the circuit board and is electrically connected to the circuit board. In the optical device provided by the embodiment of the present application, the overall performance of the optical co-packaging structure is improved, so that the reliability of the optical co-packaging structure is improved, thereby also improving the reliability of the optical device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 A schematic diagram of an optical co-packaging structure provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of another optical co-packaging structure provided in an embodiment of the present application;

[0020] Figure 3 A preparation flow chart of an optical co-packaging structure provided in an embodiment of the present application;

[0021] Figures 4 to 13 for Figure 3 A diagram of each step of the preparation process;

[0022] Figure 14 to Figure 17 A diagram showing the steps for preparing another optical co-packaging structure provided in an embodiment of the present application;

[0023] Fig.18 A schematic diagram of an optical device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0025] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0026] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0027] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0028] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0029] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0030] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0031] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0032] With the explosive growth of data traffic, the demand for data communication solutions with higher speed, lower power consumption and lower latency is increasing day by day. Due to the limitations of Moore's Law, traditional pluggable optical modules face limitations in bandwidth, latency, energy efficiency and speed. Silicon-based optoelectronic technology uses semiconductor manufacturing technology to interconnect optoelectronic components on silicon chips, opening up new possibilities for high-density multi-channel solution design. Therefore, optical co-packaging technology came into being.

[0033] Optical co-packaging technology greatly reduces the volume and weight of the optical co-packaging structure by highly integrating silicon photonic chips, that is, electrical chips including electronic integrated circuits (EIC) and optical chips including photonic integrated circuits (PIC), with computing / switch (XPU / Switch) chips in the form of advanced packaging (2.5D / 3D process). It also shortens the connection distance between chips, reduces signal delays, and improves signal transmission speed and bandwidth, achieving low latency, low power consumption and high performance.

[0034] However, there are some problems in the CPO structure in the related technology that need to be solved urgently. For the 2.5D optoelectronic co-packaging structure, the electrical chip and the optical chip are integrated side by side on the interposer, and the packaging structure has a large area. The interposer connects the application-specific integrated circuit (ASIC) chip / switch, the electrical chip and the optical chip through micro-bumps to achieve chip interconnection. The interposer can also connect the optical fiber assembly with the PIC optical fiber block, which requires very high alignment accuracy (1μm) to achieve good optical coupling efficiency.

[0035] For the 3D optoelectronic co-packaging structure, the electrical chip and the optical chip are stacked vertically and interconnected through silicon vias (TSV) or through molding vias (TMV) to form an optical engine. The area of ​​the packaging structure can be further reduced, the distance between the optical engine and the ASIC chip is further reduced, and the signal delay and loss will be further reduced. However, due to the high heat generation of the electrical chip, the 3D stacking of the electrical chip and the optical chip will aggravate the heat dissipation problem and may cause the optoelectronic performance to decrease, especially the temperature drift has a great impact on the optical characteristics. In addition, the height difference between the optical engine and the first chip is large, which is not conducive to the installation of heat dissipation and heat dissipation cover, which may lead to reduced reliability of the packaging structure.

[0036] In order to solve the above problems, an embodiment of the present application provides an optical co-packaging structure 1. Figure 1 A schematic diagram of an optical co-packaging structure provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the optical co-packaging structure 1 includes a packaging substrate 10, an adapter board 11, an optical chip 12 and a first chip 13. Among them, the adapter board 11 is arranged on the packaging substrate 10 and is electrically connected to the packaging substrate 10. Exemplarily, the adapter board 11 is electrically connected to the packaging substrate 10 through a solder ball 20, or a micro-bump is arranged on a side of the adapter board 11 close to the packaging substrate, so that the adapter board 11 is electrically connected to the packaging substrate 10 through the micro-bump. The adapter board 11 includes an electric chip 14, and the electric chip 14 is embedded in the adapter board 11. The embodiment provided in the present application is described by taking two electric chips 14 embedded in the adapter board 11 side by side as an example.

[0037] The optical chip 12 is arranged on a side of the adapter board 11 away from the packaging substrate 10, and the optical chip 12 is stacked with the electric chip 14, and the optical chip 12 is electrically connected to the electric chip 14, that is, along the direction Z, the optical chip 12 is arranged above the electric chip 14, and the optical chip 12 and the electric chip 14 are vertically stacked and electrically connected to form a "light engine". The first chip 13 is arranged on a side of the adapter board 11 away from the packaging substrate 10, and is electrically connected to the optical chip 12 and the electric chip 14 through the adapter board 10. Exemplarily, the first chip 11 can be a computing chip or a switching chip. When the first chip 11 is a computing chip, the optical co-packaging structure 1 is an optical computing packaging structure; when the first chip 11 is a switching chip, the optical co-packaging structure 1 is an optical switching packaging structure. Along the direction X, the first chip 13 and the optical chip 12 are arranged side by side to obtain a 3D packaged optical co-packaging structure 1.

[0038] The optical co-packaging structure 1 provided in the embodiment of the present application includes a packaging substrate 10, an adapter plate 11 electrically connected to the packaging substrate 10, an optical chip 12 and a first chip 13 arranged on a side of the adapter plate 11 away from the packaging substrate 10, wherein the adapter plate 11 is embedded with an electric chip 14, the electric chip 14 is stacked and electrically connected with the optical chip 12 to form an optical engine, and the first chip 13 is electrically connected with the optical chip 12, thereby realizing electrical communication among the first chip 13, the optical chip 12 and the electric chip 14. In the optical co-packaging structure 1, the structure in which the electric chip 14 is embedded in the adapter plate 11 and stacked with the optical chip 12 reduces the area occupied by the optical engine on the packaging substrate 10, thereby reducing the area of ​​the optical co-packaging structure 1 and improving the integration of the optical co-packaging structure 1, and reducing the connection distance between the optical chip 13 and the electric chip 14, thereby reducing signal delay and improving signal integrity, thereby improving the overall performance of the optical co-packaging structure 1.

[0039] In some embodiments, Figure 1 As shown, the optical co-packaging structure 1 also includes a rewiring layer 15, and the rewiring layer 15 is arranged on the side of the adapter board 11 away from the packaging substrate 10. The rewiring layer 15 can be a single-layer conductive structure or a multi-layer conductive structure, and a micro-pad is arranged on the side of the rewiring layer 15 away from the adapter board 11. The optical chip 12 is arranged on the side of the rewiring layer 15 away from the packaging substrate 10, and the optical chip 12 is electrically connected to the electrical chip 14 through the rewiring layer 15. The first chip 13 is arranged on the side of the rewiring layer 15 away from the packaging substrate 10, and the first chip 13 is electrically connected to the optical chip 12 and the electrical chip 14 through the rewiring layer 15. Exemplarily, micro-bumps are arranged on the surface of the side of the optical chip 12 and the first chip 13 close to the packaging substrate 10, and the micro-bumps of the optical chip 12 and the first chip 13 are electrically connected to the micro-pads of the rewiring layer 15 by thermocompression bonding.

[0040] Compared with the related art, in which the electrical chip and the optical chip are vertically interconnected through TSV or TMV to form an optical engine, the structure in which the optical chip 12 and the electrical chip 14 are connected through the redistribution layer 15 in the embodiment of the present application reduces the projection area of ​​the optical co-packaging structure 1 on the plane XY, makes the distance between the optical engine and the first chip 13 smaller, and does not require TSV process, thereby reducing the process difficulty of preparing the optical co-packaging structure 1, improving its process reliability, and thereby improving the reliability of the optical co-packaging structure 1.

[0041] In some embodiments, Figure 2 A schematic diagram of another optical co-packaging structure provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the adapter board 11 also includes a connection structure 16, which is embedded in the adapter board 11, and along the direction X, the connection structure 16 is located on the inner side of the electric chip 14. Exemplarily, the connection structure 16 can be a silicon bridge, and the embedding of the silicon bridge improves the wiring density of the adapter board 11, increases the propagation path of the electrical signal, thereby reducing signal delay and improving the overall performance of the optical co-packaging structure 1. The optical co-packaging structure 1 also includes a rewiring layer 15, which is arranged on the side of the adapter board 11 away from the packaging substrate 10. The rewiring layer 15 can be a single-layer conductive structure or a multi-layer conductive structure, and a micro pad is arranged on the side of the rewiring layer 15 away from the adapter board 11.

[0042] The rewiring layer 15 includes a first conductive structure 151 and a second conductive structure 152, wherein the first conductive structure 151 is electrically connected to the connection structure 16, and the second conductive structure 152 is electrically connected to the connection structure 16 and the electric chip 14. The first chip 13 is disposed on a side of the rewiring layer 15 away from the package substrate 10, and is electrically connected to the first conductive structure 151, and the optical chip 12 is disposed on a side of the rewiring layer 15 away from the package substrate 10, and is electrically connected to the second conductive structure 152. It can be understood that the first chip 13 can not only realize electrical connection with the optical chip 12 and the electric chip 14 through the rewiring layer 15, but also the first chip 13 can be electrically connected with the optical chip 12 and the electric chip 14 through the first conductive structure 151, the connection structure 16, and the second conductive structure 152 in sequence.

[0043] In some embodiments, Figure 1 and Figure 2As shown, the optical chip 12 is provided with an optical interface 17 on the side away from the first chip 13. The optical interface 17 is an optical interface or coupling area on the optical chip 12, which is used to connect with the fiber array unit (FAU) to realize the input and output of optical signals. In the embodiment provided by the present application, along the direction X, the optical interface 17 of the optical chip 12 is arranged on the outer side, realizing edge coupling, improving the coupling efficiency, and ensuring the optoelectronic performance of the optical chip 13. In addition, the outer edge of the optical interface 17 of the optical chip 12 exceeds the outer edge of the optical co-packaging structure 1, which is conducive to the connection between the optical interface 17 and the FAU.

[0044] The optical co-packaging structure 1 further includes a heat dissipation cover 18, which is disposed on the packaging substrate 10. The heat dissipation cover 18 at least covers the adapter board 11, the first chip 13 and the optical chip 12, and exposes the optical interface 17. Since the structure in which the electric chip 14 is embedded in the adapter board 11 reduces the overall height of the stacked electric chip 14 and the optical chip 12 (optical engine), and along the direction X, the first chip 13 and the optical chip 12 are arranged side by side, so that the height difference between the first chip 13 and the optical engine is reduced, which is conducive to the installation of the heat dissipation cover 18, thereby achieving the purpose of reducing the packaging height of the optical co-packaging structure 1. In addition, the structure in which the electric chip 14 is embedded in the adapter board 11 provides a new path for the heat dissipation of the electric chip 14, which is conducive to improving the heat dissipation efficiency of the optical engine.

[0045] In the embodiment provided by the present application, the heat dissipation cover 18 and the packaging substrate 10 surround the first chip 13, the optical chip 12 and the electrical chip 14, and only expose the surface on the side where the optical interface 17 is located, thereby isolating and protecting the first chip 13 and the optical engine, and the heat dissipation cover 18 has a certain heat dissipation effect, which is conducive to improving the heat conduction speed. Exemplarily, a thermal interface material (TIM) is also provided between the heat dissipation cover 18 and the first chip 13 and the optical engine, and the thermal interface material can not only bond the heat dissipation cover 18 and the first chip 13 and the optical chip 12, but also reduce the contact thermal resistance between the heat dissipation cover 18 and the first chip 13 and the optical chip 12, and has a good heat transfer effect.

[0046] On the other hand, an embodiment of the present application provides a method for preparing an optical co-packaging structure. Figure 3 A preparation flow chart of an optical co-packaging structure provided in an embodiment of the present application; Figures 4 to 13 for Figure 3 The steps of the preparation process are shown in Figure 2. Figure 3 As shown, the preparation method includes the following steps S1 to S8:

[0047] Step S1: Figure 4As shown, micro-bumps are made on any surface of the optical wafer and the electrical wafer by a bumping process, and then the optical wafer and the electrical wafer are cut to form an optical chip 12 and a first chip 13, the surface of the first chip 13 forms a first micro-bump 130, and the surface of the optical chip 12 forms a second micro-bump 120, or a ready-made optical chip 12 and a first chip 13 with micro-bumps are used. Among them, there is an optical interface 17 exposed by cutting the optical wafer on one side of the optical chip 12, and the optical interface 17 is an optical interface or coupling area on the optical chip 12, which is used to connect with the FAU to realize the input and output of optical signals. The first chip 11 can be a computing chip or a switching chip. When the first chip 11 is a computing chip, the optical co-packaging structure 1 is an optical computing packaging structure; when the first chip 11 is a switching chip, the optical co-packaging structure 1 is an optical switching packaging structure.

[0048] Step S2: Figure 5 As shown, a carrier 19 is provided. For example, the carrier 19 can be a wafer or a temporary glass carrier. The embodiment provided in this application is described by taking the carrier 19 as a temporary glass carrier as an example. Figure 6 As shown, a temporary bonding glue is applied on the surface of the carrier 19 to form a plurality of third conductive structures 153 on the carrier 19. The plurality of third conductive structures 153 are copper column bumps. The surface 190 of the carrier 19 includes a first area 191 and a second area 192. The plurality of third conductive structures 153 are located in the first area 191, and the second area 192 is left vacant as a placement position for the electrical chip 14.

[0049] Step S3: Figure 7 As shown, the electric chip 14 is disposed in the second area 192 so that the electric chip 14 is embedded in the adapter board 11 . The embodiment provided in the present application is described by taking two electric chips 14 embedded side by side in the adapter board 11 as an example.

[0050] Step S4: Figure 8 As shown, a first filling layer 110 is formed on the surface 190 of the carrier 19 to form the transfer board 11. The first filling layer 110 is located between the plurality of third conductive structures 153 and between the third conductive structures 153 and the electrical chip 14.

[0051] Step S5: Fig. 9 As shown, a rewiring layer 15 is formed on the adapter board 11, and the rewiring layer 15 is electrically connected to multiple third conductive structures 153 and the electrical chip 14. Exemplarily, micro pads are also provided on the rewiring layer 15 for electrically connecting to the first micro bumps 130 and the second micro bumps 120.

[0052] Step S6: After forming the redistribution layer 15, the above-mentioned preparation method further comprises: Fig.10As shown, the carrier 19 is debonded from the transfer board 11, and a solder ball 20 is prepared on the surface of the transfer board 11 away from the redistribution layer 15, and then Fig.11 As shown, the adapter board 11 is electrically connected to the packaging substrate 10. The adapter board 11 and the packaging substrate 10 can be electrically connected through solder balls 20, or micro-bumps are set on a side of the adapter board 11 close to the packaging substrate so that the adapter board 11 is electrically connected to the packaging substrate 10 through the micro-bumps.

[0053] For example, see Fig.11 After the adapter plate 11 is electrically connected to the package substrate 10 through the solder balls 20 , a second filling layer 111 is formed between the adapter plate 11 and the package substrate 10 to increase the firmness and durability of the connection between the adapter plate 11 and the package substrate 10 .

[0054] Step S7: Fig.12 As shown, the first chip 13 and the optical chip 12 are electrically connected to the adapter board 11, that is, the first micro-bumps 130 of the first chip 13 and the second micro-bumps 120 of the optical chip 12 are electrically connected to the micro-bumps on the rewiring layer 15 through thermal compression bonding. The first chip 13 is located on the side of the adapter board 11 away from the packaging substrate 10, and the first chip 13 is electrically connected to the electrical chip 14 through the rewiring layer 15. The optical chip 12 is located on the side of the adapter board 11 away from the packaging substrate 10. The optical chip 12 and the electrical chip 14 are stacked to form a vertically stacked light engine, and the optical chip 12 and the electrical chip 14 are electrically connected through the rewiring layer 15.

[0055] Compared with the related art, in which the electrical chip and the optical chip are vertically interconnected through TSV or TMV to form an optical engine, the structure in which the optical chip 12 and the electrical chip 14 are connected through the redistribution layer 15 in the embodiment of the present application reduces the projection area of ​​the optical co-packaging structure 1 on the plane where the packaging substrate 10 is located, makes the distance between the optical engine and the first chip 13 smaller, and does not require TSV process, thereby reducing the process difficulty of preparing the optical co-packaging structure 1, improving its process reliability, and thereby improving the reliability of the optical co-packaging structure 1.

[0056] For example, Fig.13 As shown, after the first chip 13 and the optical chip 12 are electrically connected to the adapter board 11 , the gaps between the first chip 13 and the optical chip 12 and the redistribution layer 15 are filled to form a third filling layer 112 to increase the robustness and durability of the optical co-packaging structure 1 .

[0057] Step S8: The optical chip 12 is provided with an optical interface 17. After the first chip 13 and the optical chip 12 are electrically connected to the adapter board 11, the preparation method further includes: providing a heat dissipation cover 18 on the packaging substrate 10, wherein the heat dissipation cover 18 at least covers the adapter board 11, the first chip 13 and the optical chip 12, and exposes the optical interface 17, and finally forms a Figure 1 The optical co-packaging structure 1 is shown.

[0058] Exemplarily, a thermal interface material (TIM) is also provided between the heat dissipation cover 18 and the first chip 13 and the optical chip 12. The thermal interface material can not only bond the heat dissipation cover 18 and the chip, but also reduce the contact thermal resistance between the heat dissipation cover 18 and the chip, and has a good heat transfer effect. After installing the heat dissipation cover 18, the optical co-packaging structure 1 is cut to obtain a separate CPO chip.

[0059] Since the structure in which the electric chip 14 is embedded in the adapter board 11 reduces the overall height of the stacked electric chip 14 and the optical chip 12 (light engine), and the first chip 13 and the optical chip 12 are arranged side by side in a direction parallel to the plane where the packaging substrate 10 is located, the height difference between the first chip 13 and the light engine is reduced, which is conducive to the installation of the heat dissipation cover 18, thereby achieving the purpose of reducing the packaging height of the optical co-packaging structure 1. In addition, the structure in which the electric chip 14 is embedded in the adapter board 11 provides a new path for the heat dissipation of the electric chip 14, which is conducive to improving the heat dissipation efficiency of the light engine.

[0060] The preparation method of the optical co-packaging structure 1 provided in the embodiment of the present application electrically connects the adapter structure 11 embedded with the electric chip 14 to the packaging substrate 10, and then arranges the first chip 13 and the optical chip 12 on the side of the adapter board 11 away from the packaging substrate 10, and both are electrically connected to the electric chip 14, thereby realizing the electrical connection between the first chip 13, the optical chip 12 and the electric chip 14. The optical chip 12 and the electric chip 14 are stacked to form a vertically interconnected optical engine. Since the electric chip 14 is embedded in the adapter board 11, the area occupied by the optical engine on the packaging substrate 10 is reduced, thereby reducing the area of ​​the optical co-packaging structure 1 and improving the integration of the optical co-packaging structure 1. In addition, the connection distance between the optical chip 13 and the electric chip 14 is reduced, thereby reducing signal delay and improving signal integrity, thereby improving the overall performance of the optical co-packaging structure 1.

[0061] In some embodiments, the optical co-packaging structure 1 can be provided with multiple first chips 13, multiple optical chips 12 and multiple electrical chips 14, and a light engine formed by vertically stacking multiple optical chips 12 and electrical chips 14. The light engine can be arranged around the first chip 13 and interconnected with the first chip 13 through a redistribution layer 15. Multiple electrical chips 14 are embedded in the adapter board 11 to provide a more diverse optical co-packaging structure 1.

[0062] The embodiment of the present application also provides a second method for preparing an optical co-packaging structure. Figure 14 to Figure 17 A diagram showing the steps for preparing another optical co-packaging structure provided in an embodiment of the present application. Figure 7 After the electric chip 14 is arranged in the second region 192 in the first preparation method shown in FIG. 1 , the second preparation method includes the following steps to form the Figure 2 The optical co-packaging structure 1 is shown.

[0063] like Fig.14 As shown, the surface 190 of the carrier 19 also includes a third area 193, and a connection structure 16 is formed in the third area 193. The connection structure 16 is embedded in the adapter board 11, and along the direction X, the connection structure 16 is located on the inner side of the electrical chip 14. Exemplarily, the connection structure 16 can be a silicon bridge, and the embedding of the silicon bridge increases the wiring density of the adapter board 11 and increases the propagation path of the electrical signal, thereby reducing signal delay and improving the overall performance of the optical co-packaging structure 1.

[0064] After forming the connection structure 16, as Fig.15 As shown in FIG. 1 , a first filling layer 110 is formed on the surface of the carrier 19 to form the transfer plate 11. After the transfer plate 11 is formed, as shown in FIG. Fig.16 As shown, the carrier 19 is debonded from the adapter board 11, and solder balls 20 are formed on the surface of the adapter board. Then, a rewiring layer 15 is formed on the adapter board 11. The rewiring layer 15 includes a first conductive structure 151 and a second conductive structure 152. The first conductive structure 151 is electrically connected to the connecting structure 16, and the second conductive structure 152 is electrically connected to the connecting structure 16 and the electrical chip 14.

[0065] Then as Fig.17 As shown, the first chip 13 and the optical chip 12 are electrically connected to the adapter board 11, and the gaps between the first chip 13 and the optical chip 12 and the rewiring layer 15 are filled to form a third filling layer 112. Electrically connecting the first chip 13 and the optical chip 12 to the adapter board 11 includes electrically connecting the first chip 13 and the optical chip 12 to the rewiring layer 15, the first chip 13 is disposed on a side of the rewiring layer 15 away from the packaging substrate 10, and is electrically connected to the first conductive structure 151, and the optical chip 12 is disposed on a side of the rewiring layer 15 away from the packaging substrate 10, and is electrically connected to the second conductive structure 152. It can be understood that the first chip 13 can not only realize electrical connection with the optical chip 12 and the electrical chip 14 through the rewiring layer 15, but also the first chip 13 can be electrically connected to the optical chip 12 and the electrical chip 14 through the first conductive structure 151, the connection structure 16, and the second conductive structure 152 in sequence.

[0066] Finally, the heat dissipation cover 18 is disposed on the packaging substrate 10 to form a Figure 2 The optical co-packaging structure 1 is shown.

[0067] In another aspect, the present application also provides an optical device, Fig.18 A schematic diagram of an optical device provided in an embodiment of the present application, such as Fig.18 As shown, the optical device 2 includes the above-mentioned optical co-packaging structure 1 and a circuit board 22. The structure of the optical co-packaging structure 1 can be shown as follows: Figure 1 As shown, it can also be shown as Figure 2 As shown, the embodiment of the present application is as follows Figure 1 The optical co-packaging structure 1 shown is used as an example for explanation. The optical device 2 integrates optical computing technology or optical switching technology, and can be an optical computing device or an optical switching interconnection device. For example, when the first chip 13 is a computing chip, the optical device 2 is an optical computing device; when the first chip 13 is a switching chip, the optical device 2 is an optical switching interconnection device.

[0068] The optical co-packaging structure 1 is disposed on the circuit board 22 and is electrically connected to the circuit board 22. The optical co-packaging structure 1 and the circuit board 22 may be electrically connected via the first solder ball 21, or the micro-pads on the surface of the optical co-packaging structure 1 are exposed, and the optical co-packaging structure 1 and the circuit board 22 are directly electrically connected via the micro-pads. A plurality of optical co-packaging structures 1 may be integrated on the circuit board 22, and a second solder ball 23 is further disposed on the surface of the circuit board 22 away from the optical co-packaging structure 1.

[0069] The optical device 2 provided in the embodiment of the present application has an improved overall performance of the optical co-packaging structure 1, so that the reliability of the optical co-packaging structure 1 is improved, thereby also improving the reliability of the optical device 2.

[0070] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An optical co-packaging structure, characterized in that: include: Package substrate; An adapter plate, disposed on the packaging substrate and electrically connected to the packaging substrate; The adapter board includes an electric chip, and the electric chip is embedded in the adapter board; An optical chip is arranged on a side of the adapter plate away from the packaging substrate; the optical chip is stacked with the electrical chip and is electrically connected to the electrical chip; The first chip is arranged on a side of the adapter board away from the packaging substrate and is electrically connected to the optical chip and the electrical chip.

2. The optical co-packaging structure according to claim 1, characterized in that: The optical co-packaging structure further comprises a redistribution layer, wherein the redistribution layer is arranged on a side of the adapter plate away from the packaging substrate; The optical chip is arranged on a side of the rewiring layer away from the packaging substrate, and the optical chip is electrically connected to the electrical chip through the rewiring layer; The first chip is disposed on a side of the rewiring layer away from the packaging substrate, and the first chip is electrically connected to the optical chip and the electrical chip through the rewiring layer.

3. The optical co-packaging structure according to claim 1, characterized in that: The adapter plate further comprises a connection structure, wherein the connection structure is embedded in the adapter plate; The optical co-packaging structure further includes a rewiring layer, which is arranged on a side of the adapter plate away from the packaging substrate, and the rewiring layer includes a first conductive structure and a second conductive structure, the first conductive structure is electrically connected to the connection structure, and the second conductive structure is electrically connected to the connection structure and the electrical chip; The first chip is arranged on a side of the rewiring layer away from the packaging substrate and is electrically connected to the first conductive structure; the optical chip is arranged on a side of the rewiring layer away from the packaging substrate and is electrically connected to the second conductive structure.

4. The optical co-packaging structure according to claim 1, characterized in that: The optical chip is provided with an optical interface on a side away from the first chip; The optical co-packaging structure further includes a heat dissipation cover, which is disposed on the packaging substrate and covers at least the adapter board, the first chip and the optical chip, and exposes the optical interface.

5. A method for preparing an optical co-packaging structure, characterized in that: include: The adapter board is electrically connected to the packaging substrate, wherein the adapter board includes an electrical chip, and the electrical chip is embedded in the adapter board; The first chip and the optical chip are electrically connected to the adapter board, wherein the first chip is located on a side of the adapter board away from the packaging substrate and is electrically connected to the electrical chip; The optical chip is located on a side of the adapter plate away from the packaging substrate. The optical chip is stacked with the electrical chip and is electrically connected to the electrical chip.

6. The preparation method according to claim 5, characterized in that: Before electrically connecting the adapter board to the packaging substrate, forming the adapter board includes: Forming a plurality of third conductive structures on a carrier, wherein a surface of the carrier includes a first area and a second area, and the plurality of third conductive structures are located in the first area; placing the electric chip in the second area; A filling layer is formed on the surface of the carrier, wherein the filling layer is located between the plurality of third conductive structures and between the third conductive structure and the electric chip.

7. The preparation method according to claim 6, characterized in that: After forming the adapter plate, the preparation method further includes: forming a rewiring layer on the transfer board, wherein the rewiring layer is electrically connected to the plurality of third conductive structures and the electrical chip; The first chip and the optical chip are electrically connected to the adapter board, comprising: The first chip and the optical chip are electrically connected to the rewiring layer, the first chip is located on a side of the rewiring layer away from the packaging substrate, and the first chip is electrically connected to the optical chip and the electrical chip through the rewiring layer; the optical chip is located on a side of the rewiring layer away from the packaging substrate, and the optical chip is electrically connected to the electrical chip through the rewiring layer.

8. The preparation method according to claim 6, characterized in that: The surface of the carrier sheet further includes a third region. Before forming the filling layer, the preparation method further includes: forming a connection structure in the third region; After forming the adapter plate, the preparation method further includes: forming a rewiring layer on the transfer board, the rewiring layer comprising a first conductive structure and a second conductive structure, the first conductive structure being electrically connected to the connection structure, and the second conductive structure being electrically connected to the connection structure and the electrical chip; The first chip and the optical chip are electrically connected to the adapter board, comprising: The first chip and the optical chip are electrically connected to the rewiring layer, the first chip is located on a side of the rewiring layer away from the packaging substrate and is electrically connected to the first conductive structure; the optical chip is located on a side of the rewiring layer away from the packaging substrate and is electrically connected to the second conductive structure.

9. The preparation method according to claim 5, characterized in that: The optical chip is provided with an optical interface; After electrically connecting the first chip and the optical chip to the adapter plate, the preparation method further includes: A heat dissipation cover is disposed on the packaging substrate, wherein the heat dissipation cover at least covers the adapter board, the first chip and the optical chip, and exposes the optical interface.

10. An optical device, characterized in that: include: The optical co-packaging structure according to any one of claims 1 to 4; A circuit board, the optical co-packaging structure is arranged on the circuit board and is electrically connected to the circuit board.

Images