Optical co-packaged structure and method of manufacturing the same, optical device

Abstract

The application discloses an optical co-encapsulation structure and a preparation method thereof and optical equipment, and is suitable for the technical field of semiconductors. The optical co-encapsulation structure comprises a packaging substrate, an adapter plate, an optical chip and a first chip. The adapter plate is arranged on the packaging substrate and is electrically connected with the packaging substrate. The adapter plate comprises an electric chip, and the electric chip is embedded in the adapter plate. The optical chip is arranged on a side of the adapter plate away from the packaging substrate, the optical chip and the electric chip are arranged in a stack, and the optical chip is electrically connected with the electric chip. The first chip is arranged on the side of the adapter plate away from the packaging substrate and is electrically connected with the optical chip and the electric chip. The technical scheme of the application realizes the improvement of the overall performance of the optical co-encapsulation structure.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor technology, and particularly relates to an optical co-packaged structure and a preparation method thereof and an optical device. BACKGROUND

[0002] With the development of semiconductor technology, the optical co-packaged (CPO) technology has become a new research hotspot. However, in the 3D optical co-packaged structure, there are problems such as large height difference between the computing chip or the switching chip and the optical engine, and certain signal transmission delay, which have a bad influence on the overall performance of the optical co-packaged structure. SUMMARY

[0003] The present application provides an optical co-packaged structure and a preparation method thereof and an optical device, aiming to improve the overall performance of the optical co-packaged structure.

[0004] To achieve the above-mentioned purpose, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, an optical co-packaged structure is provided, which comprises a packaging substrate, an adapter board, an optical chip and a first chip. The adapter board is arranged on the packaging substrate and electrically connected with the packaging substrate. The adapter board comprises an electrical chip, and the electrical chip is embedded in the adapter board. The optical chip is arranged on a side of the adapter board away from the packaging substrate, and the optical chip and the electrical chip are stacked and electrically connected. The first chip is arranged on the side of the adapter board away from the packaging substrate and electrically connected with the optical chip and the electrical chip.

[0006] The optical co-packaged structure provided by the embodiments of the present application comprises a packaging substrate, an adapter board electrically connected with the packaging substrate, an optical chip and a first chip arranged on a side of the adapter board away from the packaging substrate, wherein the adapter board is embedded with an electrical chip, the electrical chip and the optical chip are stacked and electrically connected to form an optical engine, and the first chip is electrically connected with the optical chip, so as to realize the electrical connection of the first chip, the optical chip and the electrical chip. In the optical co-packaged structure, the electrical chip is embedded in the adapter board and stacked with the optical chip, which reduces the area occupied by the optical engine on the packaging substrate, thereby reducing the area of the optical co-packaged structure, improving the integration of the optical co-packaged structure, and reducing the connection distance between the optical chip and the electrical chip, thereby reducing signal delay and improving signal integrity, and thus improving the overall performance of the optical co-packaged structure.

[0007] In some embodiments, the optical co-packaging structure further comprises a re-distribution layer disposed on a side of the interposer distal to the packaging substrate. The optical chip is disposed on a side of the re-distribution layer distal to the packaging substrate, and is electrically connected to the electrical chip through the re-distribution layer. The first chip is disposed on a side of the re-distribution layer distal to the packaging substrate, and is electrically connected to the optical chip and the electrical chip through the re-distribution layer.

[0008] In some embodiments, the interposer further comprises a connection structure embedded in the interposer. The optical co-packaging structure further comprises a re-distribution layer disposed on a side of the interposer distal to the packaging substrate, the re-distribution layer comprising a first conductive structure and a second conductive structure, the first conductive structure being electrically connected to the connection structure, and the second conductive structure being electrically connected to the connection structure and the electrical chip. The first chip is disposed on a side of the re-distribution layer distal to the packaging substrate, and is electrically connected to the first conductive structure. The optical chip is disposed on a side of the re-distribution layer distal to the packaging substrate, and is electrically connected to the second conductive structure.

[0009] In some embodiments, the optical chip is provided with an optical interface on a side distal to the first chip. The optical co-packaging structure further comprises a heat dissipation cover disposed on the packaging substrate, covering at least the interposer, the first chip and the optical chip, and exposing the optical interface.

[0010] In another aspect, the present application also provides a method for manufacturing an optical co-packaging structure, the method comprising: electrically connecting an interposer to a packaging substrate, the interposer comprising an electrical chip embedded in the interposer; and electrically connecting a first chip and an optical chip to the interposer, the first chip being disposed on a side of the interposer distal to the packaging substrate and being electrically connected to the electrical chip, and the optical chip being disposed on a side of the interposer distal to the packaging substrate, the optical chip being stacked with the electrical chip and being electrically connected to the electrical chip.

[0011] The method for manufacturing an optical co-packaging structure provided by the embodiments of the present application electrically connects an interposer embedded with an electrical chip to a packaging substrate, and then arranges a first chip and an optical chip on a side of the interposer distal to the packaging substrate, and electrically connects the first chip and the optical chip to the electrical chip, thereby realizing electrical connection of the first chip, the optical chip and the electrical chip. The optical chip and the electrical chip are stacked to form a vertical interconnection optical engine. Since the electrical chip is embedded in the interposer, the area occupied by the optical engine on the packaging substrate is reduced, thereby reducing the area of the optical co-packaging structure, improving the integration of the optical co-packaging structure, and reducing the connection distance between the optical chip and the electrical chip, thereby reducing signal delay and improving signal integrity, and thereby improving the overall performance of the optical co-packaging structure.

[0012] In some embodiments, before electrically connecting the adapter plate and the package substrate, the adapter plate is formed, including forming a plurality of third conductive structures on a carrier sheet, a surface of the carrier sheet including a first region and a second region, the plurality of third conductive structures being located at the first region, disposing an electrical chip at the second region, forming a filling layer on the surface of the carrier sheet, the filling layer being located between the plurality of third conductive structures and between the third conductive structures and the electrical chip.

[0013] In some embodiments, after forming the adapter plate, the method further includes forming a re-distribution layer on the adapter plate, the re-distribution layer being electrically connected with the plurality of third conductive structures and the electrical chip. Electrically connecting the first chip and the optical chip with the adapter plate includes electrically connecting the first chip and the optical chip with the re-distribution layer, the first chip being located at a side of the re-distribution layer away from the package substrate, the first chip being electrically connected with the optical chip and the electrical chip through the re-distribution layer. The optical chip is located at a side of the re-distribution layer away from the package substrate, the optical chip being electrically connected with the electrical chip through the re-distribution layer.

[0014] In some embodiments, the surface of the carrier sheet further includes a third region, before forming the filling layer, the method further includes forming a connection structure at the third region. After forming the adapter plate, the method further includes forming a re-distribution layer on the adapter plate, the re-distribution layer including a first conductive structure and a second conductive structure, the first conductive structure being electrically connected with the connection structure, the second conductive structure being electrically connected with the connection structure and the electrical chip. Electrically connecting the first chip and the optical chip with the adapter plate includes electrically connecting the first chip and the optical chip with the re-distribution layer, the first chip being located at a side of the re-distribution layer away from the package substrate and being electrically connected with the first conductive structure, the optical chip being located at a side of the re-distribution layer away from the package substrate and being electrically connected with the second conductive structure.

[0015] In some embodiments, the optical chip is provided with an optical interface, after electrically connecting the first chip and the optical chip with the adapter plate, the method further includes disposing a heat dissipation cover on the package substrate, the heat dissipation cover covering at least the adapter plate, the first chip and the optical chip, and exposing the optical interface.

[0016] In another aspect, the present application also provides an optical device, the optical device including the optical co-packaging structure mentioned above, and a circuit board, the optical co-packaging structure being disposed on the circuit board and being electrically connected with the circuit board. The optical device provided by the embodiments of the present application improves the overall performance of the optical co-packaging structure, so that the reliability of the optical co-packaging structure is improved, and thus the reliability of the optical device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description, taken in conjunction with the following drawings in which:

[0018] Figure 1 A schematic diagram of an optical co-packaging structure provided by an embodiment of the present application;

[0019] Figure 2 A schematic diagram of another optical co-packaging structure provided by an embodiment of the present application;

[0020] Figure 3 A flow chart of a preparation process of an optical co-packaging structure provided by an embodiment of the present application;

[0021] Figures 4-13 A flow chart of a preparation process of an optical co-packaging structure provided by an embodiment of the present application; Figure 3 A flow chart of a preparation process of an optical co-packaging structure provided by an embodiment of the present application;

[0022] Figures 14-17 A flow chart of a preparation process of an optical co-packaging structure provided by an embodiment of the present application;

[0023] Figure 18 A schematic diagram of an optical co-packaging structure provided by an embodiment of the present application; DETAILED DESCRIPTION

[0024] The technical solutions in some embodiments of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present application.

[0025] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is to be interpreted as open, inclusive, meaning "including, but not limited to".

[0026] Hereinafter, the terms "first" and "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0027] In describing some embodiments, the term "connected" and its derivatives can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. For example, in describing some embodiments, the term "connected" can be used to indicate that two or more components have direct physical or electrical contact with each other.

[0028] Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action "based on" one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0029] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0030] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are idealized examples. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0031] Examples of the described embodiments are illustrated in the accompanying drawings, throughout which like reference characters are used to designate like elements or elements having similar functions. The embodiments described below are exemplary only, and are not to be construed as limiting the present application.

[0032] With the explosive growth of data traffic, there is an increasing demand for data communication solutions with higher speed, lower power consumption, and lower latency. Due to the limitations of Moore's Law, traditional pluggable optical modules are facing limitations in bandwidth, latency, energy efficiency, and speed. Silicon photonics technology, which uses semiconductor manufacturing technology to realize optical and electrical component interconnection on a silicon chip, opens up new possibilities for high-density multi-channel solution design. Therefore, optical co-packaging technology has emerged.

[0033] Optical co-packaging technology greatly reduces the volume and weight of the optical co-packaging structure by integrating a silicon optical chip, i.e., an electrical chip including an electronic integrated circuit (EIC) and an optical chip including a photon integrated circuit (PIC), with a computing / switching (XPU / Switch) chip in the form of advanced packaging (2.5D / 3D process), shortens the connection distance between chips, reduces signal delay, improves signal transmission speed and bandwidth, and achieves low latency, low power consumption, and high performance.

[0034] However, the CPO structure in related technologies has some problems that urgently need to be solved. For the 2.5D optoelectronic co-package structure, the electrical chip and the optical chip are integrated side by side on the interposer, resulting in a large package area. The interposer connects the application-specific integrated circuit (ASIC) chip / switch, electrical chip, and optical chip through microbumps to achieve chip interconnection. The interposer can also connect fiber optic assemblies with PIC fiber blocks, which requires very high alignment accuracy (1μm) to achieve good optical coupling efficiency.

[0035] For 3D optoelectronic co-packaging structures, electrical and optical chips are vertically stacked and interconnected via through-silicon vias (TSVs) or through-molding vias (TMVs) to form an optical engine. This allows for further reduction in package area and distance between the optical engine and the ASIC chip, leading to further reductions in signal delay and loss. However, due to the significant heat generated by the electrical chip, the 3D stacking of the electrical and optical chips exacerbates heat dissipation issues, potentially causing a decrease in optoelectronic performance, especially since temperature drift has a significant impact on optical characteristics. Furthermore, the large height difference between the optical engine and the first chip hinders the installation of heat dissipation devices and heat sinks, which may reduce the reliability of the package structure.

[0036] To address the aforementioned problems, embodiments of this application provide an optical co-packaging structure 1. Figure 1 This is a schematic diagram of an optical co-packaging structure provided in an embodiment of this application, as shown below. Figure 1 As shown, the optical co-packaging structure 1 includes a packaging substrate 10, an adapter plate 11, an optical chip 12, and a first chip 13. The adapter plate 11 is disposed on and electrically connected to the packaging substrate 10. For example, the adapter plate 11 is electrically connected to the packaging substrate 10 via solder balls 20, or microbumps are provided on the side of the adapter plate 11 closest to the packaging substrate, allowing the adapter plate 11 to be electrically connected to the packaging substrate 10 via the microbumps. The adapter plate 11 includes an electrical chip 14 embedded within it. The embodiments provided in this application illustrate this with two electrical chips 14 embedded side-by-side within the adapter plate 11.

[0037] An optical chip 12 is disposed on the side of the adapter plate 11 away from the packaging substrate 10. The optical chip 12 and the electrical chip 14 are stacked and electrically connected, i.e., along the Z direction, the optical chip 12 is disposed above the electrical chip 14, and the optical chip 12 and the electrical chip 14 are vertically stacked and electrically connected to form an "optical engine". A first chip 13 is disposed on the side of the adapter plate 11 away from the packaging substrate 10, and is electrically connected to the optical chip 12 and the electrical chip 14 through the adapter plate 11. For example, the first chip 13 can be a computing chip or a switching chip. When the first chip 13 is a computing chip, the optical co-package structure 1 is an optical computing package structure; when the first chip 13 is a switching chip, the optical co-package structure 1 is an optical switching package structure. Along the X direction, the first chip 13 and the optical chip 12 are arranged side by side to obtain a 3D packaged optical co-package structure 1.

[0038] The optical co-packaging structure 1 provided in this application embodiment includes a packaging substrate 10, a transition plate 11 electrically connected to the packaging substrate 10, an optical chip 12 and a first chip 13 disposed on the side of the transition plate 11 away from the packaging substrate 10. The transition plate 11 embeds an electrical chip 14, which is stacked and electrically connected to the optical chip 12 to form an optical engine. The first chip 13 is electrically connected to the optical chip 12, thereby achieving electrical communication between the first chip 13, the optical chip 12, and the electrical chip 14. In the optical co-packaging structure 1, the structure of the electrical chip 14 embedded in the transition plate 11 and stacked with the optical chip 12 reduces the area occupied by the optical engine on the packaging substrate 10, thereby reducing the area of ​​the optical co-packaging structure 1, improving the integration of the optical co-packaging structure 1, and reducing the connection distance between the optical chip 12 and the electrical chip 14, thereby reducing signal delay and improving signal integrity, thus improving the overall performance of the optical co-packaging structure 1.

[0039] In some embodiments, such as Figure 1 As shown, the optical co-package structure 1 further includes a redistribution layer 15, which is disposed on the side of the adapter plate 11 away from the packaging substrate 10. The redistribution layer 15 can be a single-layer conductive structure or a multi-layer conductive structure, and micro pads are provided on the side of the redistribution layer 15 away from the adapter plate 11. The optical chip 12 is disposed on the side of the redistribution layer 15 away from the packaging substrate 10, and the optical chip 12 is electrically connected to the electrical chip 14 through the redistribution layer 15. The first chip 13 is disposed on the side of the redistribution layer 15 away from the packaging substrate 10, and the first chip 13 is electrically connected to the optical chip 12 and the electrical chip 14 through the redistribution layer 15. For example, microbumps are provided on the surface of the optical chip 12 and the first chip 13 near the packaging substrate 10, and the microbumps of the optical chip 12 and the first chip 13 are electrically connected to the micro pads of the redistribution layer 15 by thermo-bonding.

[0040] Compared to related technologies where electrical and optical chips are vertically interconnected via TSV or TMV to form an optical engine, the structure in this application where optical chip 12 and electrical chip 14 are connected via redistribution layer 15 reduces the area of ​​the optical co-package structure 1 projected onto the XY plane, making the distance between the optical engine and the first chip 13 smaller, and eliminating the need for TSV processing, thus reducing the process difficulty of fabricating the optical co-package structure 1, improving its process reliability, and thereby improving the reliability of the optical co-package structure 1.

[0041] In some embodiments, Figure 2 A schematic diagram of another optical co-packaging structure provided in this application embodiment is shown below. Figure 2 As shown, the adapter board 11 also includes a connection structure 16, which is embedded within the adapter board 11 and located inside the electrical chip 14 along the X direction. For example, the connection structure 16 can be a silicon bridge. The embedding of the silicon bridge increases the wiring density of the adapter board 11, increases the propagation path of electrical signals, thereby reducing signal delay and improving the overall performance of the optical co-package structure 1. The optical co-package structure 1 also includes a redistribution layer 15, which is disposed on the side of the adapter board 11 away from the packaging substrate 10. The redistribution layer 15 can be a single-layer conductive structure or a multi-layer conductive structure, and micropads are provided on the side of the redistribution layer 15 away from the adapter board 11.

[0042] The redistribution layer 15 includes a first conductive structure 151 and a second conductive structure 152. The first conductive structure 151 is electrically connected to the connection structure 16, and the second conductive structure 152 is electrically connected to the connection structure 16 and the electrical chip 14. A first chip 13 is disposed on the side of the redistribution layer 15 away from the packaging substrate 10 and is electrically connected to the first conductive structure 151. An optical chip 12 is disposed on the side of the redistribution layer 15 away from the packaging substrate 10 and is electrically connected to the second conductive structure 152. It is understood that the first chip 13 can not only achieve electrical connection with the optical chip 12 and the electrical chip 14 through the redistribution layer 15, but also can be sequentially electrically connected to the optical chip 12 and the electrical chip 14 through the first conductive structure 151, the connection structure 16, and the second conductive structure 152.

[0043] In some embodiments, such as Figure 1 and Figure 2As shown, the optical chip 12 has an optical interface 17 on its side away from the first chip 13. The optical interface 17 is an optical interface or coupling area on the optical chip 12, used to connect to a fiber array unit (FAU) to realize the input and output of optical signals. In the embodiment provided in this application, along the X direction, the optical interface 17 of the optical chip 12 is located on the outer side, achieving edge coupling, improving coupling efficiency, and ensuring the photoelectric performance of the optical chip 12. Furthermore, the outer edge of the optical interface 17 extends beyond the outer edge of the optical co-package structure 1, which is beneficial for the connection between the optical interface 17 and the FAU.

[0044] The optical co-package structure 1 also includes a heat sink 18, which is disposed on the packaging substrate 10. The heat sink 18 covers at least the adapter plate 11, the first chip 13, and the optical chip 12, and exposes the optical interface 17. Because the structure of the electrical chip 14 embedded in the adapter plate 11 reduces the overall height of the stacked electrical chip 14 and optical chip 12 (optical engine), and because the first chip 13 and optical chip 12 are arranged side-by-side along the X direction, the height difference between the first chip 13 and the optical engine is reduced, which facilitates the installation of the heat sink 18 and achieves the purpose of reducing the packaging height of the optical co-package structure 1. Furthermore, the structure of the electrical chip 14 embedded in the adapter plate 11 provides a new path for the heat dissipation of the electrical chip 14, which is beneficial to improving the heat dissipation efficiency of the optical engine.

[0045] In the embodiments provided in this application, the heat sink 18 and the packaging substrate 10 surround the first chip 13, the optical chip 12, and the electrical chip 14, exposing only the surface on the side where the optical interface 17 is located. This achieves isolation and protection for the first chip 13 and the optical engine. Furthermore, the heat sink 18 has a certain heat dissipation function, which is beneficial to improving the heat conduction speed. For example, a thermal interface material (TIM) is also provided between the heat sink 18 and the first chip 13 and the optical engine. The TIM can not only bond the heat sink 18 and the first chip 13 and the optical chip 12, but also reduce the contact thermal resistance between the heat sink 18 and the first chip 13 and the optical chip 12, thus having a good heat transfer effect.

[0046] On the other hand, embodiments of this application provide a method for fabricating an optical co-packaging structure. Figure 3 A flowchart illustrating the fabrication process of an optical co-packaging structure provided in this application embodiment; Figures 4-13 for Figure 3 The diagram shows the steps of the preparation process. (See attached diagram.) Figure 3 As shown, the preparation method includes the following steps S1 to S8:

[0047] Step S1: As Figure 4As shown, microbumps are fabricated on either the optical wafer or the electrical wafer using a bumping process. The optical wafer and the electrical wafer are then diced to form an optical chip 12 and a first chip 13. A first microbump 130 is formed on the surface of the first chip 13, and a second microbump 120 is formed on the surface of the optical chip 12. Alternatively, readily available optical chips 12 and 13 with microbumps can be used. One side of the optical chip 12 has an optical interface 17 exposed by dicing the optical wafer. The optical interface 17 is an optical interface or coupling area on the optical chip 12, used to connect to the FAU to realize the input and output of optical signals. The first chip 13 can be a computing chip or a switching chip. When the first chip 13 is a computing chip, the optical co-package structure 1 is an optical computing package structure; when the first chip 13 is a switching chip, the optical co-package structure 1 is an optical switching package structure.

[0048] Step S2: As Figure 5 As shown, a carrier 19 is provided. Exemplarily, the carrier 19 can be a wafer or a glass temporary carrier. The embodiments provided in this application are illustrated using the carrier 19 as a glass temporary carrier. Then, as... Figure 6 As shown, a temporary bonding adhesive is applied to the surface of the substrate 19, and a plurality of third conductive structures 153 are formed on the substrate 19. The plurality of third conductive structures 153 are copper pillar bumps. The surface 190 of the substrate 19 includes a first region 191 and a second region 192. The plurality of third conductive structures 153 are located in the first region 191, and the second region 192 is left empty as the placement position of the electrical chip 14.

[0049] Step S3: As Figure 7 As shown, the electrical chip 14 is disposed in the second region 192, so that the electrical chip 14 is embedded in the adapter board 11. The embodiment provided in this application is illustrated by taking two electrical chips 14 embedded side by side in the adapter board 11 as an example.

[0050] Step S4: As Figure 8 As shown, a first filler layer 110 is formed on the surface 190 of the substrate 19 to form the adapter plate 11. The first filler layer 110 is located between a plurality of third conductive structures 153 and between the third conductive structures 153 and the electrical chip 14.

[0051] Step S5: As Figure 9 As shown, a redistribution layer 15 is formed on the adapter board 11. The redistribution layer 15 is electrically connected to a plurality of third conductive structures 153 and electrical chips 14. For example, the redistribution layer 15 is also provided with micro pads for electrically connecting to the first micro bump 130 and the second micro bump 120.

[0052] Step S6: After forming the redistribution layer 15, the above preparation method further includes, as follows: Figure 10As shown, the substrate 19 is debonded to the adapter board 11, and solder balls 20 are prepared on the surface of the adapter board 11 away from the redistribution layer 15. Then, as shown... Figure 11 As shown, the adapter plate 11 is electrically connected to the packaging substrate 10. The adapter plate 11 and the packaging substrate 10 can be electrically connected by solder balls 20. Alternatively, microbumps can be provided on the side of the adapter plate 11 near the packaging substrate so that the adapter plate 11 is electrically connected to the packaging substrate 10 through the microbumps.

[0053] For example, see [link to previous article] Figure 11 After the adapter plate 11 and the packaging substrate 10 are electrically connected by solder balls 20, a second filler layer 111 is formed between the adapter plate 11 and the packaging substrate 10 to increase the robustness and durability of the connection between the adapter plate 11 and the packaging substrate 10.

[0054] Step S7: As Figure 12 As shown, the first chip 13 and the optical chip 12 are electrically connected to the adapter plate 11, that is, the first microbump 130 of the first chip 13 and the second microbump 120 of the optical chip 12 are electrically connected to the microbumps on the redistribution layer 15 by thermoforming bonding. The first chip 13 is located on the side of the adapter plate 11 away from the packaging substrate 10, and the first chip 13 is electrically connected to the electrical chip 14 through the redistribution layer 15. The optical chip 12 is located on the side of the adapter plate 11 away from the packaging substrate 10. The optical chip 12 and the electrical chip 14 are stacked to form a vertically stacked optical engine, and the optical chip 12 and the electrical chip 14 are electrically connected through the redistribution layer 15.

[0055] Compared to related technologies where electrical chips and optical chips are vertically interconnected via TSV or TMV to form an optical engine, the structure in this application where optical chip 12 and electrical chip 14 are connected via redistribution layer 15 reduces the area of ​​the optical co-package structure 1 projected onto the plane of the packaging substrate 10, making the distance between the optical engine and the first chip 13 smaller, and eliminating the need for TSV process, thus reducing the process difficulty of fabricating the optical co-package structure 1, improving its process reliability, and thereby improving the reliability of the optical co-package structure 1.

[0056] For example, such as Figure 13 As shown, after the first chip 13 and the optical chip 12 are electrically connected to the adapter board 11, the gap between the first chip 13 and the optical chip 12 and the redistribution layer 15 is filled to form a third filling layer 112, so as to increase the robustness and durability of the optical co-package structure 1.

[0057] Step S8: The optical chip 12 is provided with an optical interface 17. After electrically connecting the first chip 13 and the optical chip 12 to the adapter board 11, the above preparation method further includes placing a heat sink 18 on the packaging substrate 10. The heat sink 18 at least covers the adapter board 11, the first chip 13, and the optical chip 12, and exposes the optical interface 17, ultimately forming as shown in the figure. Figure 1 The optical co-packaging structure 1 is shown.

[0058] For example, a thermal interface material (TIM) is also provided between the heat sink 18 and the first chip 13 and the optical chip 12. The thermal interface material can not only bond the heat sink 18 and the chip, but also reduce the contact thermal resistance between the heat sink 18 and the chip, and has a good heat transfer effect. After the heat sink 18 is installed, the optical co-package structure 1 can be cut to obtain a separate CPO chip.

[0059] Because the structure of the electrical chip 14 embedded in the adapter plate 11 reduces the overall height of the stacked electrical chip 14 and optical chip 12 (optical engine), and because the first chip 13 and optical chip 12 are arranged side by side along the plane parallel to the packaging substrate 10, the height difference between the first chip 13 and the optical engine is reduced, which is beneficial for the installation of the heat sink 18 and achieves the purpose of reducing the packaging height of the optical co-packaging structure 1. Furthermore, the structure of the electrical chip 14 embedded in the adapter plate 11 provides a new path for the heat dissipation of the electrical chip 14, which is beneficial for improving the heat dissipation efficiency of the optical engine.

[0060] The method for fabricating the optical co-package structure 1 provided in this application embodiment electrically connects the adapter structure with embedded electrical chip 14 to the packaging substrate 10. Then, the first chip 13 and the optical chip 12 are disposed on the side of the adapter plate 11 away from the packaging substrate 10, and both are electrically connected to the electrical chip 14, thereby realizing the electrical connection between the first chip 13, the optical chip 12, and the electrical chip 14. The optical chip 12 and the electrical chip 14 are stacked to form a vertically interconnected optical engine. Since the electrical chip 14 is embedded in the adapter plate 11, the area occupied by the optical engine on the packaging substrate 10 is reduced, thereby reducing the area of ​​the optical co-package structure 1, improving the integration of the optical co-package structure 1, and reducing the connection distance between the optical chip 12 and the electrical chip 14, thereby reducing signal delay and improving signal integrity, thus improving the overall performance of the optical co-package structure 1.

[0061] In some embodiments, the optical co-packaging structure 1 may be provided with a plurality of first chips 13, a plurality of optical chips 12 and a plurality of electrical chips 14, and an optical engine formed by vertically stacking a plurality of optical chips 12 and electrical chips 14. The optical engine may be arranged around the first chip 13 and interconnected with the first chip 13 through a redistribution layer 15. The plurality of electrical chips 14 are embedded in the adapter board 11 to provide a more diverse optical co-packaging structure 1.

[0062] The embodiments of this application also provide a method for fabricating a second optical co-packaging structure. Figures 14-17 This diagram illustrates the fabrication steps of another optical co-packaging structure provided in an embodiment of this application. In such... Figure 7 The first fabrication method shown depicts the placement of the electrical chip 14 after the second region 192. The second fabrication method includes the following steps to form as shown... Figure 2 The optical co-packaging structure 1 is shown.

[0063] like Figure 14 As shown, the surface 190 of the carrier 19 also includes a third region 193, in which a connection structure 16 is formed. The connection structure 16 is embedded within the adapter plate 11 and is located inside the electrical chip 14 along the X direction. For example, the connection structure 16 can be a silicon bridge. The embedding of the silicon bridge increases the wiring density of the adapter plate 11, increases the propagation path of electrical signals, thereby reducing signal delay and improving the overall performance of the optical co-package structure 1.

[0064] After forming the connection structure 16, as follows Figure 15 As shown, a first filler layer 110 is formed on the surface of the substrate 19 to form the adapter plate 11. After the adapter plate 11 is formed, as... Figure 16 As shown, the carrier 19 is debonded to the adapter board 11, and solder balls 20 are formed on the surface of the adapter board. Then, a redistribution layer 15 is formed on the adapter board 11. The redistribution layer 15 includes a first conductive structure 151 and a second conductive structure 152. The first conductive structure 151 is electrically connected to the connection structure 16, and the second conductive structure 152 is electrically connected to the connection structure 16 and the electrical chip 14.

[0065] Then as Figure 17 As shown, the first chip 13 and the optical chip 12 are electrically connected to the adapter board 11, and the gap between the first chip 13, the optical chip 12 and the redistribution layer 15 is filled to form a third filling layer 112. Electrically connecting the first chip 13 and the optical chip 12 to the adapter board 11 includes electrically connecting the first chip 13 and the optical chip 12 to the redistribution layer 15. The first chip 13 is disposed on the side of the redistribution layer 15 away from the packaging substrate 10 and is electrically connected to the first conductive structure 151. The optical chip 12 is disposed on the side of the redistribution layer 15 away from the packaging substrate 10 and is electrically connected to the second conductive structure 152. It can be understood that the first chip 13 can not only achieve electrical connection with the optical chip 12 and the electrical chip 14 through the redistribution layer 15, but also can be electrically connected to the optical chip 12 and the electrical chip 14 sequentially through the first conductive structure 151, the connection structure 16, and the second conductive structure 152.

[0066] Finally, the heat sink 18 is placed on the packaging substrate 10 to form a structure as shown in the figure. Figure 2 The optical co-packaging structure 1 is shown.

[0067] Furthermore, this application also provides an optical device. Figure 18 This is a schematic diagram of the optical device provided in the embodiments of this application, such as... Figure 18 As shown, the optical device 2 includes the aforementioned optical co-package structure 1 and a circuit board 22. A schematic diagram of the optical co-package structure 1 can be seen as follows: Figure 1 As shown in the figure, or as illustrated in the diagram. Figure 2 As shown, the embodiments of this application are as follows Figure 1 The optical co-package structure 1 shown is used as an example for explanation. The optical device 2 integrates optical computing technology or optical switching technology and can be an optical computing device or an optical switching interconnect device. For example, if the first chip 13 is a computing chip, the optical device 2 is an optical computing device; if the first chip 13 is a switching chip, the optical device 2 is an optical switching interconnect device.

[0068] An optical co-package structure 1 is disposed on and electrically connected to a circuit board 22. The optical co-package structure 1 and the circuit board 22 can be electrically connected via a first solder ball 21, or by exposing micro pads on the surface of the optical co-package structure 1, the optical co-package structure 1 and the circuit board 22 can be directly electrically connected via the micro pads. Multiple optical co-package structures 1 can be integrated on the circuit board 22. A second solder ball 23 is also disposed on the side of the circuit board 22 away from the optical co-package structure 1.

[0069] The optical device 2 provided in this application embodiment has improved overall performance of the optical co-packaging structure 1, which improves the reliability of the optical co-packaging structure 1, thereby also improving the reliability of the optical device 2.

[0070] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An optical co-packaging structure, characterized in that, include: Packaging substrate; An adapter board is disposed on the packaging substrate and electrically connected to the packaging substrate. The adapter board includes an electrical chip embedded in the adapter board, and the adapter board and the electrical chip have the same height. An optical chip is disposed on the side of the adapter plate away from the packaging substrate; The first chip is disposed on the side of the adapter plate away from the packaging substrate and is electrically connected to the optical chip and the electrical chip. A rewiring layer is disposed on the side of the adapter board away from the packaging substrate. The optical chip is disposed on the side of the redistribution layer away from the packaging substrate, and the optical chip is electrically connected to the electrical chip through the redistribution layer. The first chip is disposed on the side of the redistribution layer away from the packaging substrate, and the first chip is electrically connected to the optical chip and the electrical chip through the redistribution layer. The optical chip and the electrical chip are stacked vertically and electrically connected through the redistribution layer to form an optical engine. The first chip and the optical chip are arranged side by side in the horizontal direction. The adapter plate also includes a connecting structure, which is embedded within the adapter plate; The redistribution layer includes a first conductive structure and a second conductive structure, wherein the first conductive structure is electrically connected to the connection structure, and the second conductive structure is electrically connected to the connection structure and the electrical chip. The first chip is disposed on the side of the redistribution layer away from the packaging substrate and is electrically connected to the first conductive structure; the optical chip is disposed on the side of the redistribution layer away from the packaging substrate and is electrically connected to the second conductive structure. The optical chip has an optical interface on the side away from the first chip; The optical co-packaging structure further includes a heat dissipation cover, which is disposed on the packaging substrate and covers at least the adapter board, the first chip and the optical chip, and exposes the optical interface.

2. A method for preparing an optical co-encapsulation structure, used to prepare the optical co-encapsulation structure of claim 1, characterized in that, include: The adapter board is electrically connected to the packaging substrate, and the adapter board includes an electrical chip embedded in the adapter board; The first chip and the optical chip are electrically connected to the adapter board. The first chip is located on the side of the adapter board away from the packaging substrate and is electrically connected to the electrical chip. The optical chip is located on the side of the adapter plate away from the packaging substrate. The optical chip and the electrical chip are stacked vertically and electrically connected to form an optical engine. The adapter board is formed before it is electrically connected to the packaging substrate, and includes: Multiple third conductive structures are formed on a substrate, the surface of which includes a first region and a second region, and the multiple third conductive structures are located in the first region; The electrical chip is disposed in the second region; A filler layer is formed on the surface of the carrier wafer, the filler layer being located between the plurality of third conductive structures and between the third conductive structures and the electrical chip; After the adapter board is formed, a redistribution layer is formed on the adapter board, and the redistribution layer is electrically connected to the plurality of third conductive structures and the electrical chip; Electrically connecting the first chip and the optical chip to the adapter board includes: The first chip and the optical chip are electrically connected to the redistribution layer. The first chip is located on the side of the redistribution layer away from the packaging substrate. The first chip is electrically connected to the optical chip and the electrical chip through the redistribution layer. The optical chip is located on the side of the redistribution layer away from the packaging substrate. The optical chip is electrically connected to the electrical chip through the redistribution layer. The surface of the substrate further includes a third region, and the preparation method further includes, prior to forming the filler layer: A connection structure is formed in the third region; After forming the adapter plate, the preparation method further includes: A redistribution layer is formed on the adapter board. The redistribution layer includes a first conductive structure and a second conductive structure. The first conductive structure is electrically connected to the connection structure, and the second conductive structure is electrically connected to the connection structure and the electrical chip. Electrically connecting the first chip and the optical chip to the adapter board includes: The first chip and the optical chip are electrically connected to the redistribution layer. The first chip is located on the side of the redistribution layer away from the packaging substrate and is electrically connected to the first conductive structure. The optical chip is located on the side of the redistribution layer away from the packaging substrate and is electrically connected to the second conductive structure. The optical chip is provided with an optical interface. After electrically connecting the first chip and the optical chip to the adapter board, the fabrication method further includes: A heat sink is disposed on the packaging substrate, the heat sink covering at least the adapter board, the first chip and the optical chip, and exposing the optical interface.

3. An optical device, characterized in that, include: The optical co-packaging structure as described in any one of claims 1; The circuit board, wherein the optical co-package structure is disposed on the circuit board and electrically connected to the circuit board.

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