Optical co-packaging structure, preparation method thereof and optical equipment

Abstract

The invention discloses an optical co-packaging structure, a preparation method thereof and optical equipment, and is suitable for the technical field of semiconductors, the optical co-packaging structure comprises a packaging substrate, a first chip and a stacking structure, the packaging substrate comprises a first surface and a second surface which are oppositely arranged, the first surface is provided with a groove, and the second surface is provided with a second chip; the groove extends into the packaging substrate from the first surface, the first chip is bonded with the first surface, the stacking structure comprises an optical chip and an electric chip which are bonded, one surface, bonded with the electric chip, of the optical chip comprises a first rewiring layer, one side, far away from the optical chip, of at least part of the first rewiring layer is provided with a first connecting terminal, and the first connecting terminal is connected with the optical chip. The first connecting terminal is in bonding connection with the first surface of the packaging substrate, and the electric chip is embedded in the groove. According to the technical scheme of the invention, the overall performance of the optical co-packaging structure is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to an optical co-packaging structure and a preparation method thereof, and an optical device. Background Art

[0002] With the development of semiconductor technology, co-packaged optics (CPO) technology has become a new research hotspot. However, in the 3D optoelectronic co-packaging structure, there are problems such as a large height difference between the computing chip or switching chip and the optical engine, and a certain delay in signal transmission. These problems have an adverse effect on the overall performance of the optical co-package structure. Summary of the invention

[0003] The present application proposes an optical co-packaging structure and a preparation method thereof, and an optical device, aiming to improve the overall performance of the optical co-packaging structure.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, an optical co-packaging structure is provided, which includes a packaging substrate, a first chip and a stacking structure, wherein the packaging substrate includes a first surface and a second surface arranged opposite to each other, the first surface is provided with a groove, the groove extends from the first surface to the packaging substrate, the first chip is bonded to the first surface, and the stacking structure includes a bonded optical chip and an electrical chip, wherein a side of the optical chip bonded to the electrical chip includes a first redistribution layer, a first connection terminal is provided on a side of at least part of the first redistribution layer away from the optical chip, the first connection terminal is bonded to the first surface of the packaging substrate, and the electrical chip is embedded in the groove.

[0006] In some embodiments, a second redistribution layer is disposed on the first surface, and the first chip and the optical chip are electrically connected via the second redistribution layer.

[0007] In some embodiments, the packaging substrate further includes a connection structure disposed in the packaging substrate, and the first chip and the optical chip are electrically connected via the connection structure.

[0008] In some embodiments, the optical chip has an optical interface formed on a side away from the first chip, and the optical packaging structure further includes a heat dissipation cover, which at least covers the first chip and the stacking structure, and exposes the optical interface.

[0009] In the optical co-packaging structure provided in the embodiment of the present application, the optical chip and the electrical chip are bonded through the first rewiring layer to form a 3D integrated stacking structure. By setting the first rewiring layer on the optical chip, a shorter connection distance between the optical chip and the electrical chip can be achieved, thereby reducing signal delay and improving signal integrity. The stacking structure is bonded to the first surface of the packaging substrate through the first connecting terminal, which reduces the area occupied by the optical engine on the packaging substrate, thereby reducing the area of ​​the optical co-packaging structure and improving the integration of the optical co-packaging structure. The electrical chip is embedded in the groove of the packaging substrate, and the first surface is also bonded to the first chip, so that the height difference between the first chip and the stacking structure relative to the packaging substrate is reduced, which facilitates the subsequent installation of thermal conductive materials and heat dissipation covers to reduce the packaging height of the optical co-packaging structure. In addition, the structure in which the electrical chip is embedded in the groove provides a new path for the heat dissipation of the electrical chip, which is beneficial to improving its heat dissipation efficiency.

[0010] On the other hand, the present application also provides an optical device, which includes the above-mentioned optical co-packaging structure and a circuit board, wherein the optical co-packaging structure is electrically connected to the circuit board. In the optical device provided by the embodiment of the present application, the overall performance of the optical co-packaging structure is improved, so that the reliability of the optical co-packaging structure is improved, thereby also improving the reliability of the optical device.

[0011] On the other hand, the present application also provides a method for preparing an optical co-packaging structure, the preparation method comprising: providing a packaging substrate, the packaging substrate comprising a first surface and a second surface arranged opposite to each other, forming a groove on the first surface, the groove extending from the first surface to the packaging substrate, providing a first chip, bonding the first chip to the first surface, providing an optical chip and an electrical chip, bonding the optical chip and the electrical chip to form a stacked structure, wherein a side of the optical chip bonded to the electrical chip comprises a first redistribution layer, forming a first connecting terminal on a side of at least part of the first redistribution layer away from the optical chip, bonding the stacked structure to the packaging substrate, wherein the first connecting terminal is bonded to the first surface of the packaging substrate, and the electrical chip is embedded in the groove.

[0012] In some embodiments, a packaging substrate is provided, including forming a second redistribution layer on a first surface, and after the stacked structure is bonded to the packaging substrate, the first chip and the optical chip are electrically connected through the second redistribution layer.

[0013] In some embodiments, an optical chip and an electrical chip are bonded to form a stacked structure, including forming an electrical chip, a second connecting terminal being provided on one side of the electrical chip bonded to the optical chip, forming a first redistribution layer on a wafer, and forming a first connecting terminal on a side of at least a portion of the first redistribution layer away from the wafer, and bonding the second connecting terminal to the first redistribution layer to form a stacked structure.

[0014] In some embodiments, after bonding the stack structure to the packaging substrate, the preparation method further includes injecting underfill between the stack structure and the packaging substrate, and between the first chip and the packaging substrate.

[0015] In some embodiments, after an optical interface is formed on the side of the optical chip away from the first chip and bottom filling is injected between the stacking structure and the packaging substrate, and between the first chip and the packaging substrate, the above-mentioned preparation method also includes setting a heat dissipation cover, the heat dissipation cover at least covers the first chip and the stacking structure, and the heat dissipation cover exposes the optical interface.

[0016] The method for preparing an optical co-packaging structure provided in an embodiment of the present application, the optical chip and the electric chip are bonded through a first rewiring layer to form a 3D integrated stacking structure. By forming a first rewiring layer on the optical chip, a shorter connection distance between the optical chip and the electric chip can be achieved, thereby reducing signal delay and improving signal integrity. The stacking structure is bonded to the first surface of the packaging substrate through the first connecting terminal, which reduces the area occupied by the optical engine on the packaging substrate, thereby reducing the area of ​​the optical co-packaging structure and improving the integration of the optical co-packaging structure. The electric chip is embedded in the groove of the packaging substrate, and the first surface is also bonded to the first chip, so that the height difference between the first chip and the stacking structure relative to the packaging substrate is reduced, which facilitates the subsequent installation of thermal conductive materials and heat dissipation covers to reduce the packaging height of the optical co-packaging structure. In addition, the structure in which the electric chip is embedded in the groove provides a new path for the heat dissipation of the electric chip, which is beneficial to improving its heat dissipation efficiency.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0019] Figure 1 A schematic diagram of an optical co-packaging structure provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of another optical co-packaging structure provided in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of an optical device provided in an embodiment of the present application;

[0022] Figure 4 A flow chart of a method for preparing an optical co-packaging structure provided in an embodiment of the present application;

[0023] Figure 5 to Figure 15A diagram of each step of the preparation method provided in the embodiments of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0025] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0026] In the description of the present application, “plurality” means two or more.

[0027] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0028] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0029] With the explosive growth of data traffic, the demand for data communication solutions with higher speed, lower power consumption and lower latency is increasing day by day. Due to the limitations of Moore's Law, traditional pluggable optical modules face limitations in bandwidth, latency, energy efficiency and speed. Silicon-based optoelectronic technology uses semiconductor manufacturing technology to interconnect optoelectronic components on silicon chips, opening up new possibilities for high-density multi-channel solution design. Therefore, co-packaged optics (CPO) technology came into being.

[0030] Optical co-packaging technology greatly reduces the volume and weight of the optical co-packaging structure by highly integrating silicon photonic chips, that is, electrical chips including electronic integrated circuits (EIC) and optical chips including photonic integrated circuits (PIC), with computing / switch (XPU / Switch) chips in the form of advanced packaging (2.5D / 3D process). It also shortens the connection distance between chips, reduces signal delays, and improves signal transmission speed and bandwidth, achieving low latency, low power consumption and high performance.

[0031] However, there are some problems in the CPO structure in the related technology that need to be solved urgently. For the 2.5D optoelectronic co-packaging structure, the electrical chip and the optical chip are integrated side by side on the interposer, and the packaging structure has a large area. The interposer connects the application-specific integrated circuit (ASIC) chip / switch, the electrical chip and the optical chip through micro-bumps to achieve chip interconnection. The interposer can also connect the optical fiber assembly with the PIC optical fiber block, which requires very high alignment accuracy (1μm) to achieve good optical coupling efficiency.

[0032] For the 3D optoelectronic co-packaging structure, the electrical chip and the optical chip are stacked vertically and interconnected through silicon vias (TSV) or through molding vias (TMV) to form an optical engine. The area of ​​the packaging structure can be further reduced, the distance between the optical engine and the ASIC chip is further reduced, and the signal delay and loss will be further reduced. However, due to the high heat generation of the electrical chip, the 3D stacking of the electrical chip and the optical chip will aggravate the heat dissipation problem and may cause the optoelectronic performance to decrease, especially the temperature drift has a great impact on the optical characteristics. In addition, the height difference between the optical engine and the first chip is large, which is not conducive to the installation of heat dissipation and heat dissipation cover, which may lead to reduced reliability of the packaging structure.

[0033] In order to solve the above problems, the present application proposes an optical co-packaging structure. Figure 1A schematic diagram of an optical co-packaging structure provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the optical co-packaging structure 1 includes a packaging substrate 10 , a first chip 11 and a stacking structure 13 .

[0034] See also Figure 1 The packaging substrate 10 includes a first surface 101 and a second surface 102 that are arranged opposite to each other. The first surface 101 is provided with a groove 103. The groove 103 extends from the first surface 101 into the packaging substrate 10. The first chip 11 is bonded to the first surface 101. Exemplarily, the first chip 11 can be a computing chip or a switching chip. When the first chip 11 is a computing chip, the optical co-packaging structure 1 is an optical computing packaging structure; when the first chip 11 is a switching chip, the optical co-packaging structure 1 is an optical switching packaging structure. The stacking structure 12 includes a bonded optical chip 13 and an electrical chip 14, so the stacking structure 12 can also be called an "optical engine". The embodiment of the present application takes the stacking structure 12 bonded to an optical chip 13 and two electrical chips 14 as an example for explanation.

[0035] Among them, the side of the optical chip 13 bonded to the electrical chip 14 includes a first rewiring layer 15. Exemplarily, the first rewiring layer 15 also includes a micro pad. The electrical chip 14 is bonded to the optical chip 13 through the first rewiring layer 15. The micro pad can be connected to the micro bumps on the surface of the electrical chip 14 for bonding. The 3D stacking and electrical connection of the optical chip 13 and the electrical chip 14 are achieved through thermocompression bonding. In addition, the first rewiring layer 15 can be a single-layer structure or a multi-layer structure.

[0036] Compared with the related art, in which the electrical chip and the optical chip are vertically interconnected through TSV or TMV to form an optical engine, the structure in which the optical chip 13 and the electrical chip 14 are connected through the first redistribution layer 15 in the embodiment of the present application reduces the projection area of ​​the optical co-packaging structure 1 on the plane XY, makes the distance between the optical engine 12 and the first chip 11 smaller, and does not require TSV process, thereby reducing the process difficulty of preparing the optical co-packaging structure 1, improving its process reliability, and thereby improving the reliability of the optical co-packaging structure 1.

[0037] Continue to see Figure 1 A first connection terminal 151 is provided on at least part of the first redistribution layer 15 on a side away from the optical chip 13. Exemplarily, the first connection terminal 151 can be a micro-bump. In the embodiment of the present application, the first connection terminal 151 is provided on a portion of the first redistribution layer 15 that is not connected to the electrical chip 14. The first connection terminal 151 is bonded to the first surface 101 of the packaging substrate 10, and the electrical chip 14 is embedded in the groove 103.

[0038] In the optical co-packaging structure 1 provided in the embodiment of the present application, the optical chip 13 and the electrical chip 14 are bonded through the first rewiring layer 15 to form a 3D integrated stacking structure 12 (optical engine). By setting the first rewiring layer 15 on the optical chip 13, a shorter connection distance between the optical chip 13 and the electrical chip 14 can be achieved, thereby reducing signal delay and improving signal integrity. The stacking structure 12 is bonded to the first surface 101 of the packaging substrate 10 through the first connecting terminal 151, reducing the area occupied by the optical engine on the packaging substrate 10, thereby reducing the area of ​​the optical co-packaging structure 1 and improving the integration of the optical co-packaging structure 1. The electric chip 14 is embedded in the groove 103 of the packaging substrate 10, and the first surface 101 is also bonded to the first chip 11, so that the height difference between the first chip 11 and the stacking structure 12 relative to the packaging substrate 10 is reduced, which is convenient for the subsequent installation of thermal conductive materials and heat dissipation cover to reduce the packaging height of the optical co-packaging structure 1. In addition, the structure in which the electric chip 14 is embedded in the groove 103 provides a new path for the heat dissipation of the electric chip 14, which is beneficial to improving its heat dissipation efficiency.

[0039] In some embodiments, Figure 1 As shown, the first surface 101 is provided with a second rewiring layer 16, and the second rewiring layer 16 can be a single-layer structure or a multi-layer structure. The first chip 11 and the optical chip 13 are electrically connected through the lines on the second rewiring layer 16. Exemplarily, the surface of the first chip 11 bonded to the package substrate 10 is provided with micro-bumps, and the first chip 11 is electrically connected to the second rewiring layer 16 of the package substrate 10 through the micro-bumps. The electrical chip 14 is interconnected with the first chip 11 through the first rewiring layer 15 on the optical chip 13 and the second rewiring layer 16 on the first surface 101 of the package substrate 10, which reduces the propagation distance of the optical signal between the above chips, thereby reducing signal delay and improving signal transmission speed and bandwidth.

[0040] In some embodiments, Figure 1 As shown, the optical chip 13 is formed with an optical interface 131 on the side away from the first chip 11. The optical interface 131 is an optical interface or coupling area on the optical chip 13, which is used to connect to the fiber array unit (Fiber Array Unit, FAU) to realize the input and output of optical signals. In the embodiment of the present application, the optical interface 131 of the optical chip 13 is set on the side, realizing edge coupling, improving coupling efficiency, and ensuring the optoelectronic performance of the optical chip 13.

[0041] The optical packaging structure 1 also includes a heat dissipation cover 17, which at least covers the first chip 11 and the stacking structure 12, and the heat dissipation cover 17 exposes the optical interface 131. In the embodiment of the present application, the heat dissipation cover 17 and the packaging substrate 10 surround the first chip 11 and the stacking structure 12, and only expose the side where the optical interface 131 is located, thereby achieving isolation and protection of the first chip 11 and the stacking structure 12. In addition, the heat dissipation cover 17 has a certain heat dissipation effect, which is conducive to improving the heat conduction speed. Exemplarily, a thermal interface material (TIM) is also provided between the heat dissipation cover 17 and the first chip 11 and the stacking structure 12. The thermal interface material can not only bond the heat dissipation cover 17 and the chip, but also reduce the contact thermal resistance between the heat dissipation cover 17 and the chip, and has a good heat transfer effect.

[0042] For example, Figure 1 As shown, the optical co-packaging structure 1 further includes an underfill 18, which is used to fill the gap between the first chip 11 and the stacking structure 12 and the packaging substrate 10, protect the bonding interface, reduce packaging stress damage, increase its robustness and durability, and thus improve the mechanical strength and service life of the optical co-packaging structure 1. In some embodiments, Figure 2 A schematic diagram of another optical co-packaging structure provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the optical co-packaging structure 1 further includes a connection structure 19 disposed in the packaging substrate 10, and the first chip 11 and the optical chip 13 can be electrically connected not only through the second redistribution layer 16, but also through the connection structure 19. Exemplarily, the connection structure 19 can be a silicon bridge, and the embedding of the silicon bridge improves the wiring density of the packaging substrate 10, increases the propagation path of the electrical signal, thereby reducing signal delay and improving the overall performance of the optical co-packaging structure 1.

[0043] On the other hand, the present application also proposes an optical device, Figure 3 A schematic diagram of an optical device provided in an embodiment of the present application, such as Figure 3 As shown, the optical device 2 includes the optical co-packaging structure 1 mentioned above, and a circuit board 21. In the embodiment of the present application, the optical device 2 includes Figure 1 The optical co-package structure 1 shown is used as an example for explanation. The optical device 2 integrates optical computing technology or optical switching technology and can be an optical computing device or an optical switching interconnection device. For example, when the first chip 11 is a computing chip, the optical device 2 is an optical computing device; when the first chip 11 is a switching chip, the optical device 2 is an optical switching interconnection device.

[0044] like Figure 3As shown, the optical co-packaging structure 1 and the circuit board 21 can be electrically connected through the first solder ball 22, or the micro pads on the second surface 102 of the optical co-packaging structure 1 are exposed, and the optical co-packaging structure 1 and the circuit board 21 are directly electrically connected through the micro pads. Multiple optical co-packaging structures 1 can be integrated on the circuit board 21. The optical interface 131 in the optical chip 13 of the optical co-packaging structure 1 is externally connected to the optical fiber array unit 24. After the electrical signal is processed by the first chip 11, it is transmitted to the optical chip 13. The optical chip 13 converts the electrical signal into an optical signal, and the converted optical signal is transmitted to the external device through the optical fiber array unit 24. A second solder ball 23 is also provided on the side of the circuit board 21 away from the optical co-packaging structure 1. The optical device 2 provided in the embodiment of the present application has an improved overall performance of the optical co-packaging structure 1, so that the reliability of the optical co-packaging structure 1 is improved, thereby also improving the reliability of the optical device 2.

[0045] In yet another aspect, the present application also provides a method for preparing an optical co-packaging structure; Figure 4 A flow chart of a method for preparing an optical co-packaging structure provided in an embodiment of the present application; Figure 5 to Figure 15 The following are the steps of the preparation method provided in the examples of this application. Figure 4 As shown, the preparation method includes the following steps S1 to S4:

[0046] Step S1: Figure 5 As shown, a packaging substrate 10 is provided, and the packaging substrate 10 includes a first surface 101 and a second surface 102 arranged opposite to each other, and then as shown in Figure 6 As shown, a groove 103 is formed on the first surface 101 . Exemplarily, the groove 103 can be formed by laser ablation. The groove 103 extends from the first surface 101 into the packaging substrate 10 .

[0047] In some embodiments, Figure 5 As shown, a second redistribution layer 16 is formed on the first surface 101. The second redistribution layer 16 is a metal layer for redistributing electrical signals. A circuit structure is arranged thereon to conduct electrical signals and achieve higher density signal connection, thereby improving the packaging performance of the packaging structure.

[0048] Step S2: Figure 7 As shown, a first chip 11 is provided. Exemplarily, the first chip 11 can be a computing chip or a switching chip. Then the first chip 11 is bonded to the first surface 101. Exemplarily, the surface of the first chip 11 used for bonding is provided with a micro pad, and the micro pad can be connected to the second redistribution layer 16 by thermocompression bonding to achieve electrical connection.

[0049] Step S3: Figure 8As shown, an optical chip 13 and an electrical chip 14 are provided, and the optical chip 13 and the electrical chip 14 are bonded to form an electrically connected stacking structure 12, wherein the side of the optical chip 13 bonded to the electrical chip 14 includes a first redistribution layer 15, and a first connection terminal 151 is formed on a side of at least a portion of the first redistribution layer 15 away from the optical chip 13.

[0050] In some embodiments, Fig. 9 As shown, the side of the electrical chip 14 formed in the above step S2 for bonding is provided with a second connection terminal 141. Exemplarily, the second connection terminal 141 can be made on the EIC wafer by a bumping process, and then the EIC wafer is cut into separate electrical chips 14, or the electrical chip 14 with the second connection terminal 141 can be directly used. The second connection terminal 141 on the electrical chip 14 can be bonded to the first redistribution layer 15 on the optical chip 13 to form an electrically connected stacked structure (optical engine) 12.

[0051] In some embodiments, Figure 10 to Figure 12 As shown, the process of forming the optical chip 13 in the above step S2 is specifically as follows: Fig.10 As shown, an optical wafer 3 is provided, and the optical wafer 3 includes an optical interface 131, and then Fig.11 As shown, a first rewiring layer 15 is formed on any surface of the optical wafer 3 . Exemplarily, the first rewiring layer 15 also includes micro pads 152 , which are used to bond with the second connection terminals 141 on the electrical chip 14 .

[0052] Exemplarily, to prepare the first rewiring layer 15 and the micro pad 152, it is necessary to first coat a layer of polyimide (PI) film on the surface of the optical wafer 3 to play a role of protection and stress buffering, and then coat a photoresist on the PI layer and perform photolithography, and form the desired pattern through the steps of exposure and development. Then, titanium or copper is sputtered on the surface of the entire optical wafer 3 by physical vapor deposition (PVD) as a seed layer for electroplating, and then photoresist is coated on the seed layer again, and the desired pattern is formed through the steps of exposure and development, and electroplating is performed at the position of the photoresist opening to increase the thickness of the seed layer and ensure the conductivity of the first rewiring layer 15. Finally, the photoresist is removed, and the seed layer covered by the first rewiring layer 15 is removed by wet etching to complete the production of the first rewiring layer 15. By repeating the above steps, a multilayer rewiring layer can be produced.

[0053] Then as Fig.12As shown, a first connection terminal 151 is formed on a side of at least part of the first redistribution layer 15 away from the optical wafer 3, and the first connection terminal 151 is used for subsequent bonding with the package substrate. The first connection terminal 151 is a micro-bump. The process of forming the first connection terminal 151 requires first depositing an isolation layer and a seed layer, then coating a photoresist on the isolation layer, and then exposing and developing to achieve patterning. Next, the micro-bump is electroplated in the patterned area, and then the photoresist is removed, and the excess metal layer is etched away to leave the desired micro-bump structure. Finally, the micro-bump is formed through specific process steps, such as reflow soldering.

[0054] Among them, the side of the optical chip 13 includes an optical interface 131, which can be connected to the optical fiber array unit to realize the input and output of optical signals. The optical interface 131 of the optical chip 13 is set on the side, realizing edge coupling, improving coupling efficiency, and ensuring the optoelectronic performance of the optical chip 13.

[0055] After obtaining the electrical chip 14 and the optical wafer 3 processed as described above, the second connection terminal 141 on the electrical chip 14 is bonded to the first redistribution layer 15 on the optical wafer 3 through die to wafer (D2F) hot compression bonding, and finally the bonded electrical chip 14 and the optical wafer 3 are cut to obtain a plurality of stacked structures 12.

[0056] Step S4: Fig.13 As shown, the stacking structure 12 is bonded to the packaging substrate 10 by flip chip bonding (FC), that is, the first connecting terminal 151 is bonded to the second rewiring layer 16 on the first surface 101 of the packaging substrate 10. In this case, the electrical chip 14 is embedded in the groove 103, and the first chip 11 and the optical chip 13 are electrically connected through the second rewiring layer 16. The electrical chip 14 is interconnected with the first chip 11 through the first rewiring layer 15 on the optical chip 13 and the second rewiring layer 16 of the packaging substrate 10, which reduces the propagation distance of the optical signal between the above chips, thereby reducing signal delay and improving signal transmission speed and bandwidth.

[0057] In the preparation method provided by the embodiment of the present application, the optical chip 13 and the electric chip 14 are bonded through the first rewiring layer 15 to form a 3D integrated stacking structure 12 (optical engine). By forming the first rewiring layer 15 on the optical chip 13, a shorter connection distance between the optical chip 13 and the electric chip 14 can be achieved, thereby reducing signal delay and improving signal integrity. The stacking structure 12 is bonded to the first surface 101 of the packaging substrate 10 through the first connection terminal 151, reducing the area occupied by the optical engine on the packaging substrate 10, thereby reducing the area of ​​the optical co-packaging structure 1 and improving the integration of the optical co-packaging structure 1. The electric chip 14 is embedded in the groove 103 of the packaging substrate 10, and the first surface 101 is also bonded to the first chip 11, so that the height difference between the first chip 11 and the stacking structure 12 is reduced relative to the packaging substrate 10, which is convenient for the subsequent installation of thermal conductive materials and heat dissipation covers to reduce the packaging height of the optical co-packaging structure 1, and the structure in which the electric chip 14 is embedded in the groove 103 provides a new path for the heat dissipation of the electric chip 14, which is conducive to improving its heat dissipation efficiency.

[0058] In some embodiments, Fig.14 As shown, after the stacking structure 12 is bonded to the packaging substrate 10, the preparation method further includes injecting an underfill 18 between the stacking structure 12 and the packaging substrate 10, and between the first chip 11 and the packaging substrate 10. The underfill 18 can fill the gap between the first chip 11 and the stacking structure 12 and the packaging substrate 10, protect the bonding interface, reduce packaging stress damage, increase its robustness and durability, and thus improve the mechanical strength and service life of the optical co-packaging structure 1.

[0059] In some embodiments, after the injection of the underfill 18 is completed, Figure 1 As shown, the preparation method also includes forming a heat dissipation cover 17, which at least covers the first chip 11 and the stacking structure 12, and the heat dissipation cover 17 exposes the optical interface 131. In the embodiment of the present application, the heat dissipation cover 17 and the packaging substrate 10 surround the first chip 11 and the stacking structure 12, and only expose one side where the optical interface 131 is located, thereby achieving isolation and protection of the first chip 11 and the stacking structure 12, and the heat dissipation cover 17 has a certain heat dissipation effect, which is beneficial to improving the heat conduction speed.

[0060] Exemplarily, a thermal interface material (TIM) is also provided between the heat dissipation cover 17 and the first chip 11 and the stacking structure 12. The thermal interface material can not only bond the heat dissipation cover 17 and the chip, but also reduce the contact thermal resistance between the heat dissipation cover 17 and the chip, and has a good heat transfer effect. Fig.15 As shown, ball planting is performed on the second surface 102 to form solder balls 22, and finally the optical co-packaging structure 1 is cut to obtain individual CPO chips.

[0061] In some embodiments, the optical co-packaging structure 1 can be provided with multiple first chips 11, multiple optical chips 13 and multiple electrical chips 14, and a stacking structure 12 formed by vertically stacking multiple optical chips 13 and electrical chips 14. The stacking structure 12 can be arranged around the first chip 11 and interconnected with the first chip 11 through a second redistribution layer 16. The electrical chips 14 in the multiple stacking structures 12 are embedded in multiple grooves 103, providing a more diverse optical co-packaging structure 1.

[0062] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. An optical co-packaging structure, characterized in that: include: A packaging substrate, comprising a first surface and a second surface arranged opposite to each other, wherein the first surface is provided with a groove, and the groove extends from the first surface into the packaging substrate; a first chip bonded to the first surface; A stacked structure includes a bonded optical chip and an electrical chip, wherein a side of the optical chip bonded to the electrical chip includes a first redistribution layer, at least a portion of the first redistribution layer is provided with a first connection terminal on a side away from the optical chip, the first connection terminal is bonded to the first surface of the packaging substrate, and the electrical chip is embedded in the groove.

2. The optical co-packaging structure according to claim 1, characterized in that: The first surface is provided with a second rewiring layer, and the first chip and the optical chip are electrically connected via the second rewiring layer.

3. The optical co-packaging structure according to claim 2, characterized in that: The packaging substrate further includes: A connection structure is provided in the packaging substrate, and the first chip and the optical chip are electrically connected through the connection structure.

4. The optical co-packaging structure according to any one of claims 1, characterized in that: The optical chip is provided with an optical interface on a side away from the first chip; The optical packaging structure further includes: A heat dissipation cover at least covers the first chip and the stacking structure, and the heat dissipation cover exposes the optical interface.

5. An optical device, characterized in that: include: The optical co-packaging structure as claimed in any one of claims 1 to 4; A circuit board, the optical co-packaging structure is electrically connected to the circuit board.

6. A method for preparing an optical co-packaging structure, characterized in that: include: Providing a packaging substrate, the packaging substrate comprising a first surface and a second surface arranged opposite to each other, a groove being formed on the first surface, and the groove extending from the first surface into the packaging substrate; providing a first chip, and bonding the first chip to the first surface; Providing an optical chip and an electrical chip, bonding the optical chip and the electrical chip to form a stacked structure, wherein a side of the optical chip bonded to the electrical chip comprises a first redistribution layer, and a first connection terminal is formed on a side of at least a portion of the first redistribution layer away from the optical chip; The stacking structure is bonded to the packaging substrate, wherein the first connection terminal is bonded to the first surface of the packaging substrate, and the electric chip is embedded in the groove.

7. The preparation method according to claim 6, characterized in that: The packaging substrate is provided, comprising: forming a second redistribution layer on the first surface; After the stacked structure is bonded to the packaging substrate, the first chip and the optical chip are electrically connected through the second redistribution layer.

8. The preparation method according to claim 6, characterized in that: Bonding the optical chip and the electrical chip to form a stacked structure, comprising: forming the electric chip, wherein a second connection terminal is provided on a side of the electric chip bonded to the optical chip; forming the first rewiring layer on a wafer, and forming the first connecting terminal on a side of at least a portion of the first rewiring layer away from the wafer; The second connection terminal is bonded to the first redistribution layer to form a stacked structure.

9. The preparation method according to claim 6, characterized in that: After bonding the stacked structure to the packaging substrate, the preparation method further includes: Underfill injection is performed between the stack structure and the packaging substrate, and between the first chip and the packaging substrate.

10. The preparation method according to claim 9, characterized in that: forming an optical interface on a side of the optical chip away from the first chip; After the underfill is injected between the stacked structure and the packaging substrate, and between the first chip and the packaging substrate, the preparation method further includes: A heat dissipation cover is provided, wherein the heat dissipation cover at least covers the first chip and the stacking structure, and the heat dissipation cover exposes the optical interface.

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