System-in-package structure and preparation method thereof

Abstract

The invention provides a system-in-package structure and a preparation method thereof, relates to the technical field of electronic device package, and aims to at least solve the problem of low heat dissipation efficiency of an electronic device in the prior art. The system-in-package structure comprises an upper copper substrate; the heat-conducting copper layer is embedded into the upper copper substrate; the first chip is arranged on the upper copper substrate; the second chip is arranged on the heat conduction copper layer, the second chip and the first chip are arranged in a spaced mode in the first direction, and the power of the second chip during working is larger than that of the first chip during working; the heat conduction copper layer comprises a heat absorption section and a heat dissipation section, the heat absorption section is connected with the second chip, and the heat dissipation section is far away from the second chip. The system-in-package structure can effectively guide the heat of an overheated area, ensures that the heat generated by the main chip is quickly dispersed to other areas, and promotes the uniform distribution of temperature.

Description

Technical Field

[0001] The present application relates to the technical field of electronic device packaging, and in particular to a system-level packaging structure and a preparation method thereof. Background Art

[0002] As electronic devices develop towards high performance, miniaturization and multifunctionality, system-level packaging technology has attracted more and more attention. Traditional packaging methods have problems such as insufficient heat dissipation performance and difficult thermal management, especially in chips with high integration and high power consumption. Traditional heat dissipation methods can no longer meet the needs of modern system-level packaging. Therefore, it is urgent to design a system-level packaging structure with high heat dissipation efficiency to effectively reduce the operating temperature of electronic devices and ensure the long-term reliability of electronic devices. Summary of the invention

[0003] The present application aims to at least solve the problem of low heat dissipation efficiency of electronic devices in the prior art or related art.

[0004] To this end, a first aspect of the present application is to propose a system-level packaging structure.

[0005] A second aspect of the present application is to provide a method for preparing a system-level packaging structure.

[0006] The embodiment of the first aspect of the present application provides a system-level packaging structure, comprising: a substrate, comprising an upper copper substrate and a lower copper substrate; a heat-conducting copper layer, embedded in the upper copper substrate; a first chip, arranged on the upper copper substrate; a second chip, arranged on the heat-conducting copper layer, and spaced apart from the first chip along a first direction, the power of the second chip when working is greater than the power of the first chip when working; the heat-conducting copper layer comprises a heat-absorbing section and a heat-dissipating section, the heat-absorbing section is connected to the second chip, the heat-dissipating section is arranged away from the second chip, the heat-conducting copper layer is a hollow structure, a heat-absorbing cavity is arranged in the heat-absorbing section, a heat-dissipating cavity is arranged in the heat-dissipating section, and the heat-absorbing cavity is connected to the heat-dissipating cavity; a plurality of first copper pillars, connected between the heat-absorbing section and the lower copper substrate, and the plurality of first copper pillars are spaced apart along the first direction; a plurality of second copper pillars, It is connected between the heat dissipation section and the lower copper substrate, and a plurality of second copper pillars are arranged at intervals along the first direction; a plurality of heat-absorbing copper pillars are arranged at intervals along the first direction in the heat-absorbing cavity, and a first conductive hole is arranged on the heat-absorbing copper pillars; a plurality of heat-conducting copper pillars are arranged at intervals along the first direction in the heat dissipation cavity, and a second conductive hole is arranged on the heat-conducting copper pillars; a heat-conducting liquid is stored in the heat-absorbing cavity, and when the second chip is working, the heat-conducting liquid can absorb heat, and vaporize into a gaseous state, and flow into the heat dissipation cavity, and liquefy into a liquid state in the heat dissipation cavity; a resistor and a capacitor are arranged on a side of the upper copper substrate close to the second chip, and are located between the first chip and the second chip; a plurality of solder pads are arranged on a side of the lower copper substrate away from the second chip, and a plurality of solder pads are arranged at intervals along the first direction.

[0007] The system-level packaging structure provided by the present invention has the following characteristics: when the temperature of the second chip (i.e., the main chip) increases, the heat generated by the second chip can be transferred in two directions. A portion of the heat can be transferred to the first copper column through the heat absorption section of the heat-conducting copper layer, and then transferred to the lower copper substrate, thereby realizing a portion of the heat dissipation. The other portion of the heat can be absorbed by the heat-conducting liquid in the heat absorption cavity, and then transferred from the heat absorption cavity to the heat dissipation cavity, thereby completing the heat release in the heat dissipation cavity. In addition, some of the heat can be transferred to multiple second copper columns through the heat dissipation section, and then transferred to the lower copper substrate. This structure can effectively guide the heat in the overheated area, ensure that the heat generated by the main chip is quickly dispersed to other areas, and promote uniform temperature distribution. In addition, since the heat-conducting copper layer, the first copper column and the second copper column are all embedded in the copper substrate, that is, arranged between the upper copper substrate and the lower copper substrate, the increase in the thickness of the system-level packaging structure can be avoided, which is in line with the development of miniaturization.

[0008] In addition, the system-level package structure also includes a plurality of pads, which are arranged on a side of the lower copper substrate away from the second chip, and the plurality of pads are arranged at intervals along the first direction. On the one hand, this design can realize the fixation of the system-level package structure, and the system-level package structure can be welded to a fixed position through the pads. On the other hand, since the plurality of pads are arranged at intervals along the first direction, the heat dissipation of the lower copper substrate will not be affected, thereby realizing bottom heat dissipation and improving heat dissipation efficiency.

[0009] In some embodiments, optionally, the system-level packaging structure further includes a pump body, which is disposed in the heat dissipation cavity and is used to transport the liquid heat-conducting liquid in the heat dissipation cavity to the heat absorption cavity.

[0010] In this embodiment, a pump body, which may be a micro pump, is arranged in the heat dissipation cavity, so that the liquid heat-conducting liquid in the heat dissipation cavity can be transported to the heat-absorbing cavity, thereby realizing the circulation heat absorption of the heat-conducting liquid.

[0011] In some embodiments, optionally, the system-level packaging structure also includes a solder pad connected between the first copper column and the heat absorption section, and the solder pad is connected between the second copper column and the heat dissipation section. In this way, during the installation process, the first copper column and the second copper column can be preferentially soldered to the solder pad, and then the first copper column and the second copper column are inserted into the gap of the substrate, and finally the solder pad and the thermal conductive copper layer are soldered together, thereby improving the installation efficiency.

[0012] In some embodiments, optionally, the first chip is connected to the upper copper substrate by welding.

[0013] In this embodiment, the first chip is connected to the upper copper substrate by welding, that is, a chip welding layer is provided between the first chip and the upper copper substrate, thereby ensuring the connection stability between the first chip and the upper copper substrate.

[0014] In some embodiments, optionally, the second chip and the thermal conductive copper layer are connected by welding.

[0015] In this embodiment, the second chip is connected to the thermally conductive copper layer by welding, that is, a chip welding layer is provided between the first chip and the upper copper substrate, thereby ensuring the connection stability between the second chip and the thermally conductive copper layer.

[0016] In some embodiments, optionally, the system-level packaging structure further includes: a third welding layer, disposed between the plurality of first copper pillars and the heat absorption section.

[0017] In this embodiment, the system-level packaging structure further includes a third welding layer, which is disposed between the plurality of first copper pillars and the heat absorption section, that is, the plurality of first copper pillars and the heat absorption section are welded and connected, thereby improving the connection strength between the two.

[0018] In some embodiments, optionally, the system-level package structure further includes a fourth welding layer disposed between the plurality of second copper pillars and the heat dissipation segment.

[0019] In this embodiment, the system-level packaging structure further includes a fourth welding layer, which is disposed between the plurality of second copper pillars and the heat dissipation segment, that is, the plurality of second copper pillars and the heat dissipation segment are welded and connected, thereby improving the connection strength between the two.

[0020] In some embodiments, optionally, the number of the first copper pillars is greater than or equal to 4 and less than or equal to 8. For example, the number may be 4, 6 or 8.

[0021] In some embodiments, optionally, the number of the second copper pillars is greater than or equal to 4 and less than or equal to 8. For example, the number may be 4, 6 or 8.

[0022] In some embodiments, optionally, the number of the heat absorbing copper pillars is greater than or equal to 4 and less than or equal to 8. For example, the number may be 4, 6 or 8.

[0023] In some embodiments, optionally, the number of the thermally conductive copper pillars is greater than or equal to 4 and less than or equal to 8. For example, the number may be 4, 6 or 8.

[0024] In some embodiments, optionally, the number of heat absorption segments is one, and the number of heat dissipation segments is greater than or equal to 2 and less than or equal to 4, for example 3, so that the heat absorbed by the heat absorption segment can be dissipated through multiple heat dissipation segments, thereby improving the heat dissipation efficiency.

[0025] In some embodiments, optionally, the system-level packaging structure further includes a heat dissipation fan, which is installed on the thermally conductive copper layer and arranged corresponding to the heat dissipation section.

[0026] In this embodiment, the system-level packaging structure also includes a heat dissipation fan installed on the thermally conductive copper layer and arranged corresponding to the heat dissipation section, so that the heat on the thermally conductive copper layer can be further removed by the heat dissipation fan, thereby improving the heat dissipation effect.

[0027] In some embodiments, optionally, the number of the resistor and the capacitor is two, and the two resistors and the capacitors are spaced apart along the first direction.

[0028] In this embodiment, there are two resistors and capacitors, which are spaced apart along the first direction. The resistors and capacitors can be combined into a low-pass, high-pass or band-pass filter.

[0029] In some embodiments, optionally, the heat dissipation section is disposed close to the first chip.

[0030] In this embodiment, the heat dissipation section is arranged close to the first chip, so that the heat of the high-power chip can be dispersed to the vicinity of the low-power chip, thereby achieving heat uniformity without increasing the overall volume of the system-level packaging structure.

[0031] In some embodiments, optionally, the resistor and capacitor are connected to the upper copper substrate by welding.

[0032] In this embodiment, the resistors and capacitors are connected to the upper copper substrate by welding, thereby improving the stability of the resistors and capacitors.

[0033] In some embodiments, optionally, on each heat-absorbing copper pillar, the number of first vias is greater than or equal to 3 and less than or equal to 8. For example, the number of first vias may be 3, 5 or 8, thereby increasing the heat exchange rate.

[0034] In some embodiments, optionally, on each heat-conducting copper pillar, the number of the second vias is greater than or equal to 3 and less than or equal to 8. For example, the number may be 3, 5 or 8, thereby increasing the heat exchange rate.

[0035] The second aspect of the present invention provides a method for preparing a system-level packaging structure, the system-level packaging structure is a system-level packaging structure as any one of the technical solutions of the first aspect of the present invention, the method for preparing the system-level packaging structure includes: obtaining a substrate, the substrate including an upper copper substrate, a lower copper substrate and a support plate located between the upper copper substrate and the lower copper substrate; punching the substrate to obtain a plurality of first mounting holes and a plurality of second mounting holes, installing a plurality of first copper pillars in the first mounting holes, and installing a plurality of second copper pillars in the second mounting holes; slotting the substrate at positions corresponding to the thermally conductive copper layer to obtain mounting grooves, and installing the thermally conductive copper layer into the mounting grooves; welding a pad at the bottom of the mounting groove, and welding the thermally conductive copper layer to the pad together; installing a heat-absorbing copper pillar in a heat-absorbing cavity, and installing a heat-conducting copper pillar in a heat-dissipating cavity; and using sintering technology to install a first chip, a second chip, and a resistor and a capacitor on the substrate.

[0036] Since the system-level packaging structure prepared by the preparation method of the present invention is the system-level packaging structure of any technical solution of the first aspect of the present invention, it has all the beneficial effects of the system-level packaging structure of any technical solution of the first aspect of the present invention.

[0037] Additional aspects and advantages of the present application will become apparent in the following description or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0039] Figure 1 One of the structural schematic diagrams of the system-level packaging structure of an embodiment of the present invention is shown;

[0040] Figure 2 A second structural schematic diagram showing the system-level packaging structure of an embodiment of the present invention;

[0041] Figure 3 A third structural schematic diagram showing the system-level packaging structure of an embodiment of the present invention;

[0042] Figure 4 A fourth structural diagram of the system-level packaging structure of an embodiment of the present invention is shown;

[0043] Figure 5 A fifth structural diagram showing a system-level packaging structure according to an embodiment of the present invention;

[0044] Figure 6 A sixth structural diagram showing a system-level packaging structure according to an embodiment of the present invention;

[0045] Figure 7 One of the structural schematic diagrams of the heat-conducting copper layer of an embodiment of the present invention is shown;

[0046] Figure 8 The second structural schematic diagram of the heat-conducting copper layer of an embodiment of the present invention is shown;

[0047] Fig. 9 The third structural schematic diagram of the thermal conductive copper layer of an embodiment of the present invention is shown;

[0048] Fig.10 A fourth structural schematic diagram of the heat-conducting copper layer of an embodiment of the present invention is shown;

[0049] Fig.11 One of the schematic diagrams showing a method for preparing a system-level packaging structure according to an embodiment of the present invention;

[0050] Fig.12The second flowchart of the method for preparing the system-level packaging structure according to the embodiment of the present invention is shown.

[0051] Figures 1 to 10 The corresponding relationship between the reference numerals and component names in the figure is:

[0052] 1 system-level packaging structure, 2 thermal conductive copper layer, 22 heat absorption section, 23 heat absorption cavity, 24 heat dissipation section, 25 heat dissipation cavity, 32 first chip, 34 second chip, 36 resistors and capacitors, 4 substrate, 42 upper copper substrate, 44 lower copper substrate, 46 supporting substrate, 52 first copper pillar, 54 second copper pillar, 62 heat absorption copper pillar, 64 thermal conductive copper pillar, 66 first via, 68 second via, 72 thermal conductive liquid, 8 pad, 92 third welding layer, 94 fourth welding layer. DETAILED DESCRIPTION

[0053] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0054] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present application is not limited to the specific embodiments disclosed below.

[0055] like Figure 1 , Figure 2 and Fig.10As shown, an embodiment of the first aspect of the present application provides a system-level packaging structure 1, including a substrate 4, the substrate 4 includes an upper copper substrate 42 and a lower copper substrate 44; a thermally conductive copper layer 2 is embedded in the upper copper substrate 42; a first chip 32 is arranged on the upper copper substrate 42; a second chip 34 is arranged on the thermally conductive copper layer 2 and is spaced apart from the first chip 32 along a first direction, and the power of the second chip 34 when working is greater than the power of the first chip 32 when working; the thermally conductive copper layer 2 includes a heat absorbing section 22 and The heat dissipation section 24, the heat absorption section 22 is connected to the second chip 34, the heat dissipation section 24 is arranged away from the second chip 34, the heat conductive copper layer 2 is a hollow structure, a heat absorption cavity 23 is arranged in the heat absorption section 22, and a heat dissipation cavity 25 is arranged in the heat dissipation section 24, and the heat absorption cavity 23 is connected to the heat dissipation cavity 25; the lower copper substrate 44 is arranged on the side of the heat conductive copper layer 2 away from the second chip 34, and a gap is arranged between the lower copper substrate 44 and the heat conductive copper layer 2; a plurality of first copper pillars 52 are connected between the heat absorption section 22 and the lower copper substrate 44, and a plurality of The first copper pillars 52 are arranged at intervals along the first direction; a plurality of second copper pillars 54 are connected between the heat dissipation section 24 and the lower copper substrate 44, and the plurality of second copper pillars 54 are arranged at intervals along the first direction; a plurality of heat-absorbing copper pillars 62 are arranged at intervals in the heat-absorbing cavity 23 along the first direction, and the heat-absorbing copper pillars 62 are provided with first conductive holes 66; a plurality of heat-conducting copper pillars 64 are arranged at intervals in the heat dissipation cavity 25 along the first direction, and the heat-conducting copper pillars 64 are provided with second conductive holes 68; a heat-conducting liquid 72 is stored in the heat-absorbing cavity 23, and when the second chip 34 is working, the heat-conducting liquid 72 can absorb heat, and vaporize into a gaseous state, and flow into the heat dissipation cavity 25, and liquefy into a liquid state in the heat dissipation cavity 25; a resistor and a capacitor 36 are arranged on a side of the upper copper substrate 42 close to the second chip 34, and are located between the first chip 32 and the second chip 34; a plurality of pads 8 are arranged on a side of the lower copper substrate 44 away from the second chip 34, and the plurality of pads 8 are arranged at intervals along the first direction.

[0056] In the system-level packaging structure 1 provided by the present invention, when the temperature of the second chip 34 (i.e., the main chip) increases, the heat generated by the second chip 34 can be transferred in two directions. A part of the heat can be transferred to the first copper pillar 52 through the heat absorption section 22 of the heat-conducting copper layer 2, and then transferred to the lower copper substrate 44, thereby realizing a part of the heat dissipation, and another part of the heat can be absorbed by the heat-conducting liquid 72 in the heat absorption cavity 23, and then transferred from the heat absorption cavity 23 to the heat dissipation cavity 25, thereby completing the heat release in the heat dissipation cavity 25. In addition, some of the heat can be transferred to the plurality of second copper pillars 54 through the heat dissipation section 24, and then transferred to the lower copper substrate 44. This structure can effectively guide the heat in the overheating area, ensure that the heat generated by the main chip is quickly dispersed to other areas, and promote uniform temperature distribution. In addition, since the heat-conducting copper layer 2, the first copper pillar 52 and the second copper pillar 54 are all embedded in the copper substrate, that is, arranged between the upper copper substrate 42 and the lower copper substrate 44, the increase in the thickness of the system-level packaging structure 1 can be avoided, which is in line with the development of miniaturization.

[0057] In addition, the system-level package structure 1 further includes a plurality of pads 8, which are disposed on a side of the lower copper substrate 44 away from the second chip 34, and the plurality of pads 8 are spaced apart along the first direction. This design can, on the one hand, realize the fixation of the system-level package structure 1, and the system-level package structure 1 can be welded to a fixed position through the pads 8. On the other hand, since the plurality of pads 8 are spaced apart along the first direction, the heat dissipation of the lower copper substrate 44 is not affected, thereby realizing the bottom heat dissipation and improving the heat dissipation efficiency.

[0058] In some embodiments, optionally, the system-level packaging structure 1 further includes a pump body, which is disposed in the heat dissipation cavity 25 and is used to transport the liquid heat-conducting liquid 72 in the heat dissipation cavity 25 to the heat absorption cavity 23 .

[0059] In this embodiment, a pump body, which may be a micro pump, is provided in the heat dissipation cavity 25 , so that the liquid heat-conducting liquid 72 in the heat dissipation cavity 25 can be transported to the heat absorption cavity 23 , thereby realizing the circulation heat absorption of the heat-conducting liquid 72 .

[0060] In some embodiments, optionally, the system-level packaging structure 1 also includes a solder pad 8 connected between the first copper pillar 52 and the heat absorption section 22, and the solder pad 8 is connected between the second copper pillar 54 and the heat dissipation section 24. In this way, during the installation process, the first copper pillar 52 and the second copper pillar 54 can be preferentially soldered to the solder pad 8, and then the first copper pillar 52 and the second copper pillar 54 can be inserted into the gap of the substrate, and finally the solder pad 8 and the thermal conductive copper layer 2 are soldered together, thereby improving the installation efficiency.

[0061] In some embodiments, optionally, the first chip 32 and the upper copper substrate 42 are connected by welding.

[0062] In this embodiment, the first chip 32 and the upper copper substrate 42 are connected by welding, that is, a chip welding layer is provided between the first chip 32 and the upper copper substrate 42, so as to ensure the connection stability between the first chip 32 and the upper copper substrate 42.

[0063] In some embodiments, optionally, the second chip 34 and the thermal conductive copper layer 2 are connected by welding.

[0064] In this embodiment, the second chip 34 is connected to the thermally conductive copper layer 2 by welding, that is, a chip welding layer is provided between the first chip 32 and the upper copper substrate 42 , thereby ensuring the connection stability between the second chip 34 and the thermally conductive copper layer 2 .

[0065] In some embodiments, optionally, the system-level package structure 1 further includes: a third welding layer 92 disposed between the plurality of first copper pillars 52 and the heat absorption section 22 .

[0066] In this embodiment, the system-level packaging structure 1 further includes a third welding layer 92 disposed between the plurality of first copper pillars 52 and the heat absorption section 22 , that is, the plurality of first copper pillars 52 and the heat absorption section 22 are welded and connected, thereby improving the connection strength between the two.

[0067] In some embodiments, optionally, the system-level package structure 1 further includes a fourth welding layer 94 disposed between the plurality of second copper pillars 54 and the heat dissipation segment 24 .

[0068] In this embodiment, the system-level packaging structure 1 further includes a fourth welding layer 94 disposed between the plurality of second copper pillars 54 and the heat dissipation segment 24 , that is, the plurality of second copper pillars 54 and the heat dissipation segment 24 are welded and connected, thereby improving the connection strength between the two.

[0069] In some embodiments, optionally, the number of the first copper pillars 52 is greater than or equal to 4 and less than or equal to 8. For example, the number may be 4, 6 or 8.

[0070] In some embodiments, optionally, the number of the second copper pillars 54 is greater than or equal to 4 and less than or equal to 8. For example, the number may be 4, 6 or 8.

[0071] In some embodiments, optionally, the number of the heat absorbing copper pillars 62 is greater than or equal to 4 and less than or equal to 8. For example, the number may be 4, 6 or 8.

[0072] In some embodiments, optionally, the number of the thermally conductive copper pillars 64 is greater than or equal to 4 and less than or equal to 8. For example, the number may be 4, 6, or 8.

[0073] In some embodiments, optionally, Figure 3 and Figure 4As shown, the thermal conductive copper layer 2 may also be a solid structure, that is, no heat absorption cavity 23 and heat dissipation cavity 25 are provided. Figure 5 and Figure 6 The structure shown does not include the heat dissipation section 24 .

[0074] In some embodiments, optionally, Figure 7 , Figure 8 and Fig. 9 As shown, the number of the heat absorbing section 22 is one, and the number of the heat dissipating sections 24 is greater than or equal to 2 and less than or equal to 4, for example, 3, so that the heat absorbed by the heat absorbing section 22 can be dissipated through multiple heat dissipating sections 24, thereby improving the heat dissipation efficiency.

[0075] In some embodiments, optionally, the system-level packaging structure 1 further includes a heat dissipation fan, which is installed on the thermal conductive copper layer 2 and is disposed corresponding to the heat dissipation section 24 .

[0076] In this embodiment, the system-level packaging structure 1 also includes a heat dissipation fan installed on the thermally conductive copper layer 2 and arranged corresponding to the heat dissipation section 24, so that the heat dissipation fan can further remove the heat on the thermally conductive copper layer 2, thereby improving the heat dissipation effect.

[0077] In some embodiments, optionally, the number of the resistor and capacitor 36 is two, and the two resistors and capacitors 36 are arranged at intervals along the first direction.

[0078] In this embodiment, there are two resistors and capacitors 36 , which are spaced apart along the first direction. The resistors and capacitors can be combined to form a low-pass, high-pass or band-pass filter.

[0079] In some embodiments, optionally, the heat dissipation segment 24 is disposed close to the first chip 32 .

[0080] In this embodiment, the heat dissipation section 24 is disposed close to the first chip 32 , so that the heat of the high-power chip can be dispersed to the vicinity of the low-power chip, thereby achieving heat uniformity without increasing the overall volume of the system-level packaging structure 1 .

[0081] In some embodiments, optionally, the resistor and capacitor 36 are connected to the upper copper substrate 42 by welding.

[0082] In this embodiment, the resistor and capacitor 36 are connected to the upper copper substrate 42 by welding, thereby improving the stability of the resistor and capacitor 36 .

[0083] In some embodiments, optionally, the system-level packaging structure 1 also includes a supporting substrate 46 connected between the upper copper substrate 42 and the lower copper substrate 44. The supporting substrate 46, the upper copper substrate 42 and the lower copper substrate 44 together constitute the substrate of the system-level packaging structure 1. The supporting substrate 46 is composed of a core layer (i.e., a supporting layer) and a semi-cured layer, so that the semi-cured layer can be cured after absorbing heat, which not only takes away part of the heat, but also improves the supporting strength on the other hand.

[0084] In some embodiments, optionally, on each heat-absorbing copper pillar 62, the number of the first vias 66 is greater than or equal to 3 and less than or equal to 8. For example, the number may be 3, 5 or 8, thereby increasing the heat exchange rate.

[0085] In some embodiments, optionally, on each heat-conducting copper pillar 64, the number of the second vias 68 is greater than or equal to 3 and less than or equal to 8. For example, the number may be 3, 5 or 8, thereby increasing the heat exchange rate.

[0086] like Fig.11 As shown, the second aspect of the present invention provides a method for preparing a system-level packaging structure, the system-level packaging structure is a system-level packaging structure as in any technical solution of the first aspect of the present invention, and the method for preparing the system-level packaging structure includes:

[0087] S102: Obtain a substrate, where the substrate includes an upper copper substrate, a lower copper substrate, and a support plate located between the upper copper substrate and the lower copper substrate;

[0088] S104: punching the substrate to obtain a plurality of first mounting holes and a plurality of second mounting holes, installing a plurality of first copper pillars in the first mounting holes, and installing a plurality of second copper pillars in the second mounting holes;

[0089] S106: performing a groove processing on the substrate at a position corresponding to the thermal conductive copper layer to obtain a mounting groove, and installing the thermal conductive copper layer into the mounting groove;

[0090] S108: welding a pad at the bottom of the mounting groove, and welding the thermal conductive copper layer and the pad together;

[0091] S110: Install a heat-absorbing copper column in the heat-absorbing cavity, and install a heat-conducting copper column in the heat-dissipating cavity;

[0092] S112: Using sintering technology to mount the first chip, the second chip, and the resistors and capacitors on the substrate.

[0093] Since the system-level packaging structure prepared by the preparation method of the present invention is the system-level packaging structure of any technical solution of the first aspect of the present invention, it has all the beneficial effects of the system-level packaging structure of any technical solution of the first aspect of the present invention.

[0094] Another embodiment of the present invention provides a system-level packaging structure, which mainly includes the following three solutions:

[0095] Solution 1: Thermal conduction method of encapsulating a single thick copper chip locally

[0096] With the rapid development of electronic devices towards high performance and miniaturization, the application scope of system-in-package (SiP) technology is becoming increasingly wide. However, the challenges faced by traditional packaging substrates in the field of heat dissipation are becoming more and more significant, mainly manifested in the two major problems of high thermal resistance and limited heat dissipation area. Due to the relatively low thermal conductivity of traditional substrates and plastic packaging materials, the heat generated by the chip is difficult to be efficiently transferred to the external environment, making it difficult to effectively control the chip temperature under high-load operation. In addition, design limitations often lead to insufficient heat dissipation area, and the integration of the heat sink and the overall structure is not high, further exacerbating the risk of heat accumulation.

[0097] like Figure 5 and Figure 6 As shown, in order to break through these heat dissipation bottlenecks, the present scheme proposes an innovative solution, which is to embed a local thick copper layer (i.e., the thermally conductive copper layer 2) in the bottom substrate of the power chip (i.e., the second chip 34). This design enables the heat generated by the chip to be quickly transferred to the thick copper layer, thereby greatly improving the thermal conductivity. Furthermore, by designing an array of copper-clad through holes or copper pillars (i.e., the first copper pillars 52) structure at the bottom of the thick copper layer, the thick copper layer can efficiently guide the heat to the copper layer under the substrate, thereby constructing an efficient and fast heat conduction path. Combined with the ingenious heat dissipation channel design, the heat can be further quickly transferred to the PCB (Printed Circuit Board) board (printed circuit board) with a larger heat dissipation area, thereby significantly improving the overall heat dissipation performance.

[0098] Solution 2: Encapsulate local chip thick copper fan-out heat dissipation method

[0099] In a system-level package, multiple chips are integrated, and their heat release is significantly different. The main chip (i.e., the second chip 34) usually generates most of the heat, while the other chips (i.e., the first chip 32) generate relatively less heat. This uneven distribution of heat will affect the performance of the chip and may cause thermal reliability problems.

[0100] For this reason, Figure 3 and Figure 4As shown in the figure, based on the single thick copper heat conduction structure of scheme 1, this scheme designs at least one thick copper fan-out heat dissipation component as a heat conduction channel. The fan-out structure can effectively guide the heat in the overheating area, ensure that the heat generated by the main chip is quickly dispersed to other areas, reduce the formation of hot spots, and promote uniform temperature distribution. At the same time, the increase in the number of heat dissipation copper-clad holes and copper pillars at the bottom of the thick copper on the substrate further accelerates the conduction of heat generated by the chip to the lower surface of the substrate, thereby significantly improving the overall heat dissipation effect.

[0101] Solution 3: Fan-out heat dissipation in the VC temperature chamber of the local chip package

[0102] like Figure 1 and Figure 2 As shown, based on Scheme 2, this scheme replaces the thick copper fan-out heat conduction structure with a VC (Vapor Chambers, air cavity) temperature-averaging cavity fan-out heat conduction structure. Each VC cavity is provided with an array of copper pillars (i.e., heat-absorbing copper pillars 62) to provide support for the cavity while improving the heat dissipation effect. The VC cavity is filled with a low-boiling-point working liquid, which is easy to evaporate at a lower temperature and can quickly absorb the heat generated by the surrounding area. When the temperature of the main chip rises, the working liquid in the cavity evaporates into gas, and the vapor then migrates to the cooling area through the temperature-averaging cavity. In the cooling area (i.e., the heat dissipation cavity 25), the vapor condenses into liquid and releases heat. This process forms an efficient heat conduction cycle, ensuring that the heat is evenly distributed in the cavity, avoiding local overheating, and maintaining a stable temperature in multiple areas. This design ensures that the chip still has excellent performance and stability when running at high load, thereby significantly improving the overall heat dissipation effect.

[0103] like Fig.12 As shown, another embodiment of the present invention provides a method for preparing a system-level packaging structure, which specifically includes the following steps:

[0104] S202: Prepare a substrate.

[0105] Specifically, a required packaging substrate is obtained, which is composed of a core layer, a plurality of copper layers and a prepreg layer.

[0106] S204: Drilling and electroplating.

[0107] Specifically, precise array holes are drilled on the substrate, and copper plating is performed after drilling to ensure that heat is conducted to the copper layer under the substrate.

[0108] S206: slotting process.

[0109] Specifically, grooves are made on the substrate at locations where thick copper needs to be embedded.

[0110] S208: Thick copper / fan-out thick copper / fan-out VC embedded substrate.

[0111] Specifically, it can be laminated or welded. Lamination means laminating the slotted substrate and the copper block to form a heat dissipation substrate with excellent thermal conductivity. Welding means setting a pad at the bottom of the substrate slot and welding the processed copper block to the substrate, which can achieve a more solid connection.

[0112] S210: Chip fixing.

[0113] Specifically, the bare chip is firmly fixed to the substrate using sintering technology (sintering copper / silver). This method not only improves the thermal contact between the chip and the substrate, but also effectively improves the heat dissipation efficiency, thereby ensuring the stability of the chip under high-performance operation.

[0114] The present invention provides a local chip thick copper fan-out (Fan-out) heat conduction method of a system-level package device, so as to effectively improve the heat dissipation performance of the system-level package device.

[0115] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0116] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A system-level packaging structure, characterized in that: include: A substrate, comprising an upper copper substrate and a lower copper substrate; A thermally conductive copper layer is embedded in the upper copper substrate; A first chip is disposed on the upper copper substrate; A second chip is disposed on the thermally conductive copper layer and is spaced apart from the first chip along a first direction, the power of the second chip when in operation is greater than the power of the first chip when in operation; the thermally conductive copper layer comprises a heat absorbing section and a heat dissipating section, the heat absorbing section is connected to the second chip, the heat dissipating section is arranged away from the second chip, a heat absorbing cavity is arranged in the heat absorbing section, a heat dissipating cavity is arranged in the heat dissipating section, and the heat absorbing cavity is communicated with the heat dissipating cavity; A plurality of first copper pillars are connected between the heat absorption section and the lower copper substrate, and the plurality of first copper pillars are spaced apart along the first direction; A plurality of second copper pillars are connected between the heat dissipation section and the lower copper substrate, and the plurality of second copper pillars are spaced apart along the first direction; A plurality of heat-absorbing copper pillars, wherein the plurality of heat-absorbing copper pillars are arranged in the heat-absorbing cavity at intervals along the first direction, and the heat-absorbing copper pillars are provided with first conducting holes; A plurality of heat-conducting copper pillars are arranged in the heat dissipation cavity at intervals along the first direction, and a second conducting hole is arranged on the heat-conducting copper pillars; A heat-conducting liquid is stored in the heat-absorbing cavity. When the second chip is working, the heat-conducting liquid can absorb heat, vaporize into a gaseous state, flow into the heat-dissipating cavity, and liquefy into a liquid state in the heat-dissipating cavity. Resistors and capacitors are arranged on a side of the upper copper substrate close to the second chip and between the first chip and the second chip; A plurality of pads are arranged on a side of the lower copper substrate away from the second chip, and the plurality of pads are arranged at intervals along the first direction; Wherein, the first chip is connected to the upper copper substrate by welding.

2. The system-level packaging structure according to claim 1, characterized in that: The second chip is connected to the heat-conducting copper layer by welding.

3. The system-level packaging structure according to claim 1, characterized in that: Also includes: A third welding layer is provided between the first copper pillars and the heat absorbing section; and / or The fourth welding layer is arranged between the plurality of the second copper pillars and the heat dissipation section.

4. The system-level packaging structure according to claim 1, characterized in that: The number of the first copper pillars is greater than or equal to 4 and less than or equal to 8; and / or The number of the second copper pillars is greater than or equal to 4 and less than or equal to 8; and / or The number of the heat-absorbing copper pillars is greater than or equal to 4 and less than or equal to 8; and / or The number of the thermally conductive copper pillars is greater than or equal to 4 and less than or equal to 8.

5. The system-level packaging structure according to claim 1, characterized in that: The number of the heat absorbing sections is one, and the number of the heat dissipating sections is greater than or equal to 2 and less than or equal to 4.

6. The system-level packaging structure according to claim 1, characterized in that: The number of the resistors and capacitors is two, and the two resistors and capacitors are spaced apart along the first direction.

7. The system-level packaging structure according to claim 1, characterized in that: The heat dissipation section is arranged close to the first chip.

8. The system-level packaging structure according to claim 1, characterized in that: The resistor and capacitor are connected to the upper copper substrate by welding.

9. The system-level packaging structure according to claim 1, characterized in that: On each of the heat-absorbing copper pillars, the number of the first conductive holes is greater than or equal to 3 and less than or equal to 8; and / or On each of the thermally conductive copper pillars, the number of the second conductive holes is greater than or equal to 3 and less than or equal to 8.

10. A method for preparing a system-level packaging structure, characterized in that: The system-level packaging structure is a system-level packaging structure as claimed in any one of claims 1 to 9, and a method for preparing the system-level packaging structure comprises: Obtaining a substrate, wherein the substrate comprises the upper copper substrate, the lower copper substrate, and a support plate located between the upper copper substrate and the lower copper substrate; Punching the substrate to obtain a plurality of first mounting holes and a plurality of second mounting holes, installing a plurality of the first copper pillars in the first mounting holes, and installing a plurality of the second copper pillars in the second mounting holes; Performing a groove processing on the substrate at a position corresponding to the thermal conductive copper layer to obtain a mounting groove, and installing the thermal conductive copper layer into the mounting groove; Welding a pad at the bottom of the mounting groove, and welding the thermal conductive copper layer and the pad together; The heat absorbing copper column is installed in the heat absorbing cavity, and the heat conducting copper column is installed in the heat dissipating cavity; The first chip, the second chip and the resistor and capacitor are mounted on the substrate by using a sintering technology.

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