Single-phase PFC power factor correction circuit

Abstract

The invention discloses a single-phase PFC power factor correction circuit which comprises a rectification filter circuit, an input voltage sampling circuit, a boost circuit, a PFC chip circuit, a voltage division circuit, a voltage regulation circuit and a voltage output end 80. The voltage input end of the rectification filter circuit is connected to the power grid commercial power, and the voltage output end is a DC output end. One end of the input voltage sampling circuit is electrically connected to the input end of a rectifier bridge in the rectifier filter circuit, the other end of the input voltage sampling circuit is electrically connected to the PFC chip circuit, and the input voltage sampling circuit feeds back a sampling signal of the voltage of the input end of the rectifier bridge of the rectifier filter circuit to the voltage regulation circuit. Under the condition that the circuit mode is not changed, by adding components and reasonably setting the PFC circuit layout, the technical difficulty is solved, and the purposes of small size, light weight and high conversion efficiency are achieved.

Description

Technical Field

[0001] The invention relates to a switching power supply technology, and in particular to a single-phase PFC power factor correction circuit. Background Art

[0002] At present, various countries have strict regulations on the power factor and harmonic requirements when switching power supplies are connected to the power grid. In order to make their products compatible with the power grids of different countries, power supply manufacturers usually set the input voltage range to between 176-264VAC. Based on this, the output voltage of the PFC circuit must reach more than 400VDC at 264VAC. At the same time, when the compatible input voltage is 164VAC, the duty cycle of the switch MOS tube Q1 in the PFC circuit will vary greatly, so the volume of the boost inductor in the circuit is also large, and the weight increases accordingly, resulting in a high temperature rise in the magnetic core, which reduces the conversion efficiency of the entire machine.

[0003] In addition, the gradual increase in PFC output power under the same volume also requires the enhancement of the heat dissipation capacity of the PFC circuit. The PFC circuit in the prior art is difficult to meet the above requirements.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] The purpose of the present invention is to provide a single-phase PFC power factor correction circuit to solve the above technical problems existing in the prior art.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] The single-phase PFC power factor correction circuit of the present invention includes a rectifier filter circuit 20, an input voltage sampling circuit 30, a boost circuit 40, a PFC chip circuit 50, a voltage divider circuit 60, a voltage regulating circuit 70, a diode D1, a capacitor C7, a capacitor C8, a resistor R8, an electrolytic capacitor EC1 and a voltage output terminal 80;

[0008] The voltage input terminal 10 of the rectifier and filter circuit 20 is connected to the mains power grid, and the voltage output terminal 80 is a DC output terminal;

[0009] One end of the input voltage sampling circuit 30 is electrically connected to the input end of the rectifier bridge in the rectifier and filter circuit 20, and the other end of the input voltage sampling circuit 30 is electrically connected to the PFC chip circuit 50. The input voltage sampling circuit 30 feeds back the sampling signal of the rectifier bridge input end voltage of the rectifier and filter circuit 20 to the voltage regulation circuit 70.

[0010] Compared with the prior art, the single-phase PFC power factor correction circuit provided by the present invention can solve the technical difficulties by adding components and reasonably setting the PFC circuit layout without changing the circuit mode, thereby achieving the purpose of small size, light weight and high conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a single-phase PFC power factor correction circuit provided by an embodiment of the present invention.

[0012] In the figure:

[0013] 20. Rectification and filtering circuit, 30. Input voltage sampling circuit, 40. Boost circuit, 50. PFC chip circuit, 60. Voltage divider circuit, 70. Voltage regulation circuit, 80. Voltage output terminal; 10. Voltage input terminal of the rectification and filtering circuit 20. DETAILED DESCRIPTION

[0014] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0015] First, the terms that may be used in this article are explained as follows:

[0016] The contents not described in detail in the examples of the present invention belong to the prior art known to professionals in the field. If no specific conditions are specified in the examples of the present invention, the conditions are carried out according to the conventional conditions in the field or the conditions recommended by the manufacturer. If the manufacturer is not specified in the reagents or instruments used in the examples of the present invention, they are all conventional products that can be purchased commercially.

[0017] The single-phase PFC power factor correction circuit of the present invention includes a rectifier filter circuit 20, an input voltage sampling circuit 30, a boost circuit 40, a PFC chip circuit 50, a voltage divider circuit 60, a voltage regulating circuit 70, a diode D1, a capacitor C7, a capacitor C8, a resistor R8, an electrolytic capacitor EC1 and a voltage output terminal 80;

[0018] The voltage input terminal 10 of the rectifier and filter circuit 20 is connected to the mains power grid, and the voltage output terminal 80 is a DC output terminal;

[0019] One end of the input voltage sampling circuit 30 is electrically connected to the input end of the rectifier bridge in the rectifier and filter circuit 20, and the other end of the input voltage sampling circuit 30 is electrically connected to the PFC chip circuit 50. The input voltage sampling circuit 30 feeds back the sampling signal of the rectifier bridge input end voltage of the rectifier and filter circuit 20 to the voltage regulation circuit 70.

[0020] The input voltage sampling circuit 30 includes a resistor R4, a resistor R5, a resistor R6, a resistor R7, and a capacitor C2 and a capacitor C5;

[0021] The resistor R4 is connected in parallel with the capacitor C2 and then in series with the resistor R5, one end of which is connected to the input circuit L and the other end is grounded;

[0022] The resistor R7 is connected in parallel with the capacitor C5 and then in series with the resistor R6 , one end of which is connected to the input circuit N, and the other end is grounded.

[0023] The voltage regulating circuit 70 includes a resistor R9 and a MOS transistor Q1. The gate of the MOS transistor Q1 is connected to the GD pin of the PFC chip circuit via the resistor R9. The source of the MOS transistor Q1 is connected to the boost circuit 40. The drain of the MOS transistor Q1 is grounded.

[0024] The boost circuit 40 includes an inductor L2 and a diode D2;

[0025] After the inductor L2 and the diode D2 are connected in series, one end thereof is connected to the voltage output terminal, and the other end is connected to the output terminal of the rectifier bridge;

[0026] The common end of the inductor L2 and the diode D2 is connected to the source S of the MOS transistor Q1.

[0027] The rectifier and filter circuit 20 includes a capacitor C1, a capacitor C3, a capacitor C4, a capacitor C6, a common mode inductor L1, a resistor R3 and a rectifier bridge BD1;

[0028] Capacitor C1 and resistor R3 are connected in parallel between input circuit L and N; common mode inductor L1 is connected in series between L and N;

[0029] One end of capacitor C3 is connected to L, and the other end is grounded; one end of capacitor C4 is connected to N, and the other end is grounded; capacitor C6 is connected in parallel between L and N; in the above structure, the rectifier bridge is a bridge rectifier circuit BD1.

[0030] The voltage divider circuit 60 includes a resistor R10 and a resistor R11 , and is disposed between the voltage regulating circuit 70 and the voltage output terminal 80 .

[0031] The PFC chip circuit 50 includes a chip U1, and a GD pin of the chip U1 is connected to the gate of the MOS tube Q1 via a resistor R9.

[0032] The electrolytic capacitor EC1 is connected in parallel to the two ends of the voltage divider circuit 60 , with a DC voltage applied to the positive electrode and a grounded negative electrode.

[0033] The circuit adopts a vertical multi-layer layout, with an aluminum substrate on the bottom layer, MOS tubes, sampling resistors, power inductors and diodes placed on the bottom plate, and the PFC chip circuit 50 placed on the upper layer.

[0034] The working process of this circuit is:

[0035] The grid power enters through the power supply end through the L and N ports, passes through the fuse F1, and pre-charges the circuit;

[0036] Switch K1 and resistor R2, after rectification by rectification and filtering circuit 20, capacitor C7 high frequency filtering turns into pulsating direct current, and sends it to the input end of freewheeling inductor L2;

[0037] The chip U1 starts working after collecting the input voltage, and its GD pin outputs a continuous pulse wave through the resistor R9 to control the on and off of the MOS tube Q1;

[0038] The pulse current flows through the freewheeling inductor L2 and reaches the ground through the MOS tube Q1, so that the voltage at the output end of the freewheeling inductor L2 increases, and then is rectified by the diode D2, and then filtered into a 400V DC power through EC1. Further, the input voltage sampling circuit 30 is formed by the resistor R4, the resistor R5, the resistor R6, the resistor R7 and the capacitor C2, and the capacitor C5, and the resistor R8 samples the change of the current in the freewheeling inductor L1;

[0039] The voltage output terminal 80 is sampled through resistors R10 and R11, and fed back to the OUT pin of U1 to adjust the pulse width of GD so that the output voltage is stabilized at 400VDC.

[0040] In summary, the single-phase PFC power factor correction circuit of the embodiment of the present invention can solve technical difficulties by adding or replacing components and reasonably setting the PFC circuit layout without changing the circuit mode, thereby achieving the purpose of small size, light weight and high conversion efficiency.

[0041] In order to more clearly demonstrate the technical solution and technical effects provided by the present invention, the embodiments of the present invention are described in detail with specific embodiments below.

[0042] Example 1

[0043] like Figure 1 As shown:

[0044] A PFC circuit includes a rectifier filter circuit 20, an input voltage sampling circuit 30, a boost circuit 40, a PFC chip circuit 50, a voltage divider circuit 60, a voltage regulating circuit 70 and a voltage output terminal 80; the voltage input terminal 10 of the rectifier filter circuit 20 is connected to the mains power of the power grid, and a DC output is realized at the voltage output terminal 80 after the mains power is rectified and filtered; one end of the input voltage sampling circuit 30 is electrically connected to the input end of the rectifier bridge BD1 in the rectifier filter circuit 20, and the voltage after voltage division is fed back to the PFC chip circuit to realize the regulation of the voltage at the voltage output terminal 80. The PFC chip circuit 50 includes a chip U1, and the model of the chip U1 is TAE32F5300.

[0045] In this embodiment, the input voltage sampling circuit 30, the PFC chip circuit 50 and the voltage regulating circuit 70 cooperate with the traditional PFC circuit to process the 220V AC power, thereby improving the conversion efficiency. The specific structures of the input voltage sampling circuit 30 and the voltage regulating circuit 70 will be further described below.

[0046] More specifically, the input voltage sampling circuit 30 includes a resistor R4, a resistor R5, a resistor R6, a resistor R7 and a capacitor C2. The capacitor C5, the resistor R4 and the capacitor C2 are connected in parallel and then connected in series with the resistor R5, one end of which is connected to the input circuit L and the other end is grounded; the resistor R7 and the capacitor C5 are connected in parallel and then connected in series with the resistor R6, one end of which is connected to the input circuit N and the other end is grounded; the common end of R4 and R5 is connected to the L sampling end of the PFC chip circuit, and the common end of R6 and R7 is connected to the N sampling end of the PFC chip circuit; the sampled voltage enters the PFC chip circuit for voltage loop calculation, and controls the GN end to output a control signal with a certain duty cycle to the voltage regulator circuit 70, so that the voltage on the output EC1 is increased to 400VDC.

[0047] Continue to refer to Figure 1 As shown, the PFC circuit also includes a boost circuit 40, a resistor R8, and a diode D1;

[0048] The boost circuit 40 includes an inductor L2 and a diode D2. After the inductor L2 and the diode D2 are connected in series, one end thereof is connected to the voltage output end, and the other end is connected to the output end of the rectifier bridge; the common end of the inductor L2 and the diode D2 is connected to the source S of the MOS tube Q1, and the inductor L2 uses a planar inductor to reduce the volume. The on-off control of the MOS tube Q1 controls the voltage on the inductor L2, so that the voltage at the rear end of the diode D2 rises to 400VDC. One end of the resistor R8 is connected to the I-end of the PFC chip circuit, and the other end is connected to the GND end of the PFC chip circuit. By sampling the current in the loop, it is sent to the chip to achieve the effect of overcurrent protection. One end of the diode D1 is connected to the output end of the rectifier filter circuit, and the other end is connected to the voltage output end 80, providing a high-frequency bypass (bypass) for the inductor L2, thereby reducing the loss of the inductor L2 at high frequencies and improving the overall efficiency and performance of the system.

[0049] Furthermore, the rectifier filter circuit includes capacitor C1, capacitor C3, capacitor C4, capacitor C6, inductor L1, resistor R3 and rectifier bridge BD1. Capacitor C1 and resistor R3 are connected in parallel between input circuit L and N; common mode inductor L1 is connected in series between L and N; one end of capacitor C3 is connected to L and the other end is grounded; one end of capacitor C4 is connected to N and the other end is grounded; capacitor C6 is connected in parallel between L and N; in the above structure, the rectifier bridge is a bridge rectifier circuit BD1. Safety capacitors C1, C3, C4, C6 and common mode inductor L1 play a role in power supply filtering, and play a role in filtering common mode and differential mode interference respectively.

[0050] The voltage divider circuit 60 is composed of a resistor R10 and a resistor R11, and is arranged between the voltage regulating circuit and the voltage output terminal. The common end of the resistor R10 and the resistor R11 is connected to the OUT terminal of the PFC chip circuit 50, and the output DC voltage is monitored. The feedback value participates in the calculation of the output duty cycle of the PFC chip, and the output overvoltage and undervoltage protection functions are realized at the same time.

[0051] Furthermore, the PFC circuit further includes an electrolytic capacitor EC1; the electrolytic capacitor EC1 is connected in parallel to two ends of the voltage divider circuit 60, with a positive electrode being supplied with a DC voltage and a negative electrode being grounded.

[0052] The PFC circuit adopts a vertical multi-layer layout, with an aluminum substrate at the bottom layer. MOS tubes, sampling resistors, power inductors, diodes and other devices that generate severe heat are placed on the bottom plate, and PFC chip circuits are placed on the upper layer, so that the overall volume of the PFC is reduced while ensuring the heat dissipation capacity of the PFC module.

[0053] In the above circuit structure, combined with Figure 1As shown, the grid power enters through the power supply end through the L and N ports, passes through the fuse F1, and the pre-charge circuit: switch K1 and resistor R2, is rectified by the rectifier filter circuit 20, and becomes pulsating direct current after high-frequency filtering by capacitor C7, and is sent to the input end of the freewheeling inductor L2. The chip U1 starts working after collecting the input voltage, and its GD pin outputs a continuous pulse wave through resistor R9 to control the conduction and cutoff of MOS tube Q1. The freewheeling inductor L2 flows through the pulse current, and reaches the ground through the MOS tube Q1, so that the voltage at the output end of the freewheeling inductor L2 increases, and then rectified by diode D2, and then filtered by EC1 into 400V direct current. Further, through resistor R4, resistor R5, resistor R6, resistor R7 and capacitor C2, capacitor C5 forms an input voltage sampling circuit 30, and resistor R8 samples the change of current in the freewheeling inductor L1. The voltage output terminal 80 is sampled through resistors R10 and R11, and fed back to the OUT pin of U1 to adjust the pulse width of GD so that the output voltage is stabilized at 400VDC. In this way, the duty cycle of the freewheeling inductor L1 will be reduced. If the inductor is replaced with a planar inductor, the volume of the inductor itself will be reduced, and the weight will also be reduced accordingly.

[0054] The beneficial effect of the invention is that it can solve the technical difficulties by adding or replacing components and reasonably setting the PFC circuit layout without changing the circuit mode, thereby achieving the purpose of small size, light weight and high conversion efficiency.

[0055] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A single-phase PFC power factor correction circuit, characterized in that: It comprises a rectifier filter circuit (20), an input voltage sampling circuit (30), a boost circuit (40), a PFC chip circuit (50), a voltage divider circuit (60), a voltage regulating circuit (70), a diode D1, a capacitor C7, a capacitor C8, a resistor R8, an electrolytic capacitor EC1 and a voltage output terminal (80); The voltage input end (10) of the rectifier and filter circuit (20) is connected to the mains power grid, and the voltage output end (80) is a DC output end; One end of the input voltage sampling circuit (30) is electrically connected to the input end of the rectifier bridge in the rectifier filter circuit (20), and the other end of the input voltage sampling circuit (30) is electrically connected to the PFC chip circuit (50). The input voltage sampling circuit (30) feeds back a sampling signal of the voltage at the input end of the rectifier bridge of the rectifier filter circuit (20) to the voltage regulating circuit (70).

2. The single-phase PFC power factor correction circuit according to claim 1, characterized in that: The input voltage sampling circuit (30) comprises a resistor R4, a resistor R5, a resistor R6, a resistor R7 and a capacitor C2 and a capacitor C5; The resistor R4 is connected in parallel with the capacitor C2 and then in series with the resistor R5, one end of which is connected to the input circuit L and the other end is grounded; The resistor R7 is connected in parallel with the capacitor C5 and then in series with the resistor R6 , one end of which is connected to the input circuit N, and the other end is grounded.

3. The single-phase PFC power factor correction circuit according to claim 2, characterized in that: The voltage regulating circuit (70) comprises a resistor R9 and a MOS tube Q1, the gate of the MOS tube Q1 is connected to the GD pin of the PFC chip circuit via the resistor R9, the source of the MOS tube Q1 is connected to the boost circuit (40), and the drain of the MOS tube Q1 is grounded.

4. The single-phase PFC power factor correction circuit according to claim 3, characterized in that: The boost circuit (40) comprises an inductor L2 and a diode D2; After the inductor L2 and the diode D2 are connected in series, one end thereof is connected to the voltage output terminal, and the other end is connected to the output terminal of the rectifier bridge; The common end of the inductor L2 and the diode D2 is connected to the source S of the MOS transistor Q1.

5. The single-phase PFC power factor correction circuit according to claim 4, characterized in that: The rectifier and filter circuit (20) comprises a capacitor C1, a capacitor C3, a capacitor C4, a capacitor C6, a common mode inductor L1, a resistor R3 and a rectifier bridge BD1; Capacitor C1 and resistor R3 are connected in parallel between input circuit L and N; common mode inductor L1 is connected in series between L and N; One end of capacitor C3 is connected to L, and the other end is grounded; one end of capacitor C4 is connected to N, and the other end is grounded; Capacitor C6 is connected in parallel between L and N; in the above structure, the rectifier bridge is a bridge rectifier circuit BD1.

6. The single-phase PFC power factor correction circuit according to claim 5, characterized in that: The voltage divider circuit (60) comprises a resistor R10 and a resistor R11, which are arranged between the voltage regulating circuit (70) and the voltage output terminal (80).

7. The single-phase PFC power factor correction circuit according to claim 6, characterized in that: The PFC chip circuit (50) comprises a chip U1, and a GD pin of the chip U1 is connected to the gate of the MOS tube Q1 via a resistor R9.

8. The single-phase PFC power factor correction circuit according to claim 7, characterized in that: The electrolytic capacitor EC1 is connected in parallel to both ends of the voltage divider circuit (60), with a DC voltage applied to the positive electrode and a grounded negative electrode.

9. The single-phase PFC power factor correction circuit according to claim 8, characterized in that: The circuit adopts a vertical multi-layer layout mode, the bottom layer adopts an aluminum substrate, the MOS tube, sampling resistor, power inductor and diode are placed on the bottom plate, and the PFC chip circuit (50) is placed on the upper layer.

10. The single-phase PFC power factor correction circuit according to any one of claims 1 to 9, characterized in that: The working process of this circuit is: The grid power enters through the power supply end through the L and N ports, passes through the fuse F1, and pre-charges the circuit; The switch K1 and the resistor R2 are rectified by the rectifying and filtering circuit (20), and the capacitor C7 high-frequency filters the pulsating direct current, which is then sent to the input end of the freewheeling inductor L2; The chip U1 starts working after collecting the input voltage, and its GD pin outputs a continuous pulse wave through the resistor R9 to control the on and off of the MOS tube Q1; The pulse current flows through the freewheeling inductor L2 and reaches the ground through the MOS tube Q1, so that the voltage at the output end of the freewheeling inductor L2 increases, and then is rectified by the diode D2, and then filtered into a 400V direct current through EC1. Further, the input voltage sampling circuit (30) is formed by the resistor R4, the resistor R5, the resistor R6, the resistor R7 and the capacitor C2, and the capacitor C5, and the resistor R8 samples the change of the current in the freewheeling inductor L1; The voltage output terminal (80) is sampled through resistors R10 and R11 and fed back to the OUT pin of U1 to adjust the pulse width of GD so that the output voltage is stabilized at 400VDC.

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