Differential Low-Noise Amplifier and RF Chip

Abstract

The present invention is applicable to the field of communication technologies, and particularly relates to a differential low-noise amplifier and a radio frequency chip. The differential low-noise amplifier includes a first low-noise amplification unit and a second low-noise amplification unit; the first low-noise amplification unit is used to cancel the noise generated by the differential low-noise amplifier; the output end of the second low-noise amplification unit serves as the output end of the differential low-noise amplifier and is used to output a signal, and the second low-noise amplification unit is used to perform input matching on the broadband of the differential low-noise amplifier. Compared with the prior art, the present invention adopts a two-stage cascaded structure composed of the first low-noise amplification unit and the second low-noise amplification unit. The first low-noise amplification unit cancels the noise by utilizing transistor characteristics, and the second low-noise amplification unit enhances the isolation between the input and the output while enhancing the gain, and finally realizes broadband input matching, noise cancellation and single-ended to differential conversion of the entire differential low-noise amplifier, and is applicable to radio frequency front-end circuits.

Description

Technical Field

[0001] The present invention is applicable to the field of communication technologies, and particularly relates to a differential low-noise amplifier and a radio frequency chip. Background Art

[0002] With the development of wireless communication technologies, the radio frequency front-end circuit has always been one of the key areas of research and innovation. As the starting part of the receiving link, the processing ability of the differential low-noise amplifier directly determines the performance of the entire communication system. In recent years, with the continuous update of communication standards and the increasingly rich application scenarios, such as the rise of smart home and intelligent transportation fields, the requirements for the adaptability and performance of radio frequency front-end circuits have become increasingly strict.

[0003] However, when facing these new requirements, the existing single-ended low-noise amplifiers gradually show their deficiencies in aspects such as noise suppression, bandwidth expansion, and signal processing flexibility, having problems of poor noise suppression effect, low gain, and poor linearity, and being unable to meet the performance requirements of existing radio frequency front-end circuits.

[0004] Therefore, there is an urgent need for a new differential low-noise amplifier and radio frequency chip to solve the above technical problems. Summary of the Invention

[0005] The present invention provides a differential low-noise amplifier and a radio frequency chip, aiming to improve the bandwidth and linearity of the differential low-noise amplifier and reduce the noise figure.

[0006] In a first aspect, the present invention provides a differential low-noise amplifier, and the differential low-noise amplifier includes a first low-noise amplification unit and a second low-noise amplification unit;

[0007] The input end of the first low-noise amplification unit serves as the input end of the differential low-noise amplifier for receiving an input signal. The first output end of the first low-noise amplification unit is connected to the first input end of the second low-noise amplification unit, and the second output end of the first low-noise amplification unit is connected to the second input end of the second low-noise amplification unit. The first low-noise amplification unit is used to cancel the noise generated by the differential low-noise amplifier and realize the conversion from a single-ended input signal to a differential output signal;

[0008] The output end of the second low-noise amplification unit serves as the output end of the differential low-noise amplifier for outputting a signal. The second low-noise amplification unit is used to match and optimize the gain and broadband of the differential low-noise amplifier;

[0009] The first low-noise amplification unit includes an input matching circuit, a first amplification circuit, and a first output matching circuit; the input end of the input matching circuit serves as the input end of the first low-noise amplification unit, the output end of the input matching circuit is connected to the input end of the first amplification circuit, the first output end of the first amplification circuit is connected to the first input end of the first output matching circuit, the second output end of the first amplification circuit is connected to the second input end of the first output matching circuit, the first output end of the first output matching circuit serves as the first output end of the first low-noise amplification unit, and the second output end of the first output matching circuit serves as the second output end of the first low-noise amplification unit; wherein, the first amplification circuit is a noise-canceling amplification circuit based on a common-gate-common-source structure composed of MOS transistors.

[0010] The second low-noise amplification unit includes a second amplification circuit, a third amplification circuit, and a second output matching circuit; the input end of the second amplification circuit serves as the first input end of the second low-noise amplification unit, the output end of the second amplification circuit is connected to the first input end of the second output matching circuit, the input end of the third amplification circuit serves as the second input end of the second low-noise amplification unit, the output end of the third amplification circuit is connected to the second input end of the second output matching circuit, and the output end of the second output matching circuit serves as the output end of the second low-noise amplification unit; wherein, the second amplification circuit is a cascode structure amplification circuit composed of MOS transistors.

[0011] The first amplification circuit includes a first inductor, a second inductor, a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the source electrode of the first MOS transistor serves as the input end of the first amplification circuit, the gate electrode of the first MOS transistor is used to connect to a first external bias voltage, and the drain electrode of the first MOS transistor is connected to the source electrode of the second MOS transistor; the first end of the first inductor is connected to the source electrode of the first MOS transistor, and the second end of the first inductor is grounded; the gate electrode of the second MOS transistor is connected to the gate electrode of the fourth MOS transistor, and the drain electrode of the second MOS transistor serves as the second output end of the first amplification circuit; the gate electrode of the third MOS transistor is connected to the source electrode of the first MOS transistor, the source electrode of the third MOS transistor is connected to the first end of the second inductor, the second end of the second inductor is grounded, the drain electrode of the third MOS transistor is connected to the source electrode of the fourth MOS transistor, and the drain electrode of the fourth MOS transistor serves as the first output end of the first amplification circuit.

[0012] Preferably, the input matching circuit includes a first capacitor; the first end of the first capacitor serves as the input end of the input matching circuit, and the second end of the first capacitor serves as the output end of the input matching circuit.

[0013] Preferably, the first output matching circuit includes a third inductor, a fourth inductor, a second capacitor, and a third capacitor; the first end of the third inductor serves as the second input end of the first output matching circuit, the second end of the third inductor is connected to an external power supply voltage, the first end of the fourth inductor serves as the first input end of the first output matching circuit, the second end of the fourth inductor is connected to an external power supply voltage, the first end of the second capacitor is connected to the first end of the third inductor, the second end of the second capacitor serves as the second output end of the first output matching circuit, the first end of the third capacitor is connected to the first end of the fourth inductor, and the second end of the third capacitor serves as the first output end of the first output matching circuit.

[0014] Preferably, the second amplifying circuit includes a fifth inductor, a sixth inductor, a seventh inductor, a fifth MOS transistor, and a sixth MOS transistor; the gate of the fifth MOS transistor serves as the input end of the second amplifying circuit, the source of the fifth MOS transistor is connected to the first end of the fifth inductor, the second end of the fifth inductor is grounded, the drain of the fifth MOS transistor is connected to the first end of the sixth inductor, the second end of the sixth inductor is connected to the source of the sixth MOS transistor, the drain of the sixth MOS transistor serves as the output end of the second amplifying circuit, the gate of the sixth MOS transistor is connected to the first end of the seventh inductor, and the second end of the seventh inductor is connected to a second external bias voltage.

[0015] Preferably, the third amplifying circuit includes an eighth inductor, a ninth inductor, a tenth inductor, a seventh MOS transistor, and an eighth MOS transistor; the gate of the seventh MOS transistor serves as the input end of the third amplifying circuit, the source of the seventh MOS transistor is connected to the first end of the eighth inductor, the second end of the eighth inductor is grounded, the drain of the seventh MOS transistor is connected to the first end of the ninth inductor, the second end of the ninth inductor is connected to the source of the eighth MOS transistor, the drain of the eighth MOS transistor serves as the output end of the third amplifying circuit, the gate of the eighth MOS transistor is connected to the first end of the tenth inductor, and the second end of the tenth inductor is connected to a second external bias voltage.

[0016] Preferably, the second output matching circuit includes a fourth capacitor, a fifth capacitor, an eleventh inductor, and a twelfth inductor; one end of the eleventh inductor serves as the first input terminal of the second output matching circuit, the second end of the eleventh inductor is connected to an external power supply voltage, the first end of the fourth capacitor is connected to the first end of the eleventh inductor, the second end of the fourth capacitor serves as the first output terminal of the second output matching circuit, the first end of the twelfth inductor serves as the second input terminal of the second output matching circuit, the second end of the twelfth inductor is connected to an external power supply voltage, the first end of the fifth capacitor is connected to the first end of the twelfth inductor, and the second end of the fifth capacitor serves as the second output terminal of the second output matching circuit.

[0017] In a second aspect, the present invention further provides a radio frequency chip, which includes the differential low-noise amplifier according to any one of the above embodiments.

[0018] Compared with the prior art, the present invention adopts a two-stage cascaded structure composed of a first low-noise amplification unit and a second low-noise amplification unit. The first low-noise amplification unit cancels noise by utilizing transistor characteristics. While enhancing the gain, the second low-noise amplification unit enhances the isolation between the input and the output, and finally realizes broadband input matching, noise cancellation, and single-ended to differential conversion of the entire differential low-noise amplifier, which is applicable to radio frequency front-end circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be described in detail below with reference to the drawings. Through the detailed description in combination with the following drawings, the above or other aspects of the present invention will become clearer and easier to understand. In the drawings:

[0020] Figure 1 is a schematic circuit structure diagram of the differential low-noise amplifier provided by an embodiment of the present invention Figure 1 ;

[0021] Figure 2 is a schematic circuit structure diagram of the differential low-noise amplifier provided by an embodiment of the present invention Figure 2 .

[0022] In the figure, 100 is a differential low-noise amplifier, 10 is a first low-noise amplification unit, 11 is an input matching circuit, 12 is a first amplification circuit, 13 is a first output matching circuit, 20 is a second low-noise amplification unit, 21 is a second amplification circuit, 22 is a third amplification circuit, and 23 is a second output matching circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0024] Embodiment 1

[0025] Please refer to Figure 1 - Figure 2 , the present invention provides a differential low-noise amplifier 100, and the differential low-noise amplifier 100 includes a first low-noise amplification unit 10 and a second low-noise amplification unit 20;

[0026] The input end of the first low-noise amplification unit 10 serves as the input end of the differential low-noise amplifier 100 for receiving an input signal. The first output end of the first low-noise amplification unit 10 is connected to the first input end of the second low-noise amplification unit 20, and the second output end of the first low-noise amplification unit 10 is connected to the second input end of the second low-noise amplification unit 20. The first low-noise amplification unit 10 is used to cancel the noise generated by the differential low-noise amplifier 100 and realize the conversion from a single-ended input signal to a differential output signal;

[0027] The output end of the second low-noise amplification unit 20 serves as the output end of the differential low-noise amplifier 100 for outputting a signal. The second low-noise amplification unit 20 is used to match and optimize the gain and bandwidth of the differential low-noise amplifier 100;

[0028] The first low-noise amplification unit 10 includes an input matching circuit 11, a first amplification circuit 12, and a first output matching circuit 13; the input end of the input matching circuit 11 serves as the input end of the first low-noise amplification unit 10, the output end of the input matching circuit 11 is connected to the input end of the first amplification circuit 12, the first output end of the first amplification circuit 12 is connected to the first input end of the first output matching circuit 13, the second output end of the first amplification circuit 12 is connected to the second input end of the first output matching circuit 13, the first output end of the first output matching circuit 13 serves as the first output end of the first low-noise amplification unit 10, and the second output end of the first output matching circuit 13 serves as the second output end of the first low-noise amplification unit 10; wherein, the first amplification circuit 12 is a noise cancellation amplification circuit based on a common-gate and common-source structure composed of MOS transistors;

[0029] The second low-noise amplification unit 20 includes a second amplification circuit 21, a third amplification circuit 22, and a second output matching circuit 23; the input end of the second amplification circuit 21 serves as the first input end of the second low-noise amplification unit 20, the output end of the second amplification circuit 21 is connected to the first input end of the second output matching circuit 23, the input end of the third amplification circuit 22 serves as the second input end of the second low-noise amplification unit 20, the output end of the third amplification circuit 22 is connected to the second input end of the second output matching circuit 23, and the output end of the second output matching circuit 23 serves as the output end of the second low-noise amplification unit 20; wherein, the second amplification circuit 21 is a cascode structure amplification circuit composed of MOS transistors.

[0030] In an embodiment of the present invention, the first amplification circuit 12 includes a first inductor L1, a second inductor L2, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4; the source electrode of the first MOS transistor M1 serves as the input end of the first amplification circuit 12, the gate electrode of the first MOS transistor M1 is connected to a first external bias voltage VBIAS1, the drain electrode of the first MOS transistor M1 is connected to the source electrode of the second MOS transistor M2, the first end of the first inductor L1 is connected to the source electrode of the first MOS transistor M1, the second end of the first inductor L1 is grounded, the gate electrode of the second MOS transistor M2 is connected to the gate electrode of the fourth MOS transistor M4, the drain electrode of the second MOS transistor M2 serves as the second output end of the first amplification circuit 12, the gate electrode of the third MOS transistor M3 is connected to the source electrode of the first MOS transistor M1, the source electrode of the third MOS transistor M3 is connected to the first end of the second inductor L2, the second end of the second inductor L2 is grounded, the drain electrode of the third MOS transistor M3 is connected to the source electrode of the fourth MOS transistor M4, and the drain electrode of the fourth MOS transistor M4 serves as the first output end of the first amplification circuit 12.

[0031] Specifically, Figure 1 - Figure 2K1-K6 in it represent different coupling coefficients, and the specific values of the coupling coefficients are adjusted according to the actual simulation results. Among them, the first inductor L1 and the second inductor L2 are mutually coupled with a coupling coefficient of K1; the third inductor L3 and the fourth inductor L4 are mutually coupled with a coupling coefficient of K2; the eleventh inductor L11 and the twelfth inductor L12 are mutually coupled with a coupling coefficient of K3; the sixth inductor L6 and the seventh inductor L7 are mutually coupled with a coupling coefficient of K4; the ninth inductor L9 and the tenth inductor L10 are mutually coupled with a coupling coefficient of K5; the fifth inductor L5 and the eighth inductor L8 are mutually coupled with a coupling coefficient of K6. The differential low-noise amplifier 100 of the present invention adopts a cascaded structure of a two-stage amplifier circuit composed of a first low-noise amplification unit 10 and a second low-noise amplification unit 20, and realizes noise cancellation and single-ended to differential conversion through the cascading of two-stage circuits.

[0032] When the input noise acts on the gate of the first MOS transistor M1 of the first low-noise amplification unit 10, the noise current will generate a voltage change at the drain and source of the first MOS transistor M1. Due to the particularity of the circuit structure, the voltage generated by the drain noise current of the first MOS transistor M1 at the differential output terminal is correlated with the noise voltage output by the second MOS transistor M2. By reasonably designing the circuit parameters according to the actual situation, these two noise voltages can be made equal in magnitude and the same in polarity, so as to cancel each other out at the differential output terminal. And the second low-noise amplification unit 20 further optimizes the gain and bandwidth of the overall circuit of the differential low-noise amplifier 100, and enhances the isolation between the input and the output. This circuit not only realizes broadband input matching and noise cancellation, but also completes single-ended to differential conversion, effectively improving the linearity, gain and bandwidth of the differential low-noise amplifier 100, not only enhancing the isolation between the input and the output, but also canceling the noise of the first amplifier circuit 12, making the performance of the differential low-noise amplifier 100 better.

[0033] In the embodiment of the present invention, the input matching circuit 11 includes a first capacitor C1; the first end of the first capacitor C1 serves as the input end of the input matching circuit 11, and the second end of the first capacitor C1 serves as the output end of the input matching circuit 11. The first capacitor C1 is an input DC-blocking capacitor.

[0034] In an embodiment of the present invention, the first output matching circuit 13 includes a third inductor L3, a fourth inductor L4, a second capacitor C2, and a third capacitor C3. The second capacitor C2 and the third capacitor C3 are inter-stage capacitors. The first end of the third inductor L3 serves as the second input end of the first output matching circuit 13. The second end of the third inductor L3 is connected to an external power supply voltage VDD. The first end of the fourth inductor L4 serves as the first input end of the first output matching circuit 13. The second end of the fourth inductor L4 is connected to the external power supply voltage VDD. The first end of the second capacitor C2 is connected to the first end of the third inductor L3. The second end of the second capacitor C2 serves as the second output end of the first output matching circuit 13. The first end of the third capacitor C3 is connected to the first end of the fourth inductor L4. The second end of the third capacitor C3 serves as the first output end of the first output matching circuit 13.

[0035] In an embodiment of the present invention, the second amplifier circuit 21 includes a fifth inductor L5, a sixth inductor L6, a seventh inductor L7, a fifth MOS transistor M5, and a sixth MOS transistor M6. The gate of the fifth MOS transistor M5 serves as the input end of the second amplifier circuit 21. The source of the fifth MOS transistor M5 is connected to the first end of the fifth inductor L5. The second end of the fifth inductor L5 is grounded. The drain of the fifth MOS transistor M5 is connected to the first end of the sixth inductor L6. The second end of the sixth inductor L6 is connected to the source of the sixth MOS transistor M6. The drain of the sixth MOS transistor M6 serves as the output end of the second amplifier circuit 21. The gate of the sixth MOS transistor M6 is connected to the first end of the seventh inductor L7. The second end of the seventh inductor L7 is connected to a second external bias voltage VBIAS2. It should be noted that the specific values of the first external bias voltage VBIAS1 and the second external bias voltage VBIAS2 can be set according to actual situations. It is feasible that the values of the first external bias voltage VBIAS1 and the second external bias voltage VBIAS2 are the same or different.

[0036] In an embodiment of the present invention, the third amplification circuit 22 includes an eighth inductor L8, a ninth inductor L9, a tenth inductor L10, a seventh MOS transistor M7, and an eighth MOS transistor M8; the gate of the seventh MOS transistor M7 serves as the input end of the third amplification circuit 22, the source of the seventh MOS transistor M7 is connected to the first end of the eighth inductor L8, the second end of the eighth inductor L8 is grounded, the drain of the seventh MOS transistor M7 is connected to the first end of the ninth inductor L9, the second end of the ninth inductor L9 is connected to the source of the eighth MOS transistor M8, the drain of the eighth MOS transistor M8 serves as the output end of the third amplification circuit 22, the gate of the eighth MOS transistor is connected to the first end of the tenth inductor L10, and the second end of the tenth inductor L10 is connected to a second external bias voltage VBIAS2.

[0037] In an embodiment of the present invention, the second output matching circuit 23 includes a fourth capacitor C4, a fifth capacitor C5, an eleventh inductor L11, and a twelfth inductor L12; one end of the eleventh inductor L11 serves as the first input end of the second output matching circuit 23, the second end of the eleventh inductor L11 is connected to an external power supply voltage VDD, the first end of the fourth capacitor C4 is connected to the first end of the eleventh inductor L11, the second end of the fourth capacitor C4 serves as the first output end of the second output matching circuit 23 (i.e., Vout1), one end of the twelfth inductor L12 serves as the second input end of the second output matching circuit 23, the second end of the twelfth inductor L12 is connected to the external power supply voltage VDD, the first end of the fifth capacitor C5 is connected to the first end of the twelfth inductor L12, and the second end of the fifth capacitor C5 serves as the second output end of the second output matching circuit 23 (i.e., Vout2).

[0038] Compared with the prior art, the present invention adopts a two-stage cascaded structure composed of a first low-noise amplification unit and a second low-noise amplification unit. The first low-noise amplification unit cancels noise by utilizing transistor characteristics. The second low-noise amplification unit enhances the isolation between the input and the output while enhancing the gain, and finally realizes broadband input matching, noise cancellation, and single-ended to differential conversion of the entire differential low-noise amplifier, which is applicable to radio frequency front-end circuits.

[0039] Embodiment 2

[0040] The embodiment of the present invention further provides a radio frequency chip, which includes the differential low-noise amplifier 100 as described in the above embodiment and can achieve the same technical effects. Referring to the description in the above embodiment, it will not be elaborated here.

[0041] It should be noted that in this text, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including such element.

[0042] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiments of the present invention. However, the present invention is not limited to the above specific implementation manners. The above specific implementation manners are merely illustrative rather than restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many equivalent changes in form without departing from the spirit of the present invention and the scope protected by the claims, and all of them fall within the protection scope of the present invention.

Claims

1. A differential low-noise amplifier, characterized in that, The differential low-noise amplifier includes a first low-noise amplification unit and a second low-noise amplification unit; The input end of the first low-noise amplification unit serves as the input end of the differential low-noise amplifier for receiving an input signal. The first output end of the first low-noise amplification unit is connected to the first input end of the second low-noise amplification unit, and the second output end of the first low-noise amplification unit is connected to the second input end of the second low-noise amplification unit. The first low-noise amplification unit is used to cancel the noise generated by the differential low-noise amplifier and implement the conversion from a single-ended input signal to a differential output signal; The output end of the second low-noise amplification unit serves as the output end of the differential low-noise amplifier for outputting a signal. The second low-noise amplification unit is used to match and optimize the gain and bandwidth of the differential low-noise amplifier; The first low-noise amplification unit includes an input matching circuit, a first amplification circuit, and a first output matching circuit; The input end of the input matching circuit serves as the input end of the first low-noise amplification unit. The output end of the input matching circuit is connected to the input end of the first amplification circuit. The first output end of the first amplification circuit is connected to the first input end of the first output matching circuit, and the second output end of the first amplification circuit is connected to the second input end of the first output matching circuit. The first output end of the first output matching circuit serves as the first output end of the first low-noise amplification unit, and the second output end of the first output matching circuit serves as the second output end of the first low-noise amplification unit. Among them, the first amplification circuit is a noise cancellation amplification circuit based on a common-gate-common-source structure composed of MOS transistors; The second low-noise amplification unit includes a second amplification circuit, a third amplification circuit, and a second output matching circuit. The input end of the second amplification circuit serves as the first input end of the second low-noise amplification unit. The output end of the second amplification circuit is connected to the first input end of the second output matching circuit. The input end of the third amplification circuit serves as the second input end of the second low-noise amplification unit. The output end of the third amplification circuit is connected to the second input end of the second output matching circuit. The output end of the second output matching circuit serves as the output end of the second low-noise amplification unit. Among them, the second amplification circuit is a cascode structure amplification circuit composed of MOS transistors; The first output matching circuit includes a third inductor, a fourth inductor, a second capacitor, and a third capacitor; the first end of the third inductor serves as the second input terminal of the first output matching circuit, the second end of the third inductor is used to connect to an external power supply voltage, the first end of the fourth inductor serves as the first input terminal of the first output matching circuit, and the second end of the fourth inductor is used to connect to an external power supply voltage; the first end of the second capacitor is connected to the first end of the third inductor, the second end of the second capacitor serves as the second output terminal of the first output matching circuit, the first end of the third capacitor is connected to the first end of the fourth inductor, and the second end of the third capacitor serves as the first output terminal of the first output matching circuit.

2. The differential low-noise amplifier according to claim 1, wherein The first amplifier circuit includes a first inductor, a second inductor, a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the source electrode of the first MOS transistor serves as the input terminal of the first amplifier circuit, the gate electrode of the first MOS transistor is used to connect to a first external bias voltage, and the drain electrode of the first MOS transistor is connected to the source electrode of the second MOS transistor; The first end of the first inductor is connected to the source electrode of the first MOS transistor, and the second end of the first inductor is grounded; the gate electrode of the second MOS transistor is connected to the gate electrode of the fourth MOS transistor, and the drain electrode of the second MOS transistor serves as the second output terminal of the first amplifier circuit; the gate electrode of the third MOS transistor is connected to the source electrode of the first MOS transistor, the source electrode of the third MOS transistor is connected to the first end of the second inductor, the second end of the second inductor is grounded, the drain electrode of the third MOS transistor is connected to the source electrode of the fourth MOS transistor, and the drain electrode of the fourth MOS transistor serves as the first output terminal of the first amplifier circuit.

3. The differential low-noise amplifier according to claim 1, wherein The input matching circuit includes a first capacitor; the first end of the first capacitor serves as the input terminal of the input matching circuit, and the second end of the first capacitor serves as the output terminal of the input matching circuit.

4. The differential low-noise amplifier according to claim 1, wherein The second amplifier circuit includes a fifth inductor, a sixth inductor, a seventh inductor, a fifth MOS transistor, and a sixth MOS transistor; the gate electrode of the fifth MOS transistor serves as the input terminal of the second amplifier circuit, the source electrode of the fifth MOS transistor is connected to the first end of the fifth inductor, the second end of the fifth inductor is grounded, and the drain electrode of the fifth MOS transistor is connected to the first end of the sixth inductor; the second end of the sixth inductor is connected to the source electrode of the sixth MOS transistor, the drain electrode of the sixth MOS transistor serves as the output terminal of the second amplifier circuit, the gate electrode of the sixth MOS transistor is connected to the first end of the seventh inductor, and the second end of the seventh inductor is used to connect to a second external bias voltage.

5. The differential low-noise amplifier according to claim 1, characterized in that, The third amplifying circuit includes an eighth inductor, a ninth inductor, a tenth inductor, a seventh MOS transistor, and an eighth MOS transistor; the gate of the seventh MOS transistor serves as the input terminal of the third amplifying circuit, the source of the seventh MOS transistor is connected to the first end of the eighth inductor, the second end of the eighth inductor is grounded, and the drain of the seventh MOS transistor is connected to the first end of the ninth inductor; the second end of the ninth inductor is connected to the source of the eighth MOS transistor, the drain of the eighth MOS transistor serves as the output terminal of the third amplifying circuit, the gate of the eighth MOS transistor is connected to the first end of the tenth inductor, and the second end of the tenth inductor is used to connect to a second external bias voltage.

6. The differential low-noise amplifier according to claim 1, characterized in that The second output matching circuit includes a fourth capacitor, a fifth capacitor, an eleventh inductor, and a twelfth inductor; one end of the eleventh inductor serves as the first input terminal of the second output matching circuit, and the second end of the eleventh inductor is used to connect to an external power supply voltage; the first end of the fourth capacitor is connected to the first end of the eleventh inductor, and the second end of the fourth capacitor serves as the first output terminal of the second output matching circuit; one end of the twelfth inductor serves as the second input terminal of the second output matching circuit, and the second end of the twelfth inductor is used to connect to an external power supply voltage; the first end of the fifth capacitor is connected to the first end of the twelfth inductor, and the second end of the fifth capacitor serves as the second output terminal of the second output matching circuit.

7. A radio frequency chip, characterized in that, The RF chip includes the differential low-noise amplifier as described in claims 1-6.

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