High-density integrated interference suppression device and electronic device

Abstract

The invention discloses a high-density integrated interference suppression device and an electronic device. The device comprises a first band elimination module, a second band elimination module and a branch module, wherein the frequency response of the first band elimination module has an attenuation pole; the first band-stop module comprises a first capacitive structure and a first inductive structure which are coupled in parallel; the second band-stop module comprises a first connecting end, a second connecting end, a first common end, a second capacitive structure, a third capacitive structure, a second inductive structure, a first potential end and a second capacitive structure, and the first common end is connected between the first connecting end and the second connecting end; the third capacitive structure and the second inductive structure are connected in series between the first common end and the first potential end; the branch module comprises a third connecting end, a second potential end, and a third band-stop module and a fourth capacitive structure which are connected between the third connecting end and the second potential end; the third band-stop module comprises a fifth capacitive structure and a third inductive structure which are coupled in parallel. The filter has the characteristics of excellent noise suppression capability, excellent frequency selection performance and outstanding miniaturization.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of radio frequency filters, and in particular to a high-density integrated interference suppression device and an electronic device. Background Art

[0002] Filters are key circuit components in modern communication systems. As the complexity of RF front-end systems increases, the size of filters must be further miniaturized to improve integration. At the same time, as channels in the wireless spectrum become more and more dense, in order to reduce interference between adjacent channels and ensure highly reliable wireless access, higher requirements are placed on the out-of-band suppression capabilities of RF filters in the system. However, most of the chip filters widely used in today's RF systems are based on traditional circuit structures, and their interference suppression performance is limited. At the same time, most chip filters use planar integration, and the required planar size is relatively large, which makes it difficult to meet the application requirements of high integration of communication systems. Summary of the invention

[0003] In view of the above problems, the object of the present invention is to provide a high-density integrated interference suppression device and an electronic device with outstanding out-of-band suppression and miniaturization.

[0004] The high-density integrated interference suppression device proposed in the present invention is based on a first band-stop module, a second band-stop module and a branch module having attenuation poles in frequency response, and designs the internal structure of the above modules and the coupling relationship therebetween, so that the frequency response of the high-density integrated interference suppression device can achieve at least three out-of-band transmission zero points, and has excellent noise suppression capability and frequency selection performance.

[0005] According to one aspect of the present invention, there is provided a high-density integrated interference suppression device, comprising:

[0006] The first band-stop module comprises a first capacitive structure and a first inductive structure coupled in parallel with the first capacitive structure, and the frequency response of the first band-stop module has an attenuation pole; the second band-stop module comprises a first connection terminal, a second connection terminal, a first common terminal, a second capacitive structure, a third capacitive structure, a second inductive structure and a first potential terminal, the second capacitive structure and the first common terminal are arranged on a coupling path between the first connection terminal and the second connection terminal, the third capacitive structure is arranged on a coupling path between the first common terminal and the first potential terminal, and the second inductive structure is arranged on a coupling path between the second capacitive structure and the first potential terminal; the frequency response of the second band-stop module has an attenuation pole; the branch module comprises a third connection terminal, a second A potential terminal, a third band-stop module and at least one fourth capacitive structure; the third band-stop module includes a fifth capacitive structure and a third inductive structure coupled in parallel with the fifth capacitive structure; the frequency response of the third band-stop module has an attenuation pole; the fourth capacitive structure is configured on a coupling path between the third connection terminal and the third band-stop module, or configured on a coupling path between the second potential terminal and the third band-stop module; the frequency response of the branch module has an attenuation pole; a first signal terminal and a second signal terminal, the first signal terminal is coupled to the first band-stop module, and the second signal terminal is coupled to the second band-stop module; and a second common terminal is coupled to the third connection terminal of the branch module, and the second common terminal is configured on the coupling path between the first band-stop module and the second band-stop module.

[0007] Optionally, the first band-stop module further includes a sixth capacitive structure coupled in series with the first capacitive structure; the sixth capacitive structure is arranged on a coupling path between the first capacitive structure and the second common end. In this case, the flexibility of impedance matching of the first band-stop module is improved.

[0008] Optionally, the first band-stop module further includes a fourth inductive structure, and the fourth inductive structure is coupled in parallel with the sixth capacitive structure. In this case, the number of out-of-band transmission zeros can be further increased, which is conducive to improving the frequency selection performance of the high-density integrated interference suppression device.

[0009] Optionally, the first band-stop module further includes a seventh capacitive structure and a third potential terminal, and the seventh capacitive structure is configured on a common coupling path from the first capacitive structure to the third potential terminal and from the sixth capacitive structure to the third potential terminal. In this case, it is beneficial to improve the out-of-band roll-off, thereby improving the frequency selection performance of the high-density integrated interference suppression device.

[0010] Optionally, the first band-stop module further comprises a fifth inductive structure coupled in parallel with the seventh capacitive structure. In this case, it is beneficial to improve the out-of-band roll-off, thereby improving the frequency selection performance of the high-density integrated interference suppression device.

[0011] Optionally, the first band-stop module further includes a sixth inductive structure coupled in series with the first capacitive structure; the sixth inductive structure is arranged on a coupling path between the first capacitive structure and the second common end. In this case, the flexibility of impedance matching of the first band-stop module is improved.

[0012] Optionally, the high-density integrated interference suppression device includes two first band-stop modules, one of which is coupled to the first signal terminal, and the other is configured on the coupling path between the second band-stop module and the second signal terminal. In this case, the number of out-of-band transmission zeros can be further increased, which is conducive to improving the frequency selection performance of the high-density integrated interference suppression device.

[0013] Optionally, the second band-stop module further includes an eighth capacitive structure coupled in series with the second capacitive structure; the eighth capacitive structure and the second capacitive structure are respectively configured on a coupling path between the first connection end and the first common end and a coupling path between the second connection end and the first common end. In this case, the flexibility of impedance matching of the second band-stop module is improved.

[0014] Optionally, the second band-stop module further includes a seventh inductive structure coupled in series with the second capacitive structure; the seventh inductive structure is arranged on a coupling path between the second connection terminal and the first common terminal. In this case, the flexibility of impedance matching of the second band-stop module is improved.

[0015] Optionally, the second band-stop module further includes an eighth inductive structure coupled in parallel with the third capacitive structure. In this case, it is beneficial to improve the out-of-band roll-off, thereby improving the frequency selection performance of the high-density integrated interference suppression device.

[0016] Optionally, the high-density integrated interference suppression device includes two branch modules, wherein the third connection end of one branch module is coupled to the second common end; the third connection end of the other branch module is coupled to the third common end, and the third common end is configured on the coupling path between the first signal end and the first band-stop module, or configured on the coupling path between the second signal end and the second band-stop module. In this case, the number of out-of-band transmission zeros can be further increased, which is conducive to improving the frequency selection performance of the high-density integrated interference suppression device.

[0017] Optionally, the branch module further includes a ninth inductive structure coupled in series with the fourth capacitive structure; the ninth inductive structure is configured on a coupling path between the third connection terminal and the second potential terminal. In this case, the number of out-of-band transmission zeros can be further increased, which is beneficial to improving the frequency selection performance of the high-density integrated interference suppression device.

[0018] The band-stop module can be formed in a matrix formed by a dielectric layer, including the following cases:

[0019] Optionally, at least a portion of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is formed inside or on the surface of the first substrate, and the first substrate includes one or more dielectric layers arranged along a stacking direction.

[0020] Optionally, the first substrate is formed of any one or more of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide and polyimide.

[0021] Optionally, the high-density integrated interference suppression device package further includes a second substrate formed by stacking one or more dielectric layers along a stacking direction, the first substrate and the second substrate are sequentially arranged in the stacking direction, and the first substrate is fixed to the second substrate.

[0022] Optionally, the first substrate and the second substrate are electromagnetically coupled via one or more connecting members therebetween, and the connecting members include at least one of metal bumps, copper pillars, solder balls, gold wires, and solder bumps.

[0023] Optionally, at least one of the connectors is configured to be used for conductive connection. In this case, it is beneficial to conductively connect structures on different substrates.

[0024] Optionally, an electrically insulating adhesive is used to fill the space between the first substrate and the second substrate. In this case, it is beneficial to improve the bonding force between the first substrate and the second substrate.

[0025] Optionally, the first substrate is attached to the second substrate via a flip-chip solder bonding process, a copper pillar flip-chip bonding process or an anisotropic conductive film process. In this case, it is beneficial to improve the bonding strength between the first substrate and the second substrate.

[0026] Optionally, the second substrate is formed of any one or more of epoxy resin, polyester resin, polyimide (PI), organic polymer dielectric, glass fiber cloth, bismaleimide triazine resin (BT) and polyphenylene ether (PPE).

[0027] Optionally, at least a portion of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is formed on the surface or inside of the second substrate.

[0028] Optionally, at least a portion of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is formed on the surface or inside of the first substrate and the second substrate at the same time.

[0029] Optionally, the first to ninth inductive structures are at least partially formed on the surface or inside of the second substrate.

[0030] Optionally, at least part of the first to ninth inductive structures are formed on the surface or inside of the first substrate and the second substrate at the same time. In the above four cases, the module / inductive structure layout can make full use of the vertical space, can reduce the plane size required for the high-density integrated interference suppression device, and is conducive to device miniaturization.

[0031] Optionally, the high-density integrated interference suppression device further includes a third substrate formed by stacking one or more dielectric layers in a stacking direction, the third substrate is fixed to the second substrate; the first substrate, the second substrate and the third substrate are arranged in sequence in the stacking direction, the second substrate is located between the first substrate and the third substrate, and at least a portion of the first band-stop module and / or the second band-stop module and / or the branch module is formed on the surface or inside of the third substrate. In this case, the three-dimensional layout space of the structure is expanded, and the plane size required for the high-density integrated interference suppression device is reduced.

[0032] Optionally, the third substrate is formed of any one or more of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, aluminum oxide, aluminum nitride, silicon nitride and silicon oxide.

[0033] Optionally, at least a portion of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is formed on the surface or inside of the second substrate and the third substrate at the same time.

[0034] Optionally, at least a portion of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is simultaneously formed on the surface or inside of the first substrate, the second substrate and the third substrate.

[0035] Optionally, at least parts of the first to ninth inductive structures are formed on the surface or inside of the second substrate and the third substrate at the same time.

[0036] Optionally, at least part of the first to ninth inductive structures are formed on the surface or inside of the first substrate, the second substrate and the third substrate. In the above four cases, the device layout utilizes the vertical space, which can reduce the plane size required for the high-density integrated interference suppression device, which is conducive to device miniaturization.

[0037] Optionally, the capacitive structure is formed by coupling metallized electrodes. In this case, it is beneficial to realize a miniaturized capacitive structure.

[0038] Optionally, the inductive structure is formed by a metal trace extending in the form of a zigzag line, an arc, a spiral or a combination thereof.

[0039] Optionally, the inductive structure includes a plurality of metal traces formed on different dielectric layers and a plurality of metallized via pillars interconnecting the plurality of metal traces.

[0040] Optionally, the projection of the metal trace on the plane perpendicular to the stacking direction is formed to be centered at a point and arranged around the point. In this case, the plane size required for the trace is reduced by the surrounding layout.

[0041] Optionally, the inductive structure includes a plurality of metal traces formed in different dielectric layers and substantially vertically aligned.

[0042] In this case, a high-performance inductive structure can be realized by multi-layer wiring.

[0043] Optionally, each metal trace has no more than one turn.

[0044] Optionally, the first signal terminal and the first band-stop module share the same metallized electrode, and / or the second signal terminal and the second band-stop module share the same metallized electrode. In this case, the shared electrode makes the structure more compact, which is conducive to miniaturization of the device.

[0045] Optionally, the first potential end and the second potential end are at the same potential.

[0046] Optionally, the second capacitive structure, the third capacitive structure, the fourth capacitive structure and the fifth capacitive structure are all formed by coupling at least two metallized electrodes facing each other in the stacking direction, and the projections of the metallized electrodes on the plane perpendicular to the stacking direction partially overlap. In this case, it is beneficial to realize a miniaturized capacitive structure with a high quality factor.

[0047] Optionally, the second capacitive structure and the third capacitive structure share the same metallized electrode.

[0048] Optionally, the fourth capacitive structure and the fifth capacitive structure share the same metallized electrode. In the above two cases, the shared electrode makes the structure more compact, which is conducive to miniaturization of the device.

[0049] Optionally, the second inductive structure and the third capacitive structure share the same metallized electrode, and / or the second inductive structure and the first potential terminal share the same metallized electrode. In this case, the shared electrode makes the structure more compact, which is conducive to miniaturization of the device.

[0050] Optionally, the projection of the second inductive structure on the plane perpendicular to the stacking direction partially overlaps with the projection of the second capacitive structure on the plane perpendicular to the stacking direction, and / or the projection of the second inductive structure on the plane perpendicular to the stacking direction partially overlaps with the projection of the third capacitive structure on the plane perpendicular to the stacking direction. In this case, the structural layout is more compact, which is conducive to miniaturization of the device.

[0051] Optionally, the eighth capacitive structure is formed by coupling at least two metallized electrodes facing each other in the stacking direction, and the projections of the metallized electrodes on the plane perpendicular to the stacking direction partially overlap. In this case, it is beneficial to realize a miniaturized capacitive structure with a high quality factor.

[0052] Optionally, the eighth capacitive structure and the second capacitive structure share the same metallized electrode.

[0053] Optionally, the projection of the ninth inductive structure on the plane perpendicular to the stacking direction partially overlaps with the projection of the third band-stop module on the plane perpendicular to the stacking direction. In this case, the structural layout is more compact, which is conducive to miniaturization of the device.

[0054] Optionally, the first band-stop module includes a first conductor portion, a second conductor portion, a third conductor portion, a first conductive column and a second conductive column, the first conductor portion, the second conductor portion and the third conductor portion are stacked along a stacking direction, and the first conductive column and the second conductive column extend in the first substrate along the stacking direction.

[0055] Optionally, the first conductor portion is formed so that when viewed from the stacking direction, its projection on the plane perpendicular to the stacking direction is arranged around a point by at least one of a fold line, an arc line, and a spiral line around the point; the second conductor portion is arranged between the first conductor portion and the third conductor portion along the stacking direction, and the second conductor portion includes a first subsection and a second subsection with a gap between the first subsection and the first subsection; the projection of the third conductor portion on the plane perpendicular to the stacking direction partially overlaps with the projection of the second conductor portion on the plane perpendicular to the stacking direction, and there is a mutually facing relationship between the third conductor portion and the second subsection of the second conductor portion. The first capacitive structure is formed by partial coupling of the system; the projection of the first conductor part on the plane perpendicular to the stacking direction overlaps with the projection of the first capacitive structure on the plane perpendicular to the stacking direction; the first conductor part, the second conductor part and the third conductor part are composed of metallized materials; the first conductor part is coupled to the first sub-part through the first conductive column, and the first conductor part is coupled to the second sub-part through the second conductive column, and the first sub-part is conductively connected to the third conductor part; the first conductor part, the first capacitive structure, the first conductive column, the second conductive column, the first sub-part and the coupling path therebetween form a three-dimensional structure. In this case, the first band-stop module is formed into a three-dimensional structure, which is conducive to achieving a higher quality factor than the traditional planar band-stop module, thereby facilitating lower insertion loss and higher frequency selectivity, while reducing the required planar size.

[0056] Optionally, the third band-stop module includes a fourth conductor portion, a fifth conductor portion, a sixth conductor portion, a third conductive column and a fourth conductive column, the fourth conductor portion, the fifth conductor portion and the sixth conductor portion are stacked along a stacking direction, and the third conductive column and the fourth conductive column extend in the first substrate along the stacking direction.

[0057] Optionally, the fourth conductor portion is formed so that when viewed from the stacking direction, its projection on the plane perpendicular to the stacking direction is centered on a point and is surrounded by at least one of a broken line, an arc line, and a spiral line; the fifth conductor portion is arranged between the fourth conductor portion and the sixth conductor portion along the stacking direction; the projection of the sixth conductor portion on the plane perpendicular to the stacking direction and the projection of the fifth conductor portion on the plane perpendicular to the stacking direction at least partially overlap, and there is a partial coupling between the sixth conductor portion and the fifth conductor portion that is facing each other to form a fifth capacitive structure; the projection of the fourth conductor portion on the plane perpendicular to the stacking direction and the projection of the fifth capacitive structure on the plane perpendicular to the stacking direction partially overlap; the fourth conductor portion, the fifth conductor portion and the sixth conductor portion are formed of metallized material; the fourth conductive portion is coupled to the fifth capacitive structure through the third conductive column and the fourth conductive column, and the fourth conductor portion, the fifth capacitive structure, the third conductive column and the fourth conductive column and the coupling path therebetween form a three-dimensional structure in the first substrate. In this case, the third band-stop module is formed into a three-dimensional structure, which is conducive to achieving a higher quality factor than a traditional planar band-stop module, thereby facilitating lower insertion loss and higher frequency selectivity while reducing the required planar size.

[0058] According to another aspect of the present invention, there is provided an electronic device, comprising the high-density integrated interference suppression device described in any embodiment of the present invention.

[0059] The high-density integrated interference suppression device disclosed in the present invention is based on the first band-stop module, the second band-stop module and the branch module with attenuation poles in the frequency response. By configuring the internal circuit structure of each module and the coupling between them, the frequency response of the high-density integrated interference suppression device has at least three out-of-band transmission zeros, which is conducive to achieving high out-of-band noise suppression and has excellent frequency selection performance. The first band-stop module and the third band-stop module are based on a three-dimensional structure, which is easy to achieve a smaller size than the traditional planar band-stop unit, which is conducive to improving the miniaturization performance of the device, and has a higher quality factor than the traditional planar band-stop structure, which is conducive to achieving high roll-off and high noise suppression performance. The high-density integrated interference suppression device has a compact layout and outstanding miniaturization performance. By arranging the first substrate, the second substrate and the third substrate in the stacking direction, and forming the structure on different substrates, the vertical space is effectively utilized, and the plane size occupied by the device is greatly reduced, so that the high-density integrated interference suppression device has the advantage of easy integration, which is very suitable for the application scenario of high-performance and high-integration radio frequency systems.

[0060] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings required for the description of the embodiments or the conventional technology are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Note that the relative sizes of the following drawings may not be drawn to scale.

[0062] Figure 1 is a schematic diagram of an equivalent circuit of a high-density integrated interference suppression device provided by an embodiment of the present invention;

[0063] Figure 2 is a schematic diagram of an equivalent circuit of a high-density integrated interference suppression device provided by another embodiment of the present invention;

[0064] Figure 3 is a schematic diagram of an equivalent circuit of a high-density integrated interference suppression device provided by another embodiment of the present invention;

[0065] Figure 4 1 is a schematic structural diagram of a first band-stop module 101 of a high-density integrated interference suppression device 107 provided in an embodiment of the present invention;

[0066] Figure 5 1 is a schematic structural diagram of a branch module 109 and a branch module 110 of a high-density integrated interference suppression device 107 provided in an embodiment of the present invention;

[0067] Figure 6 yes Figure 5 a see-through top view of the structure shown;

[0068] Figure 7 yes Figure 5 a side view of the structure shown;

[0069] Figure 8 A schematic structural diagram of a first substrate 10 and a second substrate 11 of an interference suppression device in a modified example is shown;

[0070] Fig. 9 A schematic structural diagram of a second band-stop module 108 of a high-density integrated interference suppression device 107 provided in an embodiment of the present invention is shown;

[0071] Fig.10 It shows a schematic diagram of the overall structure of a high-density integrated interference suppression device 107 provided in an embodiment of the present invention;

[0072] Fig.11 yes Fig.10 a see-through top view of the structure shown;

[0073] Fig.12yes Fig.10 Schematic diagram of the reflection and attenuation characteristics of the structure shown;

[0074] Fig.13 A structural side view of another embodiment of the present invention is shown;

[0075] Fig.14 is a schematic diagram of an equivalent circuit of a high-density integrated interference suppression device 112 provided by another embodiment of the present invention;

[0076] Fig.15 Schematic diagram of various electronic devices that can integrate the high-density integrated interference suppression device provided by the embodiments of the present invention. DETAILED DESCRIPTION

[0077] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0079] It should be understood that when an element or layer is referred to as being "on," "connected to," other elements or layers, it may be directly on or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of the present invention, the first module, component, region, layer, or portion discussed below may be represented as a second module, component, region, layer, or portion; for example, a first direction may be referred to as a second direction, and similarly, a second direction may be referred to as a first direction; the first direction and the second direction are different directions.

[0080] Spatially relative terms such as "disposed on," "located above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "disposed on," "located above," will be oriented "below" the other elements or features. Therefore, the exemplary terms "disposed on" and "located above" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0081] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0082] Embodiments of the invention are described herein with reference to schematic diagrams that are idealized embodiments (and intermediate structures) of the invention, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0083] The embodiment of the present invention provides a high-density integrated interference suppression device. Figure 1 is a schematic diagram of an equivalent circuit of a high-density integrated interference suppression device provided by an embodiment of the present invention, with reference to Figure 1The high-density integrated interference suppression device 100 includes a first band-stop module 101, a second band-stop module 102, a branch module 103, a first signal terminal P1, a second signal terminal P2, and a second common terminal P3. The first band-stop module 101 includes a first capacitive structure C1 and a first inductive structure G1 coupled in parallel with the first capacitive structure C1. The frequency response of the first band-stop module 101 has an attenuation pole. The second band-stop module 102 includes a first connection terminal P5, a second connection terminal P6, a first common terminal P7, a second capacitive structure C2, a third capacitive structure C3, a second inductive structure G2, and a first potential terminal P8. The second capacitive structure C2 and the first common terminal P7 are arranged on a coupling path between the first connection terminal P5 and the second connection terminal P6, the third capacitive structure C3 is arranged on a coupling path between the first common terminal P7 and the first potential terminal P8, and the second inductive structure G2 is arranged on a coupling path between the second capacitive structure C2 and the first potential terminal P8. The frequency response of the second band-stop module 102 has an attenuation pole. The branch module 103 includes a third connection terminal P9, a second potential terminal P10, a third band-stop module 105 and a fourth capacitive structure C4. The third band-stop module 105 includes a fifth capacitive structure C5 and a third inductive structure G3 coupled in parallel with the fifth capacitive structure C5. The frequency response of the third band-stop module 105 has an attenuation pole. The fourth capacitive structure C4 is configured on the coupling path between the second potential terminal P10 and the third band-stop module 105. The frequency response of the branch module 103 has an attenuation pole. The first signal terminal P1 is coupled to the first band-stop module 101, and the second signal terminal P2 is coupled to the second band-stop module 102. The third connection terminal P9 of the branch module 103 is coupled to the second common terminal P3, and the second common terminal P3 is configured on the coupling path between the first band-stop module 101 and the second band-stop module 102. The first capacitive structure C1, the second capacitive structure C2, the third capacitive structure C3, the fourth capacitive structure C4, and the fifth capacitive structure C5 are shown as reactance capacitance within the working frequency band of the interference suppression device 100. The first inductive structure G1, the second inductive structure G2, and the third inductive structure G3 are shown as reactance inductance within the working frequency band of the interference suppression device 100. The frequency response of the high-density integrated interference suppression device 100 has three out-of-band transmission zeros, which is conducive to achieving high out-of-band suppression and has excellent frequency selection performance.

[0084] In addition, the fourth capacitive structure C4 may also be configured on the coupling path between the third connection terminal P9 and the third band-stop module 105 .

[0085] Furthermore, the interference suppression device 100A of another embodiment of the high-density integration includes a second branch module 104 and a third common terminal P4. Figure 2, the branch module 104 includes a third connection terminal P11, a second potential terminal P12, a third band-stop module 106 and a fourth capacitive structure C6. The third band-stop module 106 includes a fifth capacitive structure C7 and a third inductive structure G4 coupled in parallel with the fifth capacitive structure C7. The frequency response of the third band-stop module 106 has an attenuation pole. The fourth capacitive structure C6 is configured on the coupling path between the second potential terminal P12 and the third band-stop module 106. The frequency response of the branch module 104 has an attenuation pole. The third connection terminal P11 of the branch module 104 is coupled with the third common terminal P4, and the third common terminal P4 is configured on the coupling path between the second signal terminal P2 and the second band-stop module 102. The fourth capacitive structure C6 and the fifth capacitive structure C7 behave as reactance capacitance within the working frequency band of the interference suppression device. The third inductive structure G4 behaves as reactance inductance within the working frequency band of the interference suppression device. The frequency response of the high-density integrated interference suppression device 100A has four out-of-band transmission zeros.

[0086] In addition, the third common terminal P4 may also be configured on the coupling path between the first signal terminal P1 and the first band-stop module 101 .

[0087] In another embodiment of the present invention, referring to Figure 3, shows an equivalent circuit diagram of a high-density integrated interference suppression device 107 provided in an embodiment. The high-density integrated interference suppression device 107 comprises a first band-stop module 101, a second band-stop module 108, a branch module 109, a branch module 110, a first signal terminal P1, a second signal terminal P2, a second common terminal P3, and a third common terminal P4. The first band-stop module 101 comprises a first capacitive structure C1 and a first inductive structure G1 coupled in parallel with the first capacitive structure C1, and the frequency response of the first band-stop module 101 has an attenuation pole. The second band-stop module 108 includes a first connection terminal P5, a second connection terminal P6, a first common terminal P7, a second capacitive structure C2, a third capacitive structure C3, an eighth capacitive structure C8, a second inductive structure G2 and a first potential terminal P8. The first common terminal P7 is configured on a coupling path between the first connection terminal P5 and the second connection terminal P6. The eighth capacitive structure C8 and the second capacitive structure C2 are respectively configured on a coupling path between the second connection terminal P6 and the first common terminal P7 and a coupling path between the first connection terminal P5 and the first common terminal P7. The third capacitive structure C3 is configured on a coupling path between the first common terminal P7 and the first potential terminal P8. The second inductive structure G2 is configured on a coupling path between the second capacitive structure C2 and the first potential terminal P8. The frequency response of the second band-stop module 108 has an attenuation pole. The branch module 109 includes a third connection terminal P9, a second potential terminal P10, a third band-stop module 105, a fourth capacitive structure C4, and a ninth inductive structure G5. The third band-stop module 105 includes a fifth capacitive structure C5 and a third inductive structure G3 coupled in parallel with the fifth capacitive structure C5. The frequency response of the third band-stop module 105 has an attenuation pole. The fourth capacitive structure C4 is configured on the coupling path between the second potential terminal P10 and the third band-stop module 105, and the ninth inductive structure G5 is configured on the coupling path between the second potential terminal P10 and the third band-stop module 105. The frequency response of the branch module 109 has an attenuation pole. The branch module 110 includes a third connection terminal P11, a second potential terminal P12, a third band-stop module 106, a fourth capacitive structure C6, and a ninth inductive structure G6. The third band-stop module 106 includes a fifth capacitive structure C7 and a third inductive structure G4 coupled in parallel with the fifth capacitive structure C7. The frequency response of the third band-stop module 106 has an attenuation pole. The fourth capacitive structure C6 is configured on the coupling path between the second potential terminal P12 and the third band-stop module 106, and the ninth inductive structure G6 is configured on the coupling path between the second potential terminal P12 and the third band-stop module 106. The frequency response of the branch module 110 has an attenuation pole. The first signal terminal P1 is coupled to the first band-stop module 101, and the second signal terminal P2 is coupled to the second band-stop module 108. The third connection terminal P9 of the branch module 109 is coupled to the second common terminal P3, and the second common terminal P3 is configured on the coupling path between the first band-stop module 101 and the second band-stop module 108.The third connection terminal P11 of the branch module 110 is coupled to the third common terminal P4, and the third common terminal P4 is configured on the coupling path between the second signal terminal P2 and the second band-stop module 108. The first capacitive structure C1, the second capacitive structure C2, the third capacitive structure C3, the fourth capacitive structure C4, the fifth capacitive structure C5, the fourth capacitive structure C6, the fifth capacitive structure C7, and the eighth capacitive structure C8 all show reactance capacitance within the working frequency band of the high-density integrated interference suppression device 107. The first inductive structure G1, the second inductive structure G2, the third inductive structure G3, the third inductive structure G4, the ninth inductive structure G5, and the ninth inductive structure G6 all show reactance inductance within the working frequency band of the high-density integrated interference suppression device 107. In addition, in other embodiments or variations, the third common terminal P4 may also be configured on the coupling path between the first signal terminal P1 and the first band-stop module 101, and the ninth inductive structure G5 / G6 may also be configured on the coupling path between the third connection terminal and the third band-stop module.

[0088] Figure 4 1 is a schematic diagram of the structure of the first band-stop module 101 of the high-density integrated interference suppression device 107. Figure 4, the first direction x, the second direction y and the stacking direction z are perpendicular to each other. Part of the structure of the first band-stop module 101 is formed on the surface of the first substrate 10 and inside the first substrate 10. The first substrate 10 is formed by stacking dielectric layers along the stacking direction z, wherein the dielectric layers can be formed by any one or more of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, polyimide or a combination thereof. The first band-stop module 101 includes a first conductor part M1, a second conductor part M2, a third conductor part M3, a first conductive pillar V1 and a second conductive pillar V2. The first conductor part M1, the second conductor part M2 and the third conductor part M3 are arranged in sequence in the stacking direction z, and the first conductive pillar V1 and the second conductive pillar V2 extend in the first substrate 10 along the stacking direction z. The first conductor part M1, the second conductor part M2, and the third conductor part M3 can be formed of one or more metallized materials such as Ag, Au, and Cu. The first conductive pillar V1 and the second conductive pillar V2 can be formed of through holes formed of one or more metallized materials such as Ag, Au, and Cu, or can be formed of solid pillars formed of one or more metallized materials such as Ag, Au, and Cu. The first conductor part M1 is formed on the upper surface of the first substrate 10, and is formed to be arranged around a point in a zigzag line or a spiral line. The two ends of the first conductor part M1 are respectively connected to the first conductive pillar V1 and the second conductive pillar V2. The second conductor part M2 is formed in the first substrate 10, and includes a first sub-portion M21 and a second sub-portion M22 with a gap from the first sub-portion. The first sub-portion M21 is coupled to the first conductor part M1 through the first conductive pillar V1, and the second sub-portion M22 is coupled to the first conductor part M1 through the second conductive pillar V2. The third conductor part M3 is formed in the first substrate 10, and the projection of the plane perpendicular to the stacking direction z partially overlaps with the projection of the second conductor part M2 on the plane perpendicular to the stacking direction z. The third conductor part M3 and the second sub-part M22 are partially coupled in a mutually facing relationship to form the first capacitive structure C1. The first sub-part M21 is conductively connected to the third conductor part M3 through a conductor. The first band-stop module 101 forms a three-dimensional structure, and is formed into a three-dimensional band-stop functional unit by configuring conductor parts on different planes and conducting columns extending along the stacking direction. It is easy to achieve a smaller size than a planar structure, which is conducive to the miniaturization of the filter device. On the other hand, it is easy to achieve a higher quality factor, which is conducive to achieving excellent out-of-band noise suppression.

[0089] Please continue to refer to Figure 4 The first conductor portion M1 is formed above the first capacitive structure C1, and its projection on a plane perpendicular to the stacking direction z partially overlaps with the projection of the first capacitive structure C1 on a plane perpendicular to the stacking direction Z. This structure can reduce the layout size and is conducive to the miniaturization of the device.

[0090] Figure 5The schematic diagram of the structure of the branch module 109 and the branch module 110 of the high-density integrated interference suppression device 107 provided by the embodiment of the present invention is shown. The first direction x, the second direction y and the stacking direction z are perpendicular to each other. The third band-stop module 105 in the branch module 109 includes a fourth conductor part M4, a fifth conductor part M5, a sixth conductor part M6, a third conductive column V3 and a fourth conductive column V4. The fourth conductor part M4, the fifth conductor part M5 and the sixth conductor part M6 are arranged in sequence in the stacking direction z, and the third conductive column V3 and the fourth conductive column V4 extend along the stacking direction z in the first substrate 10. The fourth conductor part M4, the fifth conductor part M5 and the sixth conductor part M6 can be formed of one or more metallized materials such as Ag, Au, Cu, etc. The third conductive column V3 and the fourth conductive column V4 can be formed of through holes formed of one or more metallized materials such as Ag, Au, Cu, etc., or can be formed of solid columns formed of one or more metallized materials such as Ag, Au, Cu, etc. The fourth conductor portion M4 is formed on the upper surface of the first substrate 10, and is formed to be arranged around a point in the form of a zigzag line and a spiral. The two ends of the fourth conductor portion M4 are respectively connected to the third conductive column V3 and the fourth conductive column V4. The fifth conductor portion M5 is formed in the first substrate 10, located below the fourth conductor portion M4, and is coupled to the fourth conductor portion M4 through the third conductive column V3. The sixth conductor portion M6 is formed in the first substrate 10, located below the fifth conductor portion M5, and the projection of the surface perpendicular to the stacking direction z partially overlaps with the projection of the fifth conductor portion M5 on the surface perpendicular to the stacking direction z. The sixth conductor portion M6 is coupled to the fourth conductor portion M4 through the fourth conductive column V4 and the metallized electrode E1. The fifth conductor portion M5 and the sixth conductor portion M6 are partially coupled in a mutually facing relationship to form a fifth capacitive structure C5. A portion of the fourth conductor portion M4 is arranged directly above the fifth capacitive structure C5, and the projection of the fourth conductor portion M4 on the plane perpendicular to the stacking direction z overlaps with the projection of the fifth capacitive structure C5 on the plane perpendicular to the stacking direction Z. The metallized electrode E2 is formed below the fifth conductor portion M5, and the fifth conductor portion M5 and the electrode E2 are partially coupled to form the fourth capacitive structure C4. The fourth capacitive structure C4 and the fifth capacitive structure C5 share the fifth conductor portion M5, that is, the fourth capacitive structure and the third band-stop module share the same metallized electrode. A portion of the ninth inductive structure G5 is formed inside the first substrate 10, and is conductively connected to the fourth capacitive structure C4, and shares the same metallized electrode E2. Another portion of the ninth inductive structure G5 is formed on the surface of the second substrate 11, and is formed in the form of a broken line extending from a point and bending multiple times. It is conductively connected to the portion of the ninth inductive structure G5 formed on the first substrate 10 through a solder bump, and can also be connected through a metal conductor with a structural support effect such as a copper column, a BGA ball, or a gold ball. The second potential terminal P10 is formed at the end of the ninth inductive structure G5.The second substrate 11 is located below the first substrate 10 along the stacking direction z, and is formed by stacking a plurality of bismaleimide triazine resin (BT) dielectric layers along the stacking direction z. In addition, the second substrate may also be composed of a dielectric layer, wherein the dielectric layer may also be formed of any one or more of epoxy resin, polyester resin, polyimide (PI), organic polymer dielectric, glass fiber cloth, polyphenylene ether (PPE) or a combination thereof.

[0091] The third band-stop module 106 in the branch module 110 includes a fourth conductor portion M7, a fifth conductor portion M8, a sixth conductor portion M9, a third conductive column V5 and a fourth conductive column V6. The fourth conductor portion M7, the fifth conductor portion M8 and the sixth conductor portion M9 are arranged in sequence in the stacking direction z, and the third conductive column V5 and the fourth conductive column V6 extend along the stacking direction z in the first substrate 10. The fourth conductor portion M7, the fifth conductor portion M8 and the sixth conductor portion M9 can be formed of one or more metallized materials such as Ag, Au, and Cu, and the third conductive column V5 and the fourth conductive column V6 can be formed of a through hole formed of one or more metallized materials such as Ag, Au, and Cu, or can be formed of a solid column formed of one or more metallized materials such as Ag, Au, and Cu. The fourth conductor portion M7 is formed on the upper surface of the first substrate 10, and is formed to be arranged around a point in the form of a folded line and a spiral, and the two ends are respectively connected to the third conductive column V5 and the fourth conductive column V6. The fifth conductor portion M8 is formed in the first substrate 10, located below the fourth conductor portion M7, and coupled to the fourth conductor portion M7 through the third conductive pillar V5. The sixth conductor portion M9 is formed in the first substrate 10, located below the fifth conductor portion M8, and the projection of the surface perpendicular to the stacking direction z partially overlaps with the projection of the fifth conductor portion M8 on the surface perpendicular to the stacking direction z. The sixth conductor portion M9 is coupled to the fourth conductor portion M7 through the fourth conductive pillar V6 and the electrode E3. The fifth conductor portion M8 and the sixth conductor portion M9 are partially coupled in a facing relationship to form a fifth capacitive structure C7. At this time, the fourth conductor portion M7, the third conductive pillar V5, the fourth conductive pillar V6 and a part of the fifth conductor portion M8 constitute a third inductive structure G4 coupled in parallel with the fifth capacitive structure C7.

[0092] The electrode E4 is formed below the fifth conductor portion M8, and the fifth conductor portion M8 and the electrode E4 are partially coupled in a facing relationship to form a fourth capacitive structure C6. The fourth capacitive structure C6 and the fifth capacitive structure C7 share the fifth conductor portion M8, that is, the fourth capacitive structure and the third band-stop module share the same metallized electrode. A portion of the ninth inductive structure G6 is formed inside the first substrate 10, one end of which is coupled to the electrode E4 through the fifth conductive column V7, forming a shape extending from one point in the form of a broken line and bending multiple times, and the other end is conductively connected to another portion of the surface of the second substrate 11 formed by the ninth inductive structure G6 through the conductive column V8, the electrode E5 and the solder bump. The fifth conductive column V7 and the conductive column V8 extend in the first substrate 10 along the stacking direction z. The second potential terminal P12 is formed at the end of the ninth inductive structure G6, and is equipotential with the second potential terminal P10, and is also equipotential with the reference ground. The two parts of the ninth inductive structure G6 formed on different substrates can also be connected by metal conductors with structural support effects such as copper pillars, BGA balls, and gold balls. The metallized electrodes E1-E4 are formed of copper, and can be formed of one or more metallized materials such as gold, silver, and nickel. The solder bump can be formed of materials such as Sn, Pb, Ag, and Ni. Taking port Port1 and port Port2 as ports formed on the ninth inductive structure G5 / G6, the relationship between the voltage and current between ports Port1 and Port2 can be represented by the admittance matrix [Y]', and the imaginary part of Y11 in the admittance matrix [Y]' is less than zero. The ninth inductive structure G5 / G6 exhibits reactance inductance within the working frequency band. In addition, the ninth inductive structure G5 / G6 can also be formed by different multiple metal conductors distributed in the second substrate 11 and arranged along the stacking direction z, and the above multiple different layers of metal conductors can be conductively interconnected through vertical conductive structures such as conductive pillars.

[0093] like Figure 6 As shown, the projection of the ninth inductive structure G5 on the plane perpendicular to the stacking direction z partially overlaps with the projection of the third band-stop module 105 on the plane perpendicular to the stacking direction. The projection of the ninth inductive structure G6 on the plane perpendicular to the stacking direction z partially overlaps with the projection of the fourth capacitive structure C6 on the plane perpendicular to the stacking direction z. The projection of the first substrate 10 on the plane perpendicular to the stacking direction z at least partially overlaps with the projection of the second substrate 11 on the plane perpendicular to the stacking direction z.

[0094] The third band-stop module 105 and the third band-stop module 106 are formed into a three-dimensional structure, and a three-dimensional band-stop functional unit is formed by forming conductor parts on different planes and conductive columns extending along the stacking direction. It is easy to achieve a smaller size than a planar structure, which is beneficial to the miniaturization of the filter device. On the other hand, it is easy to achieve a higher quality factor, which is beneficial to achieve excellent out-of-band noise suppression.

[0095] Figure 7 Shows Figure 5 Side view of the structure shown. Figure 7 , the first substrate 10 is fixed on the second substrate 11 by a plurality of solder bumps through a flip-chip solder bonding process. The first substrate 10 can be electromagnetically coupled with the second substrate 11 by using solder bumps as connectors. Some of these solder bumps are configured to be used for the ninth inductive structure G5 / G6 to be arranged between structures of different substrates for conductive connection. Some of the solder bumps are used for fixing, but are not configured to be used as conductive connections. In addition, the first substrate 10 can also be connected to the second substrate 11 by a plurality of copper pillars through a copper pillar flip-chip bonding process; or it can be tightly attached to the second substrate 11 using an organic adhesive through an anisotropic conductive film process.

[0096] Figure 8 FIG. 1 is a schematic structural diagram of a first substrate 10 and a second substrate 11 of an interference suppression device of a modified example. Figure 8 The first substrate 10 is fixed to the second substrate 11, and a plurality of copper pillars are used as connectors to make the first substrate 10 and the second substrate 11 electromagnetically coupled. Epoxy resin is filled between the first substrate 10 and the second substrate 11, which can enhance the bonding force between the substrates after curing, which is conducive to making the device structure more solid. In addition, the first substrate and the second substrate can also be filled with an insulating adhesive such as silicone or polyurethane.

[0097] Fig. 9The schematic diagram of the structure of the second band-stop module 108 of the high-density integrated interference suppression device 107 provided by an embodiment of the present invention is shown. The first direction x, the second direction y and the stacking direction z are perpendicular to each other. The second capacitive structure C2 includes electrodes E6, E7, E8 and E9, wherein electrode E7 is formed below electrode E6, electrode E7 and electrode E6 face each other and their projections on the plane perpendicular to the stacking direction z overlap, electrode E8 is formed above electrode E7, electrode E8 is not connected to electrode E6, electrode E8 and electrode E7 face each other and their projections on the plane perpendicular to the stacking direction overlap, electrode E9 is located below electrode E8 and is formed into a bent shape, electrode E9 and electrode E8 face each other and their projections on the plane perpendicular to the stacking direction z overlap. There is a gap between the overlapping part of the projections of electrodes E8 and E7 on the plane perpendicular to the stacking direction and the overlapping part of the projections of electrodes E8 and E9 on the plane perpendicular to the stacking direction. Electrode E6, electrode E7, electrode E8 and electrode E9 are coupled through a dielectric layer therebetween to form a second capacitive structure C2. Electrode E6, electrode E7, electrode E8 and electrode E9 can be formed of one or more metallized materials such as Ag, Au, Cu, etc. The first connection terminal P5 is formed on electrode E6 and shares the same metallized electrode with the second capacitive structure C2. The eighth capacitive structure C8 includes electrode E9, electrode E10 and electrode E11. Electrode E10 is formed above electrode E9. Electrode E10 is not connected to electrode E8. Electrode E10 and electrode E9 face each other and their projections on a plane perpendicular to the stacking direction z overlap. Electrode E11 is formed below electrode E10. Electrode E11 is not connected to electrode E9. Electrode E11 and electrode E10 face each other and their projections on a plane perpendicular to the stacking direction z overlap. Electrode E9, electrode E10 and electrode E11 are coupled through a dielectric layer therebetween to form the eighth capacitive structure C8. The third capacitive structure C3 includes an electrode E9 and an electrode E12. The electrode E12 is located above the electrode E9 and is not connected to the electrode E8 and the electrode E11. The electrode E12 and the electrode E9 face each other and their projections on the plane perpendicular to the stacking direction z overlap. The electrode E9 and the electrode E12 are coupled through the dielectric layer therebetween to form the third capacitive structure C3. The electrode E10, the electrode E11 and the electrode E12 can be formed of one or more metallized materials such as Ag, Au, Cu, etc. The eighth capacitive structure C8, the second capacitive structure C2 and the third capacitive structure C3 share the same electrode E9. The first common terminal P7 is formed on the electrode E9. The second connection terminal P6 is formed on the electrode E11 and shares the same metallized electrode with the eighth capacitive structure C8. The third capacitive structure C3 is coupled to the second inductive structure G2 through the electrode E13 and the solder bump. The second inductive structure G2 is formed in the second substrate 11, and is formed by a plurality of metal conductors of different dielectric layers, which are sequentially arranged along the stacking direction z and conductively interconnected. The plurality of metal conductors are formed by a fold line extending around a point and being bent multiple times.With port Port3 and port Port4 as ports formed on the second inductive structure G2, the relationship between the voltage and current between port Port3 and port4 can be represented by the admittance matrix [Y]', the imaginary part of Y33 in the admittance matrix [Y]' is less than zero, and the second inductive structure G2 exhibits reactance inductance within the working frequency band. The first potential terminal P8 is formed at the end of the second inductive structure G2, and has the same potential as the second potential terminal P10 and the second potential terminal P12. In other embodiments or variations, the second inductive structure G2 can also be formed by extending from a point by a straight line, a broken line, an arc, a spiral or a combination thereof. In addition, the second inductive structure G2 can also be formed in the first substrate 10, extending outward from one end of the electrode E12 of the third capacitive structure C3, and at this time, the second inductive structure G2 and the third capacitive structure C3 share the same metallized electrode E12.

[0098] Fig.10 FIG. 1 shows a schematic diagram of the overall structure of a high-density integrated interference suppression device 107 provided in an embodiment of the present invention, referring to FIG. Fig.10 , wherein the first direction x, the second direction y and the stacking direction z are perpendicular to each other. Figure 4 and Fig. 9 , the second subsection M22 of the first band-stop module 101 is connected to the electrode E6 of the second band-stop module 108, so that the first band-stop module 101 is coupled to the second band-stop module 108. Figure 5 and Fig. 9, the sixth conductor portion M6 of the branch module 109 is connected to the electrode E6 of the second band-stop module 108, so that the branch module 109 is coupled with the second band-stop module 108. The branch module 109 and the first band-stop module 101 are arranged in sequence along the second direction y. The electrode E11 of the second band-stop module 108 and the sixth conductor portion M9 of the branch module 110 are conductively interconnected to form the same electrode, and the second band-stop module 108 is coupled with the branch module 110. The branch module 110, the first band-stop module 101, and the branch module 109 are arranged in sequence along the first direction x, and the first band-stop module 101, the second band-stop module 108, and the branch module 109 are located on the same side of the branch module 110. Observed from the stacking direction z, the first band-stop module 101, the third band-stop module 105 of the branch module 109, the third band-stop module 106 of the branch module 110 and the ninth inductive structure G6 of the branch module 110 are respectively arranged in the upper left, lower left, upper right and lower right regions of the first substrate 10. The eighth capacitive structure C8, the second capacitive structure C2 and the third capacitive structure C3 of the second band-stop module 108 are sandwiched between the branch module 110 and the branch module 109. The first signal terminal P1 is formed on the third conductor portion M3, coupled with the first band-stop module 101 and shares the same metallized electrode. The second signal terminal P2 is formed on the sixth conductor portion M9 of the branch module, and is further conductively connected to the electrode E11 of the second band-stop module 108, and the second signal terminal P2 is coupled with the second band-stop module 108.

[0099] Fig.11 yes Fig.10 A through-view top view of the structure shown, see Fig.11 Combined with Fig.10 , from the second substrate 11 to the first substrate 10, the projections of the second inductive structure G2 and the first band-stop module 101 on the plane perpendicular to the stacking direction z overlap, the projections of the second inductive structure G2 and the branch module 109 on the plane perpendicular to the stacking direction z overlap, and the projections of the second inductive structure G2 and the branch module 110 on the plane perpendicular to the stacking direction z overlap. The high-density integrated interference suppression device 107 has a compact internal structure and outstanding miniaturization performance.

[0100] Reference Fig.12 The high-density integrated interference suppression device 107 provided in this embodiment is based on the first band-stop module 101, the second band-stop module 108, the branch module 109 and the branch module 110 having attenuation poles in the frequency response. By setting the internal circuit structure of each module and the coupling relationship between the adjustment modules, the frequency response characteristics of six out-of-band transmission zero points (TZ1~TZ6) are realized, and the device has high out-of-band noise suppression and excellent frequency selection performance.

[0101] In addition, in the high-density integrated interference suppression device 107 provided in this embodiment, the first band-stop module 101 may further include a sixth inductive structure G7 coupled in series with the first capacitive structure C1, and the sixth inductive structure G7 is configured on the coupling path between the first capacitive structure C1 and the second common terminal P3. By introducing the sixth inductive structure G7 and adjusting its equivalent reactance inductance in the coupling path, it is beneficial to flexibly adjust the impedance matching of the first band-stop module.

[0102] In addition, in the high-density integrated interference suppression device 107 provided in this embodiment, the eighth capacitive structure C8 in the second band-stop module 108 can be replaced by the seventh inductive structure G8, which can be designed to provide a certain reactance value in certain scenarios requiring impedance conjugate matching, which is conducive to improving the flexibility of the second band-stop module for external impedance matching. In this case, the seventh inductive structure G8 can be formed as a metallized conductor extending from a point by one of a straight line, a broken line, an arc, a spiral, or a combination thereof. The seventh inductive structure G8 is conductively connected to the second connection terminal P6 or the first common terminal P6, and can also share the same metallized electrode with the second connection terminal P6 or the first common terminal P6.

[0103] Based on the above embodiments, another embodiment of the present invention further includes a third substrate 12. Fig.13 The high-density integrated interference suppression device 111 comprises a first substrate 10, a second substrate 11 and a third substrate 12. The third substrate 12 is formed by stacking dielectric layers along a stacking direction z, wherein the dielectric layers can be formed by any one or more of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, polyimide or a combination thereof. The first substrate 10 and the third substrate 12 are fixed on different sides of the second substrate 11, so that the first substrate 10, the second substrate 11 and the third substrate 12 are arranged in sequence in the stacking direction z, and the second substrate 11 is located between the first substrate 10 and the third substrate 12. Copper pillars are used as connectors between the second substrate 11 and the third substrate 12. Epoxy resin is filled between the first substrate 10 and the second substrate 11, and insulating glue is filled between the second substrate 11 and the third substrate 12 to improve the bonding strength of the entire structure. The branch module is arranged on the third substrate 12, and the circuit structure in the third substrate 13 can be coupled with the circuit structure in the first substrate 10 through the multi-layer wiring or metallized conductive pillars in the second substrate 11. Most of the third substrate 12 is arranged within the vertical perimeter of the first substrate 10, so that the projection of the third substrate 12 on the plane perpendicular to the stacking direction z at least partially overlaps with the projection of the first substrate 10 on the plane perpendicular to the stacking direction z, which is conducive to further miniaturization of the device plane size.

[0104] On the basis of the above embodiments, in a high-density integrated interference suppression device 112 in another embodiment of the present invention, the first band-stop module 113 further includes a fourth inductive structure G9, a sixth capacitive structure C9, a seventh capacitive structure C10, a fifth inductive structure G10, an eighth inductive structure G11 and a third potential terminal P13. Fig.14 , the sixth capacitive structure C9 is connected in series with the first capacitive structure C1, and is arranged on the coupling path between the first capacitive structure C1 and the second common terminal P3. The fourth inductive structure G9 is coupled in parallel with the sixth capacitive structure C9, and is arranged on the coupling path between the first capacitive structure C1 and the second common terminal P3, and is coupled in series with the first inductive structure G1. The seventh capacitive structure C10 is configured on the common coupling path from the first capacitive structure C1 to the third potential terminal P13 and from the sixth capacitive structure C9 to the third potential terminal P13. The fifth inductive structure G10 is coupled in parallel with the seventh capacitive structure C10. The eighth inductive structure G11 is coupled in parallel with the third capacitive structure C3. The sixth capacitive structure C9 and the seventh capacitive structure C10 show reactance capacitance within the working frequency band of the interference suppression device 112. The fourth inductive structure G9, the fifth inductive structure G10 and the eighth inductive structure G11 show reactance inductance within the working frequency band of the interference suppression device 112. In this case, more out-of-band transmission zeros will be introduced, which is beneficial to further enhance the out-of-band suppression capability of the high-density integrated interference suppression device.

[0105] An embodiment of the present invention further provides an electronic device, comprising the high-density integrated interference suppression device described in any of the above embodiments.

[0106] Fig.15 Various electronic devices that can be integrated with the high-density integrated interference suppression device according to any of the above embodiments and their variations are shown. For example, a mobile phone 20, a laptop computer 21, and a fixed location terminal 22 may include a high-density integrated interference suppression device as described herein. Fig.15 The devices are merely exemplary, and other electronic devices may also include any of the high-density integrated interference suppression devices described herein, including but not limited to: music players, video players, entertainment units, global positioning system-enabled devices, navigation devices, communication devices, mobile devices, mobile phones, smart phones, personal digital assistants, fixed location terminals, tablet computers, wearable devices, servers, routers, Internet of Things devices, laptop computers, or any combination thereof.

[0107] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A high-density integrated interference suppression device, characterized in that: include: A first band-stop module, comprising a first capacitive structure and a first inductive structure coupled in parallel with the first capacitive structure, wherein a frequency response of the first band-stop module has an attenuation pole; A second band-stop module, comprising a first connection end, a second connection end, a first common end, a second capacitive structure, a third capacitive structure, a second inductive structure and a first potential end, wherein the second capacitive structure and the first common end are arranged on a coupling path between the first connection end and the second connection end, the third capacitive structure is arranged on a coupling path between the first common end and the first potential end, and the second inductive structure is arranged on a coupling path between the second capacitive structure and the first potential end; the frequency response of the second band-stop module has an attenuation pole; A branch module, wherein the branch module comprises a third connection terminal, a second potential terminal, a third band-stop module and at least one fourth capacitive structure; the third band-stop module comprises a fifth capacitive structure and a third inductive structure coupled in parallel with the fifth capacitive structure; the frequency response of the third band-stop module has an attenuation pole; the fourth capacitive structure is configured on a coupling path between the third connection terminal and the third band-stop module, or configured on a coupling path between the second potential terminal and the third band-stop module; the frequency response of the branch module has an attenuation pole; a first signal terminal and a second signal terminal, wherein the first signal terminal is coupled to the first band-stop module, and the second signal terminal is coupled to the second band-stop module; as well as, The second common end is coupled to the third connection end of the branch module, and the second common end is configured on a coupling path between the first band-stop module and the second band-stop module.

2. The high-density integrated interference suppression device according to claim 1, characterized in that: The first band-stop module further includes a sixth capacitive structure coupled in series with the first capacitive structure; the sixth capacitive structure is configured on a coupling path between the first capacitive structure and the second common end.

3. The high-density integrated interference suppression device according to claim 2, characterized in that: The first band-stop module further includes a fourth inductive structure, and the fourth inductive structure is coupled in parallel with the sixth capacitive structure.

4. The high-density integrated interference suppression device according to claim 3, characterized in that: The first band-stop module further includes a seventh capacitive structure and a third potential end, and the seventh capacitive structure is configured on a common coupling path from the first capacitive structure to the third potential end and from the sixth capacitive structure to the third potential end.

5. The high-density integrated interference suppression device according to claim 4, characterized in that: The first band-stop module further includes a fifth inductive structure coupled in parallel with the seventh capacitive structure.

6. The high-density integrated interference suppression device according to claim 1, characterized in that: The first band-stop module further includes a sixth inductive structure coupled in series with the first capacitive structure; the sixth inductive structure is arranged on a coupling path between the first capacitive structure and the second common end.

7. The high-density integrated interference suppression device according to claim 1, characterized in that: It comprises two first band-stop modules, one of which is coupled to the first signal end, and the other is arranged on a coupling path between the second band-stop module and the second signal end.

8. The high-density integrated interference suppression device according to claim 1, characterized in that: The second band-stop module further includes an eighth capacitive structure coupled in series with the second capacitive structure; the eighth capacitive structure and the second capacitive structure are respectively configured on a coupling path between the first connection end and the first common end and a coupling path between the second connection end and the first common end.

9. The high-density integrated interference suppression device according to claim 1, characterized in that: The second band-stop module further includes a seventh inductive structure coupled in series with the second capacitive structure; the seventh inductive structure is configured on a coupling path between the second connection end and the first common end.

10. The high-density integrated interference suppression device according to claim 1, characterized in that: The second band-stop module further includes an eighth inductive structure coupled in parallel with the third capacitive structure.

11. The high-density integrated interference suppression device according to claim 1, characterized in that: It comprises two branch modules, wherein the third connection end of one branch module is coupled to the second common end; the third connection end of the other branch module is coupled to the third common end, and the third common end is configured on the coupling path between the first signal end and the first band-stop module, or configured on the coupling path between the second signal end and the second band-stop module.

12. The high-density integrated interference suppression device according to claim 11, characterized in that: The branch module further includes a ninth inductive structure coupled in series with the fourth capacitive structure; the ninth inductive structure is arranged on a coupling path between the third connection terminal and the second potential terminal.

13. The high-density integrated interference suppression device according to any one of claims 1 to 12, characterized in that: At least a part of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is formed inside or on the surface of a first substrate, and the first substrate includes one or more dielectric layers arranged along a stacking direction.

14. The high-density integrated interference suppression device according to claim 13, characterized in that: The first substrate is formed of any one or more of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide and polyimide.

15. The high-density integrated interference suppression device according to claim 14, characterized in that: It also includes a second substrate formed by stacking one or more dielectric layers along the stacking direction. The first substrate and the second substrate are arranged in sequence in the stacking direction, and the first substrate is fixed to the second substrate.

16. The high-density integrated interference suppression device according to claim 15, characterized in that: The first substrate and the second substrate are electromagnetically coupled via one or more connecting members therebetween, and the connecting members include at least one of metal bumps, copper pillars, solder balls, gold wires, and solder bumps.

17. The high-density integrated interference suppression device according to claim 15, characterized in that: At least one of the connectors is configured for an electrically conductive connection.

18. The high-density integrated interference suppression device according to claim 15, characterized in that: The space between the first substrate and the second substrate is filled with an electrically insulating adhesive.

19. The high-density integrated interference suppression device according to claim 15, characterized in that: The first substrate is attached to the second substrate via a flip-chip solder bonding process, a copper pillar flip-chip bonding process, or an anisotropic conductive film process.

20. The high-density integrated interference suppression device according to claim 15, characterized in that: The second matrix is ​​formed of any one or more of epoxy resin, polyester resin, polyimide (PI), organic polymer dielectric, glass fiber cloth, bismaleimide triazine resin (BT) and polyphenylene ether (PPE).

21. The high-density integrated interference suppression device according to claim 15, characterized in that: At least a part of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is formed on the surface or inside of the second substrate.

22. The high-density integrated interference suppression device according to claim 21, characterized in that: At least a part of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is formed on the surface or inside of the first substrate and the second substrate at the same time.

23. The high-density integrated interference suppression device according to claim 21, characterized in that: At least a portion of the first to ninth inductive structures are formed on the surface or inside of the second substrate.

24. The high-density integrated interference suppression device according to claim 21, characterized in that: At least part of the structures of the first to ninth inductive structures are formed on the surface or inside of the first substrate and the second substrate at the same time.

25. The high-density integrated interference suppression device according to claim 21, characterized in that: It also includes a third substrate formed by stacking one or more dielectric layers along the stacking direction, and the third substrate is fixed to the second substrate; the first substrate, the second substrate and the third substrate are arranged in sequence along the stacking direction, the second substrate is located between the first substrate and the third substrate, and at least a part of the first band-stop module and / or the second band-stop module and / or the branch module is formed on the surface or inside of the third substrate.

26. The high-density integrated interference suppression device according to claim 25, characterized in that: The third substrate is formed of any one or more of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, diamond, indium phosphide, glass, sapphire, aluminum oxide, aluminum nitride, silicon nitride and silicon oxide.

27. The high-density integrated interference suppression device according to claim 25, characterized in that: At least a part of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is simultaneously formed on the surface or inside of the second substrate and the third substrate.

28. The high-density integrated interference suppression device according to claim 25, characterized in that: At least a part of the structure of the first band-stop module and / or the second band-stop module and / or the branch module is simultaneously formed on the surface or inside of the first substrate, the second substrate and the third substrate.

29. The high-density integrated interference suppression device according to claim 25, characterized in that: At least part of the structures of the first to ninth inductive structures are formed on the surface or inside of the second substrate and the third substrate at the same time.

30. The high-density integrated interference suppression device according to claim 25, characterized in that: At least parts of the first to ninth inductive structures are simultaneously formed on the surface or inside of the first substrate, the second substrate, and the third substrate.

31. The high-density integrated interference suppression device according to claim 13, characterized in that: The capacitive structure is formed by coupling metallized electrodes.

32. The high-density integrated interference suppression device according to claim 13, characterized in that: The inductive structure is formed by metal traces extending in the form of zigzag lines, arcs, spirals or a combination thereof.

33. The high-density integrated interference suppression device according to claim 32, characterized in that: The inductive structure includes a plurality of the metal traces formed on different dielectric layers and a plurality of metallized via pillars interconnecting the plurality of the metal traces.

34. The high-density integrated interference suppression device according to claim 32, characterized in that: The projection of the metal trace on the plane perpendicular to the stacking direction is formed to be centered at one point and to be arranged around the point.

35. The high-density integrated interference suppression device according to claim 34, characterized in that: The inductive structure includes a plurality of the metal traces formed in different dielectric layers and substantially vertically aligned.

36. The high-density integrated interference suppression device according to claim 35, characterized in that: Each of the metal traces has no more than one turn.

37. The high-density integrated interference suppression device according to claim 1, characterized in that: The first signal end and the first band-stop module share a same metallized electrode, and / or the second signal end and the second band-stop module share a same metallized electrode.

38. The high-density integrated interference suppression device according to claim 1, characterized in that: The first potential end and the second potential end have the same potential.

39. The high-density integrated interference suppression device according to claim 13, characterized in that: The second capacitive structure, the third capacitive structure, the fourth capacitive structure and the fifth capacitive structure are all formed by coupling at least two metallized electrodes facing each other in the stacking direction, and the projections of the metallized electrodes on a plane perpendicular to the stacking direction partially overlap.

40. The high-density integrated interference suppression device according to claim 39, characterized in that: The second capacitive structure and the third capacitive structure share a same metallized electrode.

41. The high-density integrated interference suppression device according to claim 40, characterized in that: The fourth capacitive structure and the fifth capacitive structure share a same metallized electrode.

42. The high-density integrated interference suppression device according to claim 1, characterized in that: The second inductive structure and the third capacitive structure share a same metallized electrode, and / or the second inductive structure and the first potential end share a same metallized electrode.

43. The high-density integrated interference suppression device according to claim 13, characterized in that: The projection of the second inductive structure on the plane perpendicular to the stacking direction partially overlaps with the projection of the second capacitive structure on the plane perpendicular to the stacking direction, and / or the projection of the second inductive structure on the plane perpendicular to the stacking direction partially overlaps with the projection of the third capacitive structure on the plane perpendicular to the stacking direction.

44. The high-density integrated interference suppression device according to claim 13, characterized in that: The eighth capacitive structure is formed by coupling at least two metallized electrodes facing each other in the stacking direction, and the projections of the metallized electrodes on a plane perpendicular to the stacking direction partially overlap.

45. The high-density integrated interference suppression device according to claim 44, characterized in that: The eighth capacitive structure and the second capacitive structure share a same metallized electrode.

46. ​​The high-density integrated interference suppression device according to claim 13, characterized in that: A projection of the ninth inductive structure on a plane perpendicular to the stacking direction partially overlaps with a projection of the third band-stop module on a plane perpendicular to the stacking direction.

47. The high-density integrated interference suppression device according to claim 13, characterized in that: The first band-stop module includes a first conductor portion, a second conductor portion, a third conductor portion, a first conductive column and a second conductive column. The first conductor portion, the second conductor portion and the third conductor portion are stacked along the stacking direction, and the first conductive column and the second conductive column extend in the first substrate along the stacking direction.

48. The high-density integrated interference suppression device according to claim 47, characterized in that: The first conductor part is formed such that when viewed from the stacking direction, its projection on the plane perpendicular to the stacking direction is centered on a point and is surrounded by at least one of a fold line, an arc line, and a spiral line around the point; the second conductor part is arranged between the first conductor part and the third conductor part along the stacking direction, and the second conductor part includes a first subsection and a second subsection with a gap between the first subsection; the projection of the third conductor part on the plane perpendicular to the stacking direction partially overlaps with the projection of the second conductor part on the plane perpendicular to the stacking direction, and the third conductor part and the second subsection of the second conductor part are partially coupled in a facing relationship to form the first capacitive structure; the projection of the first conductor part on the plane perpendicular to the stacking direction partially overlaps with the projection of the first capacitive structure on the plane perpendicular to the stacking direction; the first conductor part, the second conductor part, and the third conductor part are made of metalized materials; the first conductor part is coupled to the first subsection through the first conductive column, and the first conductor part is coupled to the second subsection through the second conductive column, and the first subsection is conductively connected to the third conductor part; The first conductor portion, the first capacitive structure, the first conductive column, the second conductive column, the first sub-portion and coupling paths therebetween form a three-dimensional structure.

49. The high-density integrated interference suppression device according to claim 13, characterized in that: The third band-stop module includes a fourth conductor portion, a fifth conductor portion, a sixth conductor portion, a third conductive column and a fourth conductive column. The fourth conductor portion, the fifth conductor portion and the sixth conductor portion are stacked along the stacking direction, and the third conductive column and the fourth conductive column extend in the first substrate along the stacking direction.

50. The high-density integrated interference suppression device according to claim 49, characterized in that: The fourth conductor portion is formed such that, when viewed from the stacking direction, its projection on a plane perpendicular to the stacking direction is arranged around a point as the center by at least one of a fold line, an arc line, and a spiral line; the fifth conductor portion is arranged between the fourth conductor portion and the sixth conductor portion along the stacking direction; the projection of the sixth conductor portion on a plane perpendicular to the stacking direction and the projection of the fifth conductor portion on a plane perpendicular to the stacking direction at least partially overlap, and the sixth conductor portion and the fifth conductor portion are partially coupled in a facing relationship to form a fifth capacitive structure; the projection of the fourth conductor portion on a plane perpendicular to the stacking direction and the projection of the fifth capacitive structure on a plane perpendicular to the stacking direction partially overlap; The fourth conductor part, the fifth conductor part and the sixth conductor part are formed of metallized materials; the fourth conductive part is coupled with the fifth capacitive structure through the third conductive column and the fourth conductive column, and the fourth conductor part, the fifth capacitive structure, the third conductive column and the fourth conductive column and the coupling path therebetween form a three-dimensional structure in the first substrate.

51. An electronic device, characterized in that: A high-density integrated interference suppression device comprising any one of claims 1 to 50.

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