Heterogeneous integrated filter structure with transient voltage protection and method of manufacture

Abstract

The application provides a heterogeneous integrated filter structure with transient voltage protection and a manufacturing method. The filter structure comprises an insulating substrate, a mounting groove is arranged on the upper surface of the insulating substrate, a semiconductor chip with transient voltage protection function is arranged in the mounting groove, a double-layer spiral inductor is arranged on the upper surface of the insulating substrate, the double-layer spiral inductor comprises a first planar inductor coil and a second planar inductor coil which are arranged in a stack mode, a first passivation layer is arranged between the semiconductor chip and the first planar inductor coil, a second passivation layer is arranged between the first planar inductor coil and the second planar inductor coil, a third passivation layer is arranged on the upper surface of the second planar inductor coil, the first passivation layer and the second passivation layer are both provided with through holes for electrically connecting the upper and lower layers, filter pins are arranged on the third passivation layer, and the filter pins are electrically connected with the second planar inductor coil. The application can improve the differential mode bandwidth index of the filter.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of filter structure, in particular to a heterogeneous integrated filter structure with transient voltage protection, and to a filter structure manufacturing method for manufacturing the heterogeneous integrated filter structure with transient voltage protection. BACKGROUND

[0002] With the increasingly complex structure and powerful functions of electronic devices, the electromagnetic interference (EMI) phenomenon they suffer during operation also increases. For example, when there is a strong external electromagnetic field, the device will simultaneously induce a voltage in the adjacent conductors in the same direction through electromagnetic induction, forming a common-mode voltage. Or inside the electronic device, the parasitic capacitance and inductance between different circuits are coupled through internal circuits, which may generate common-mode noise.

[0003] Common-mode noise can interfere with the normal operation of electronic devices. For example, in a communication system, common-mode noise superimposed on the signal will increase the bit error rate of data transmission, and in severe cases, it may cause communication interruption. In wireless communication, common-mode noise may interfere with the received signal of the antenna, affecting the communication distance and quality. Therefore, in order to reduce the influence of common-mode noise on the signal, a common-mode filter or common-mode choke is usually used to suppress common-mode noise.

[0004] In addition to common-mode noise, electronic devices are also susceptible to electrostatic discharge and transient surges. A transient voltage suppressor (TVS) is a semiconductor component that can effectively protect electronic devices from transient overvoltages (such as electrostatic discharge, lightning surge, etc.). It has been widely used in various electronic devices.

[0005] To suppress common-mode noise and protect against transient overvoltage, researchers have designed a common-mode filter with electrostatic protection function. The equivalent circuit of the common-mode filter is shown in Figure 1 It integrates common-mode inductance with two TVS elements, which can significantly save area. However, the common-mode inductance here is realized by a silicon-based planar spiral inductor. This integrated device has the following problems:

[0006] (1) The planar spiral inductor will be affected by the loss of the silicon substrate below, resulting in a low quality factor and deteriorating the matching of the double-layer inductor, ultimately deteriorating the differential-mode bandwidth index of the filter;

[0007] (2) The planar spiral inductor usually occupies a large layout area, which undoubtedly significantly increases the silicon area and increases the manufacturing cost.

[0008] Therefore, the existing common mode filter design with electrostatic protection function cannot meet the market demand, and a new scheme is urgently needed to realize the new requirements of electronic devices on the performance and cost of devices. SUMMARY

[0009] To solve the problems in the prior art, the application provides a heterogeneous integrated filter structure with transient voltage protection, and a filter structure manufacturing method for manufacturing the heterogeneous integrated filter structure with transient voltage protection, which can significantly reduce the silicon area and improve the differential mode bandwidth index of the product by synergistically optimizing the layout of the semiconductor chip and the wiring of the packaging metal layer, on the basis of realizing the dual functions of electrostatic protection and filtering.

[0010] The heterogeneous integrated filter structure with transient voltage protection comprises an insulating substrate, a mounting groove is arranged on the upper surface of the insulating substrate, a semiconductor chip with transient voltage protection function is arranged in the mounting groove, a double-layer spiral inductor is arranged on the upper surface of the insulating substrate, the double-layer spiral inductor comprises a first planar inductor coil and a second planar inductor coil arranged in layers, a first passivation layer is arranged between the semiconductor chip and the first planar inductor coil, a second passivation layer is arranged between the first planar inductor coil and the second planar inductor coil, a third passivation layer is arranged on the upper surface of the second planar inductor coil, the first passivation layer and the second passivation layer are both provided with through holes for electrical connection between the upper and lower layers, a filter pin is arranged on the third passivation layer, and the filter pin is electrically connected with the second planar inductor coil.

[0011] Further, the internal metal circuit of the semiconductor chip is replaced by an external metal circuit layer, the filter structure further comprises a metal circuit layer arranged between the semiconductor chip and the first passivation layer, the metal circuit layer is used for jumper connection between the electrode of the semiconductor chip and the first planar inductor coil, and a fourth passivation layer is arranged between the semiconductor chip and the metal circuit layer.

[0012] Further, the semiconductor chip without internal metal circuit is completely separated from the double-layer spiral inductor in the vertical projection plane.

[0013] Further, the material of the insulating substrate comprises glass, ceramic or FR4 board.

[0014] Further, the manufacturing process of the filter pin comprises implanting solder balls or wire bonding.

[0015] Further, the filter structure comprises a common mode filter, a low-pass L-C filter or a high-pass L-C filter.

[0016] Further, the double-layer spiral inductor is manufactured by a metal layer or redistribution layer in an integrated circuit process, or is manufactured by a metal layer or redistribution layer in a packaging process, and the double-layer spiral inductor is made of a metal conductor.

[0017] Further, the semiconductor chip manufacturing process includes a semiconductor silicon process, a group III-V compound semiconductor process, or a silicon carbide process.

[0018] The application also provides a filter structure manufacturing method for manufacturing the heterogeneous integrated filter structure with transient voltage protection, comprising the following steps:

[0019] S101: machining a mounting groove on the insulating substrate, the size and depth of the mounting groove being adapted to the size and thickness of the semiconductor chip;

[0020] S102: depositing a buffer adhesion layer on the upper surface of the insulating substrate, and then etching back the buffer adhesion layer except the area of the mounting groove;

[0021] S103: embedding the semiconductor chip in the mounting groove, the upper surface of the semiconductor chip being flush with the upper surface of the insulating substrate;

[0022] S104: manufacturing the double-layer spiral inductor on the upper surface of the insulating substrate, first depositing a first passivation layer and machining a through hole for electrical connection, then forming a first planar inductor coil on the upper surface of the first passivation layer; then depositing a second passivation layer and machining a through hole for electrical connection, and then forming a second planar inductor coil on the upper surface of the second passivation layer;

[0023] S105: depositing a third passivation layer on the upper surface of the second planar inductor coil, and then machining a filter pin for external connection on the third passivation layer.

[0024] The application also provides another filter structure manufacturing method for manufacturing the heterogeneous integrated filter structure with transient voltage protection, comprising the following steps:

[0025] S201: machining a mounting groove on the insulating substrate, the size and depth of the mounting groove being adapted to the size and thickness of the semiconductor chip;

[0026] S202: depositing a buffer adhesion layer on the upper surface of the insulating substrate, and then etching back the buffer adhesion layer except the area of the mounting groove;

[0027] S203: embedding the semiconductor chip in the mounting groove, the upper surface of the semiconductor chip being flush with the upper surface of the insulating substrate;

[0028] S204: manufacturing the metal line layer of the jumper connection on the upper surface of the insulating substrate, first, depositing the fourth passivation layer and processing the through hole for electrical connection with the semiconductor chip, then constructing the metal line on the upper surface of the fourth passivation layer;

[0029] S205: manufacturing the double-layer spiral inductor on the upper surface of the insulating substrate, first, depositing the first passivation layer and processing the through hole for electrical connection, then forming the first planar inductor coil on the upper surface of the first passivation layer; then depositing the second passivation layer and processing the through hole for electrical connection, then forming the second planar inductor coil on the upper surface of the second passivation layer;

[0030] S206: depositing the third passivation layer on the upper surface of the second planar inductor coil, then processing the filter pin for external connection on the third passivation layer.

[0031] Compared with the prior art, the beneficial effects of the present application are: compared with the traditional common mode filter manufactured directly on the silicon substrate, the differential mode bandwidth index is expected to be optimized by 30% ~ 50%, the present application uses an insulating substrate such as glass to replace the silicon substrate of the semiconductor device, then an installation groove is opened on the upper surface of the insulating substrate, and the semiconductor chip is placed in the installation groove, since the semiconductor device has a very small size, therefore, the hollow part of the coil of the double-layer spiral inductor has little overlap with silicon, thus significantly suppressing the substrate eddy current effect, and the deterioration of the quality factor and inductance matching degree of the semiconductor silicon substrate on the double-layer inductor is avoided to the greatest extent, thereby improving the differential mode bandwidth index of the filter, in addition, the use of silicon wafers is significantly reduced, thereby effectively reducing the manufacturing cost;

[0032] By externally setting the metal line layer to replace the internal metal line of the semiconductor chip, the jumper connection is realized, and in this design, only the electrode lead-out of the semiconductor chip uses the internal metal of the silicon chip, so that the area of the silicon chip used in this example can be further reduced, thereby reducing the cost; the coil of the double-layer spiral inductor can be completely separated from the semiconductor chip in the vertical projection direction, thereby avoiding any substrate loss, and further improving the differential mode bandwidth. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the schemes in the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description, and obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0034] Figure 1 Equivalent circuit diagram of the prior common mode filter with electrostatic protection function;

[0035] Figure 2Fig. 1 is a schematic diagram of a layout structure of a first embodiment of the present application;

[0036] Figure 3 Fig. 2 is a flow chart of a filter structure manufacturing method of the first embodiment of the present application;

[0037] Figure 4 Fig. 3 is a schematic diagram of a layout structure of a second embodiment of the present application;

[0038] Figure 5 Fig. 4 is a flow chart of a filter structure manufacturing method of the second embodiment of the present application. DETAILED DESCRIPTION

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting upon the application; the description and claims of the application as well as the above abstract are intended to cover all alternatives, modifications, equivalents and equivalents thereof falling within the scope of the application; the description and claims of the application or the above abstract, the terms "comprise", "have" and "include" and any variations thereof are intended to cover a non-exclusive inclusion; the description and claims of the application or the above abstract, the terms "first", "second" and the like are used to distinguish different objects, not to describe a particular order.

[0040] In the present application, the phrase "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase at various places in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in the present application can be combined with other embodiments.

[0041] In order for those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings.

[0042] As Figures 2-5As shown in the figure, the hetero-integrated filter structure with transient voltage protection of the application comprises an insulating substrate, the upper surface of the insulating substrate is provided with a mounting groove, the mounting groove is provided with a semiconductor chip with transient voltage protection function, the upper surface of the insulating substrate is provided with a double-layer spiral inductor, the double-layer spiral inductor comprises a first planar inductor coil and a second planar inductor coil arranged in layers, a first passivation layer is arranged between the semiconductor chip and the first planar inductor coil, a second passivation layer is arranged between the first planar inductor coil and the second planar inductor coil, a third passivation layer is arranged on the upper surface of the second planar inductor coil, the first passivation layer and the second passivation layer are both provided with through holes for electrical connection between the upper and lower layers, and a filter pin is arranged on the third passivation layer, the filter pin is electrically connected with the second planar inductor coil.

[0043] As Figure 2 As shown in the figure, as the first embodiment of the application, the filter structure of the example is a common mode filter, the insulating substrate of which adopts a glass substrate 100, and the entire common mode filter is composed of a TVS silicon chip 220 embedded in the glass substrate 100 and a double-layer spiral inductor above the glass substrate 100. The double-layer spiral inductor of the example comprises a first planar inductor coil 110 and a second planar inductor coil 111 provided with N turns, wherein the first planar inductor coil 110 and the second planar inductor coil 111 are provided with a hollow area 130, where the magnetic field strength is the largest. Since the entire filter structure needs to be connected by jumper wires with the internal metal of the TVS silicon chip 220, the TVS silicon chip 220 cannot be completely separated from the inductor coil in the vertical projection direction, and there will be some overlap. However, as can be seen from the structure, the overlap of the hollow area 130 of the inductor coil and the silicon is very small, thus significantly suppressing the substrate eddy current effect and maximizing the avoidance of the deterioration of the quality factor and inductance matching degree of the double-layer spiral inductor caused by the semiconductor silicon substrate, thereby improving the differential mode bandwidth index of the filter.

[0044] The material of the first planar inductor coil 110 and the second planar inductor coil 111 of the example is a conductor, preferably a metal conductor, which can be made of aluminum, copper, aluminum-copper alloy, etc. In addition to the rectangular shape of the example, the double-layer spiral inductor can also adopt other shapes such as square, circular, octagonal, and circular-like shapes. The double-layer spiral inductor can be manufactured using the metal layer or redistribution layer in the integrated circuit process, or using the metal layer or redistribution layer in the packaging process.

[0045] The first planar inductor coil 110 and the second planar inductor coil 111 of the example are both manufactured by redistribution layer, and in order to achieve the best magnetic field matching, the layout of the double-layer coil should be consistent as much as possible, and the metal material and thickness should be as same as possible.

[0046] The insulating substrate can also be a ceramic substrate, FR4 board, or other common insulating material substrate. The TVS silicon chip 220 of the present example can be various common electrostatic protection devices / circuits or surge protection devices / circuits. The process platform on which the TVS silicon chip 220 of the present example is manufactured can be a typical semiconductor process platform, including but not limited to semiconductor silicon processes, three-five compound semiconductor processes, silicon carbide processes, etc. The present example is described by way of example using a redistribution layer manufacturing process.

[0047] As shown in Figure 3 , as one of the embodiments of the first embodiment of the present application, the packaging process of the common mode filter of the present example uses a 3P3M process (i.e. three layers of passivation layer and three layers of metal layer), and the manufacturing method of the common mode filter of the present example is as follows:

[0048] S101: Process a mounting groove 270 on the glass substrate 200, the size and depth of the mounting groove 270 being adapted to the size and thickness of the semiconductor chip.

[0049] Before processing, a glass substrate 200 is provided, the thickness of the glass substrate 200 being determined by the mechanical strength and the packaging height of the finished filter product. In the present example, a thicker glass substrate can be used first, and then thinned after step S105 is performed.

[0050] The size and depth of the mounting groove of the present example are determined by the "TVS silicon chip" to be embedded subsequently. The mounting groove can be cut by mechanical equipment or etched by laser. Figure 3 , (a) and (b).

[0051] S102: Deposit a buffer adhesion layer 210 on the upper surface of the glass substrate, and then etch back the buffer adhesion layer in areas other than the mounting groove.

[0052] The buffer adhesion layer of the present example can be a single layer structure, or can be divided into a buffer layer and an adhesion layer. The buffer layer is used to relieve mechanical and thermal stress between the silicon and the glass, and the adhesion layer, which is similar to insulating glue, is used to adhere the TVS silicon chip in the mounting groove 270 of the glass substrate 200. Etching back is used to remove the excess "buffer + adhesion" layer on the upper surface of the glass substrate 200, and can be performed by etching or grinding. The processing process is shown in Figure 3 , (c) and (d).

[0053] S103: embedding the TVS silicon chip 220 in the mounting groove 270, the TVS silicon chip 220 is manufactured by silicon technology, which can be an avalanche tube, NPN, PNP, silicon controlled rectifier, MOSFET, etc., and the upper surface of the TVS silicon chip 220 is provided with a metal pad 230; the upper surface of the TVS silicon chip 220 is flush with the upper surface of the glass substrate 200. The processing process is specifically shown in Figure 3 (e).

[0054] S104: manufacturing a double-layer spiral inductor on the upper surface of the glass substrate.

[0055] First, deposit the first passivation layer 240 and process the first electrically conductive hole 280, then form the first layer of redistribution layer 250 on the upper surface of the first passivation layer 240, and then etch the first planar inductor coil for the first layer of redistribution layer 250; then deposit the second passivation layer 241 and process the second electrically conductive hole 281, then form the second layer of redistribution layer 251 on the upper surface of the second passivation layer 241, and then etch the second planar inductor coil for the second layer of redistribution layer 251.

[0056] The two layers of redistribution layers each form a planar inductor coil, in order to ensure matching, in addition to layout, the material, thickness and other process parameters of the two layers of redistribution layers need to be maintained as consistent as possible, and the material of the two layers of redistribution layers is preferably copper. The processing process of this step is specifically shown in Figure 3 (f)-(i).

[0057] S105: depositing a third passivation layer 242 on the upper surface of the second layer of redistribution layer 251, then opening a pin hole 282 on the third passivation layer 242, and finally processing a filter pin 260 for external connection at the pin hole 282, the manufacturing process of the filter pin can be a common process such as solder ball implantation or wire bonding, in this example, solder balls are implanted in the pin hole 282 as external pins of the entire filter product, and the solder balls are internally connected to the second layer of redistribution layer 251 inside the filter. The processing process is specifically shown in Figure 3 (j) and (k).

[0058] The heterogeneous integration process proposed in the application is not only suitable for common-mode filters, but also suitable for other filters containing "semiconductor chips" and "inductor elements", such as low-pass L-C filters, high-pass L-C filters, etc.

[0059] As Figure 4As shown, as the second embodiment of the present application, this embodiment is based on the first embodiment, and the metal circuit 330 is constructed on the upper surface of the common mode filter glass substrate 300 instead of the internal metal circuit of the TVS silicon chip, which is used for the jumper connection of the first planar inductor coil 310, the second planar inductor coil 311 and the TVS silicon chip 420, so that the first planar inductor coil 310, the second planar inductor coil 311 and the TVS silicon chip 420 can be completely separated in the vertical projection direction, thereby avoiding any substrate loss and further improving the differential mode bandwidth. At this time, only the electrode of the TVS silicon chip 420 is led out to the surface of the TVS silicon chip 420, and the internal metal of the silicon chip is used, so that the area of the silicon chip can be further reduced, and the manufacturing cost is effectively reduced.

[0060] As shown in FIG. 1, the first embodiment of the present application is a common mode filter structure, which is manufactured by a 3P3M packaging process, i.e., a 3-layer passivation layer and a 3-layer metal layer process. Figure 5 As shown, compared with the packaging process (3P3M process) of the first embodiment, the present embodiment adopts a 4P4M packaging process, i.e., a 4-layer passivation layer and a 4-layer metal layer process. The filter structure manufacturing method of this embodiment is as follows:

[0061] S201: A mounting groove 470 is processed on the glass substrate 400, and the size and depth of the mounting groove 470 are adapted to the size and thickness of the semiconductor chip.

[0062] Before processing, a glass substrate 400 is provided, and the thickness of the glass substrate 400 is determined by the mechanical strength and the packaging height of the finished filter product. In this embodiment, a thicker glass substrate can be used first, and then thinned after step S206 is performed to obtain the final finished product.

[0063] The size and depth of the mounting groove of this embodiment are determined by the subsequent embedded "TVS silicon chip". The mounting groove can be cut by mechanical equipment or etched by laser. Figure 5 The processes of processing the mounting groove 470 are shown in (a) and (b) of FIG. 4.

[0064] S202: A buffer adhesion layer 410 is deposited on the upper surface of the glass substrate, and then the buffer adhesion layer in the area except the mounting groove is etched back.

[0065] The buffer adhesion layer of this embodiment can be a single layer structure or a layered buffer adhesion layer composed of a buffer layer and an adhesion layer. The buffer layer is used to relieve the mechanical stress and thermal stress between the silicon and the glass, and the adhesion layer, which is similar to the insulating glue, is used to adhere the TVS silicon chip in the mounting groove 470 of the glass substrate 400. The etching or grinding method can be used to remove the excess "buffer + adhesion" layer on the upper surface of the glass substrate 400, and the processing process is shown in (c) and (d) of FIG. 5. Figure 5

[0066] ​S203: embed the TVS silicon chip 420 in the mounting groove 470, the upper surface of the TVS silicon chip 420 is provided with a metal pad 430; the upper surface of the TVS silicon chip 420 is flush with the upper surface of the glass substrate 400. The processing process is specifically seen in Figure 5 (e).

[0067] S204: manufacture the metal wire layer of the jumper connection on the upper surface of the glass substrate 400.

[0068] First, deposit the fourth passivation layer 440 and process the third electrically connected through hole 480 electrically connected with the TVS silicon chip 420, then form the third redistribution layer 450 on the upper surface of the fourth passivation layer 440, and then etch the metal wire on the third redistribution layer 450. The processing process is specifically seen in Figure 5 (f).

[0069] S205: manufacture the double-layer spiral inductor on the upper surface of the glass substrate.

[0070] First, deposit the first passivation layer 441 on the upper surface of the metal wire layer and process the first electrically connected through hole 481, then form the first redistribution layer 451 on the upper surface of the first passivation layer 441, and then etch the first planar inductor coil on the first redistribution layer 451; then deposit the second passivation layer 442 and process the second electrically connected through hole 482, then form the second redistribution layer 452 on the upper surface of the second passivation layer 442, and then etch the second planar inductor coil on the second redistribution layer 452. Two redistribution layers each form a planar inductor coil. In order to ensure matching, in addition to layout, the material, thickness and other process parameters of the two redistribution layers need to be consistent as much as possible. The material of the two redistribution layers is preferably copper. The processing process is specifically seen in Figure 5 (h)-(k).

[0071] S206: deposit the third passivation layer 443 on the upper surface of the second redistribution layer 452, then open the pin hole 483 on the third passivation layer 443, and finally process the solder ball 460 for external connection at the pin hole 483, as the external pin of the whole filter product. The solder ball is internally electrically connected with the second redistribution layer 452 inside the filter. The processing process is specifically seen in Figure 5 (l) and (m).

[0072] Compared with the common mode filter directly manufactured on the silicon substrate, the differential mode bandwidth index of the present application is expected to be optimized by 30%-50%, the present application uses an insulating substrate such as glass to replace the silicon substrate of the semiconductor device, then a mounting groove is formed on the surface of the insulating substrate, and the semiconductor chip is placed in the mounting groove, since the semiconductor device has a very small size, therefore, the overlap between the hollow part of the double-layer spiral inductor coil and the silicon is very small, thus the substrate eddy current effect is significantly suppressed, the quality factor and inductance matching degree of the double-layer inductor are avoided from being deteriorated by the semiconductor silicon substrate to the maximum extent, thus the differential mode bandwidth index of the filter is improved, in addition, the use of the silicon wafer is significantly reduced, thus the manufacturing cost is effectively reduced.

[0073] By externally setting the metal circuit layer to replace the internal metal circuit of the semiconductor chip, the jumper connection is realized, in this design, only the electrode lead-out of the semiconductor chip uses the internal metal of the silicon chip, therefore, the area of the silicon chip used in the present example can be further reduced, and the cost is reduced; the double-layer spiral inductor coil can be completely separated from the semiconductor chip in the vertical projection direction, thus any substrate loss is avoided, and the differential mode bandwidth is further improved.

[0074] The above specific embodiments are the preferred embodiments of the present application, and are not intended to limit the specific implementation range of the present application, the scope of the present application includes but is not limited to the specific embodiments, any equivalent changes made according to the present application are within the protection scope of the present application.

Claims

1. A heterogeneously integrated filter structure with transient voltage protection, characterized by: The filter structure comprises an insulating substrate, a mounting groove is arranged on the upper surface of the insulating substrate, a semiconductor chip with transient voltage protection function is arranged in the mounting groove, a double-layer spiral inductor is arranged on the upper surface of the insulating substrate, the double-layer spiral inductor comprises a first planar inductor coil and a second planar inductor coil which are arranged in a stack, a first passivation layer is arranged between the semiconductor chip and the first planar inductor coil, a second passivation layer is arranged between the first planar inductor coil and the second planar inductor coil, a third passivation layer is arranged on the upper surface of the second planar inductor coil, the first passivation layer and the second passivation layer are both provided with through holes for electrical connection between the upper and lower layers, a filter pin is arranged on the third passivation layer, and the filter pin is electrically connected with the second planar inductor coil.

2. The heterogeneously integrated filter structure with transient voltage protection of claim 1, wherein: The internal metal circuit of the semiconductor chip is replaced by an external metal circuit layer, the filter structure further comprises a metal circuit layer arranged between the semiconductor chip and the first passivation layer, the metal circuit layer is used for jumper connection between the electrode of the semiconductor chip and the first planar inductor coil, and a fourth passivation layer is arranged between the semiconductor chip and the metal circuit layer.

3. The heterogeneously integrated filter structure with transient voltage protection of claim 2, wherein: The semiconductor chip without internal metal circuit is arranged to be completely separated from the double-layer spiral inductor in a vertical projection plane.

4. The heterogeneously integrated filter structure with transient voltage protection according to any of claims 1 to 3, characterized in that: The material of the insulating substrate comprises glass, ceramic or FR4 board.

5. The heterogeneously integrated filter structure with transient voltage protection according to any of claims 1-3, characterized in that: The manufacturing process of the filter pin comprises implanting solder balls or wire bonding.

6. The heterogeneously integrated filter structure with transient voltage protection according to any of claims 1-3, characterized in that: The filter structure comprises a common-mode filter, a low-pass L-C filter or a high-pass L-C filter.

7. The heterogeneously integrated filter structure with transient voltage protection according to any of claims 1-3, characterized in that: The double-layer spiral inductor is manufactured by a metal layer or a redistribution layer in an integrated circuit process or a metal layer or a redistribution layer in a packaging process, and the material of the double-layer spiral inductor is a metal conductor.

8. The heterogeneously integrated filter structure with transient voltage protection according to any of claims 1-3, characterized in that: The preparation process of the semiconductor chip comprises a semiconductor silicon process, a three-five compound semiconductor process or a silicon carbide process.

9. A filter structure manufacturing method for manufacturing the hetero-integration type filter structure with transient voltage protection according to claim 1, characterized by, The method comprises the following steps: S101: a mounting groove is processed on the insulating substrate, and the size and depth of the mounting groove are adapted to the size and thickness of the semiconductor chip; S102: a buffer adhesion layer is deposited on the upper surface of the insulating substrate, and then the buffer adhesion layer in regions other than the mounting groove is etched back; S103: a semiconductor chip is embedded in the mounting groove, and the upper surface of the semiconductor chip is flush with the upper surface of the insulating substrate; S104: a double-layer spiral inductor is manufactured on the upper surface of the insulating substrate, firstly, a first passivation layer is deposited and a through hole for electrical connection is processed, then a first planar inductor coil is formed on the upper surface of the first passivation layer; then a second passivation layer is deposited and a through hole for electrical connection is processed, then a second planar inductor coil is formed on the upper surface of the second passivation layer; S105: a third passivation layer is deposited on the upper surface of the second planar inductor coil, and then a filter pin for external connection is processed on the third passivation layer.

10. A filter structure manufacturing method for manufacturing the hetero-integration type filter structure with transient voltage protection according to claim 2, characterized by, The method comprises the following steps: S201: a mounting groove is processed on the insulating substrate, and the size and depth of the mounting groove are adapted to the size and thickness of the semiconductor chip; S202: a buffer adhesion layer is deposited on the upper surface of the insulating substrate, and then the buffer adhesion layer in regions other than the mounting groove is etched back; S203: embedding a semiconductor chip in the mounting groove, the upper surface of the semiconductor chip being flush with the upper surface of the insulating substrate; S204: manufacturing a metal wire layer with jumper connection on the upper surface of the insulating substrate, first, depositing a fourth passivation layer and processing a through hole for electrical connection with the semiconductor chip, then constructing a metal wire layer on the upper surface of the fourth passivation layer; S205: manufacturing a double-layer spiral inductor on the upper surface of the insulating substrate, first, depositing a first passivation layer and processing a through hole for electrical connection, then forming a first planar inductor coil on the upper surface of the first passivation layer; then depositing a second passivation layer and processing a through hole for electrical connection, then forming a second planar inductor coil on the upper surface of the second passivation layer; S206: depositing a third passivation layer on the upper surface of the second planar inductor coil, then processing a filter pin for external connection on the third passivation layer.

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