A digital channelization implementation method based on fractional oversampling polyphase filter bank

Abstract

The application provides a digital channelization implementation method based on a fractional multiple oversampling polyphase filter bank, which works in a parallel pipeline mode, the input parallel channel number is A in , the output parallel channel number is A, the channel number is M, the length of each phase sub-filter is L, the total filter length is L*M, wherein M=M1*A, A in <A, M1, A in , A, L are all positive integers. The method comprises the following steps: shaping A in parallel input data into A parallel data through a data shaping module; rearranging the input data according to M phases through an input data rearrangement module, and outputting A*L data under each clock; calling filter coefficients according to the parallel degree A through a sub-filter and a scheduling module to perform filtering; performing channel frequency shift through a parallel hierarchical FFT module; and finally correcting the phase deflection caused by oversampling through a phase rotation module to obtain the channelized result. The application realizes real-time digital channelization with large bandwidth and multiple channels based on a polyphase filter bank in limited resources, and solves the problem of traditional polyphase filter channel spectrum attenuation with flexible channel division.

Description

Technical Field

[0001] This invention relates to the field of signal processing, and more particularly to a digital channelization implementation method based on fractional oversampling multiphase filter banks. Background Technology

[0002] With the increasing demand for signals in society and the development of technologies such as semiconductors and signal processing, signal bandwidth is becoming larger, signal processing speed is becoming faster, and signal processing accuracy is becoming higher. For example, radio telescope terminal equipment and radar detection systems require receivers to operate on a very wide frequency band and to divide this wide frequency band evenly into multiple independent sub-bands through channelization algorithms. This allows for the acquisition and fine processing of signals in any frequency band at any time.

[0003] Because Field Programmable Gate Arrays (FPGAs) provide a powerful parallel computing architecture, FPGA-based digital signal processing systems are well-suited for high-performance applications that require fast, real-time processing and large data bandwidth.

[0004] Polyphase filter banks (PFBs) are a popular choice for channelization algorithms because they effectively apply windowed filters before performing discrete Fourier transforms, minimizing spectral leakage between subbands. However, the transition bands of the filters can cause spectral attenuation of broadband signals.

[0005] Oversampled polyphase filter banks (OPFBs) are an extension of the PFB algorithm. Their data is reused in an overlapping manner, maintaining the same subband spacing but increasing both subband bandwidth and sampling rate. Spectral overlap occurs between adjacent subbands, reducing spectral attenuation in the transition band. Compared to PFBs, OPFBs not only require overlapping and serpentine shifting of input data but also compensation for phase shift caused by oversampling of output data. This makes implementation extremely complex, especially with numerous phases, multi-channel parallel processing, and real-time handling, particularly when the oversampling factor is a fractional multiple. Currently, there are many FPGA implementations of digital channelization based on PFBs, and research on FPGA implementations of digital channelization based on integer multiple oversampling OPFBs, but no specific FPGA implementation of OPFBs based on fractional multiple oversampling. Some articles describe the serpentine data multiplexing method of OPFBs with fractional multiple oversampling, but FPGA memory cannot implement this function; it can only be achieved through registers. In high-bandwidth, multi-channel scenarios, the demand for registers is enormous, leading to placement and routing difficulties, reduced operating clock frequency, and significantly impacting system processing speed. Summary of the Invention

[0006] The purpose of this invention is to provide a real-time digital channelization FPGA implementation method based on fractional oversampling multiphase filter banks, which solves the problem of subband spectrum attenuation in digital channelization based on PFBs and improves the processing performance and speed of the system.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] This invention operates in parallel pipeline mode, with a parallel input path count of A. in The number of parallel output paths is A, the number of channels is M, the length of each phase sub-filter is L, and the total filter length is L*M, where M = M1*A, M = M1*A, A in <A,M1、A in A, L are all positive integers. The oversampling factor is A / A. in Output extraction factor D = M * A in / A = D1 * A. M1 is the channel intermediate parameter, and D1 is the decimation parameter. Since the system output is A parallel paths, D needs to be an integer multiple of A, and D1 is a positive integer.

[0009] Assume the bandwidth of the input signal x(n) is f s The frequency band range is (Note: Discrete signal spectra have periodicity) Frequency band range is equivalent to It is divided into M subbands, with a subband bandwidth of The center frequency of the m-th sub-band is down-converted signal d m (n) is shown in equation (1):

[0010]

[0011] We perform a low-pass filter on it, where h(k) is the inverted result of the low-pass filter response, the filter order is LM, and the filtering result is b. m (n) is shown in equation (2):

[0012]

[0013] y is obtained through 1 / D sampling. m (n) is shown in equation (3):

[0014]

[0015] The parentheses () contain polyphase filtering, the square brackets [] contain FFT, and the brackets outside contain phase rotation.

[0016] On one hand, this invention discloses a digital channelization implementation method based on fractional oversampling multiphase filter banks, characterized in that the method operates in parallel pipeline mode and includes the following steps:

[0017] 1) Fill in the input A in The parallel data from one path is reshaped into A-path parallel data;

[0018] 2) The input data rearrangement module rearranges the input A-channel parallel data according to M phases, and outputs A*L data in parallel each clock cycle. This includes: using the BRAM write control unit to store the data shaped in step 1) into the BRAM storage space in sequence; using the BRAM read control unit to read the data in the BRAM storage space in sequence; using the data rearrangement control state machine to control the state of the BRAM write control unit and the BRAM read control unit; and using the read data reordering unit to rearrange the data read from the storage space in each clock cycle according to the order required by the subsequent stage.

[0019] 3) Filter the data output in step 2) according to the parallelism A and the filter coefficients.

[0020] 4) Perform channel frequency shifting on the filtered data;

[0021] 5) Multiply the frequency-shifted signal by the correction rotation factor to correct the phase deflection caused by oversampling and obtain the channelized result.

[0022] On the other hand, the present invention provides a digital channelization implementation system based on fractional oversampling multiphase filter banks for implementing the above method, characterized in that it includes:

[0023] The data shaping module is used to shape the input A. in The parallel data from one path is reshaped into A-path parallel data;

[0024] The input data rearrangement module includes a BRAM write control unit, a BRAM read control unit, a data rearrangement control state machine, and a read data sequencing unit. The BRAM write control unit stores the shaped data sequentially into the BRAM storage space, and the BRAM read control unit reads the data from the BRAM storage space sequentially. The data rearrangement control state machine controls the states of the BRAM write control unit and the BRAM read control unit. The read data sequencing unit rearranges the data read from the storage space in each clock cycle according to the order required by the subsequent stage.

[0025] The sub-filter and its scheduling module, which calls the filtering coefficients according to the parallelism A, filters the data output by the input data rearrangement module.

[0026] The parallel hierarchical FFT module performs channel frequency shifting on the data filtered by the sub-filters and their scheduling modules.

[0027] The phase rotation module multiplies the frequency-shifted signal from the parallel hierarchical FFT module by a correction rotation factor to correct the phase deflection caused by oversampling and obtain the channelized result.

[0028] The beneficial effects of this invention are:

[0029] This invention achieves real-time digital channelization with large bandwidth and multiple channels based on oversampling polyphase filter banks within limited resources. It offers flexible channel partitioning and solves the spectral attenuation problem in traditional polyphase filter bank-based channelization techniques, while minimizing resource consumption. This is beneficial for FPGA implementation of higher-precision and higher-performance digital channelization technologies. Attached Figure Description

[0030] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 The present invention provides an overall functional block diagram of a real-time digital channelization FPGA implementation method based on fractional oversampling multiphase filter banks;

[0032] Figure 2 This is a functional block diagram of the input data rearrangement module provided by the present invention;

[0033] Figure 3 This is a schematic diagram of the state transition of the input data rearrangement module control state machine provided by the present invention;

[0034] Figure 4 This is a functional block diagram of the sub-filter and its scheduling module provided by the present invention;

[0035] Figure 5 The functional block diagram of the parallel hierarchical FFT module provided by this invention;

[0036] Figure 6 This is a functional block diagram of the phase rotation module provided by the present invention;

[0037] Figure 7 A schematic diagram illustrating the input data rearrangement module writing data into BRAM according to an embodiment of the present invention;

[0038] Figure 8 This is a schematic diagram of the state transition of the input data rearrangement module control state machine provided in an embodiment of the present invention;

[0039] Figure 9 This is a schematic diagram of the input data rearrangement module BRAM readout provided in an embodiment of the present invention;

[0040] Figure 10 This is a schematic diagram of the BRAM reading data reordering module provided in an embodiment of the present invention;

[0041] Figure 11 This is a simplified schematic diagram of the phase rotation module provided in an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] In this embodiment, the system bandwidth is 1.96608 Gps, the sampling quantization bit width is 12 bits, the system operates in parallel pipeline mode, the input signal duty cycle is 1, and the number of parallel paths is A. in The output signal duty cycle is 1, the number of parallel paths A is 8, the number of channels M is 2048, and the decimation factor D = M * A is 6. in / A = 1536, the length L of each phase sub-filter is 4, the total filter length L*M is 8192, the sub-band bandwidth is 1.28Mbps, and the inter-sub-band spacing is 0.96M. The channel intermediate parameter M1 = M / A = 256, and the decimation parameter D1 = D / A = 192.

[0044] like Figure 1 As shown, an example of a digital channelization implementation method based on fractional oversampling multiphase filter banks is presented, which includes:

[0045] 1) Fill in the input A in The parallel data from one path is reshaped into A-path parallel data;

[0046] 2) The input data rearrangement module rearranges the input A-channel parallel data according to M phases, and outputs A*L data in parallel each clock cycle. This includes: using the BRAM write control unit to store the data shaped in step 1) into the BRAM storage space in sequence; using the BRAM read control unit to read the data in the BRAM storage space in sequence; using the data rearrangement control state machine to control the state of the BRAM write control unit and the BRAM read control unit; and using the read data sorting unit to sort the data read from the storage space in each clock cycle according to the order required by the subsequent stage and output it.

[0047] 3) Filter the data output in step 2) according to the parallelism A and the filter coefficients.

[0048] 4) Perform channel frequency shifting on the filtered data;

[0049] 5) Multiply the frequency-shifted signal by the correction rotation factor to correct the phase deflection caused by oversampling and obtain the channelized result.

[0050] In a specific embodiment of the present invention, a real-time digital channelization FPGA implementation system based on fractional oversampling multiphase filter banks is provided to implement the above method, comprising five parts: a data shaping module (for implementing step 1), an input data rearrangement module (for implementing step 2), a sub-filter and its scheduling module (for implementing step 3), a parallel hierarchical FFT module (for implementing step 4), and a phase rotation module (for implementing step 5).

[0051] The data shaping module is used to transform the A input in a full time slot into a more accurate and accurate representation of the input data. in Parallel data is shaped into effective data with a duty cycle of A. in / A is the A-channel parallel data. In this embodiment, it means shaping the 6-channel parallel data input at full time slot into 8-channel parallel data with an effective data duty cycle of 3 / 4.

[0052] The functions of the input data rearrangement module are as follows: Figure 2 As shown, it mainly consists of four parts: a BRAM write control unit, a data rearrangement control state machine, a BRAM read control unit, and a read data sequencing unit. The BRAM write control unit stores the signals input to the data rearrangement module sequentially into the BRAM storage space. The data rearrangement control state machine controls the states of the BRAM write control unit and the BRAM read control unit. The BRAM read control unit reads the signals from the BRAM storage space sequentially. The read data sequencing unit sequences and outputs the signals read from the storage space in each clock cycle according to the required order for subsequent stages.

[0053] like Figure 2 As shown: Considering the IQ two-way quadrature input mode, L bit widths of A * data bit width * 2 and depths of M / A * 2 are allocated in the FPGA. x The block random access memory (BRAM) space, where x = 0, 1, ..., the value of x is determined according to the length of a single BRAM in the selected FPGA and M1, the purpose of which is to reduce the complexity of the data rearrangement control state machine by utilizing space expansion (hereinafter, x = 0 is used as an example).

[0054] Specifically, in this embodiment, four BRAM spaces with a bit width of 8*12*2=192bit (8 represents the number of parallel channels, 12 represents the quantization bit width of ADC sampling, and 2 represents the real and imaginary parts of the signal) and a depth of 2048 / 8=256 (2048 represents the number of channels and 8 represents the number of parallel channels) need to be allocated in the FPGA.

[0055] The clock of the input signal is counted, and the count value is t1, t1 = 0, 1, ..., M1*L-1. When t1 = M1*L-1, the next time step t1 = 0. The input data is stored according to the value of t1. The A data input at time t1 is stored in the (l+1)th BRAM at the address rem(t1 / M1), where l = mod(t1 / M1), rem() represents the remainder operation, and mod() represents the modulo operation.

[0056] The clock of the output signal is counted, with a count value of t2, where t2 = 0, 1, ..., M1-1. When t2 = M1-1, the next time step is t2 = 0. The transitions of the control state machine are controlled by the data rearrangement based on the values ​​of t1 and t2. Since the state of the state machine is related to M1, D1, L, and x, the state machine needs to be customized for each coefficient.

[0057] Specifically, in this embodiment, the BRAM write control unit needs to count the clock of the signal (shaped A-channel parallel data) input by the data shaping module. In this embodiment, the input signal is represented by matrix X, as shown in equation (4):

[0058]

[0059] The matrix consists of 8 rows and infinite columns. Each column represents the signal that is input to the data rearrangement module in 8 parallel channels for one clock cycle after being shaped. x(a,b) represents the a-th signal in the b-th decimation cycle, where a = 1, 2, ..., 1536 and b = 1, 2, ...

[0060] The input signal is counted, with a count value of t1, where t1 = 0, 1, ..., 1023. When t1 = 1023, the next time step t1 = 0. The input data is stored based on the value of t1. A schematic diagram of writing to BRAM is shown below. Figure 7 As shown:

[0061] When t1 = 0 to 255, the control input data is stored at address t1 in the first BRAM space;

[0062] When t1 = 256~511, the control input data is stored at address t1-256 in the second BRAM space;

[0063] When t1 = 512 to 767, the control input data is stored at address t1-512 in the third BRAM space;

[0064] When t1 = 768~1023, the control input data is stored at address t1-768 in the fourth BRAM space.

[0065] The BRAM readout control unit counts the clock of the signal output to the sub-filter and its scheduling module. The count value is t2, where t2 = 0, 1, ..., 255 (M1-1). When t2 = 255, the next time step is t2 = 0. Based on the values ​​of t1 and t2, the control data rearrangement controls the transitions of the state machine (hereinafter referred to as the state machine).

[0066] The state machine transitions of this invention are as follows: Figure 3 As shown: In the initial stage, when l = L-1 and rem(t1 / D1) = D1-1, the state machine transitions to the read / write state, and t2 starts counting. The read / write state is further divided into several sub-states. Initially, it is read / write state 1. When t2 = f1(M1,D1,L,x,1), it transitions to read / write state 2. When t2 = f1(M1,D1,L,x,1), it transitions to read / write state 2. i When (M1,D1,L,x,i) is reached, the state transitions to read / write state i+1; There are I read / write sub-states, i = 1, 2, ..., I. When i = I, the next state is i = 1, where f i This represents the condition for transitioning from the i-th read / write sub-state to the (i+1)-th read / write sub-state. i The value is M1-1 or rem(d*(M1-D1)-1 / M1), where d is the number of times M1 is reached from read / write state 1 (t2). The condition is true whichever state t2 reaches first. I is the end position of the read / write sub-state loop, at which point d = L*M1 / gcd(M1,D1), where gcd() represents the greatest common divisor.

[0067] The state transition diagram of the state machine in this embodiment is as follows: Figure 8 As shown:

[0068] When the system starts, the state machine is in the initial stage. When t1 = 959, the state machine jumps to read / write state 1, and at the same time, t2 starts counting.

[0069] In read / write state 1, when t2 = 255, the state machine transitions to read / write state 2.

[0070] In read / write state 2, when t2 = 63, the state machine transitions to read / write state 3.

[0071] In read / write state 3, when t2 = 255, the state machine transitions to read / write state 4.

[0072] In read / write state 4, when t2 = 127, the state machine transitions to read / write state 5.

[0073] In read / write state 5, when t2 = 255, the state machine transitions to read / write state 6.

[0074] In read / write state 6, when t2 = 191, the state machine transitions to read / write state 7.

[0075] In read / write state 7, when t2 = 255, the state machine transitions to read / write state 8.

[0076] In read / write state 8, when t2 = 255, the state machine transitions to read / write state 9.

[0077] In read / write state 9, when t2 = 63, the state machine transitions to read / write state 10.

[0078] In read / write state 10, when t2 = 255, the state machine transitions to read / write state 11.

[0079] In read / write state 11, when t2 = 127, the state machine transitions to read / write state 12.

[0080] In read / write state 12, when t2 = 255, the state machine transitions to read / write state 13.

[0081] In read / write state 13, when t2 = 191, the state machine transitions to read / write state 14.

[0082] In read / write state 14, when t2 = 255, the state machine transitions to read / write state 15.

[0083] In read / write state 15, when t2 = 255, the state machine transitions to read / write state 16.

[0084] In read / write state 16, when t2 = 63, the state machine transitions to read / write state 17.

[0085] In read / write state 17, when t2 = 255, the state machine transitions to read / write state 18.

[0086] In read / write state 18, when t2 = 127, the state machine transitions to read / write state 19.

[0087] In read / write state 19, when t2 = 255, the state machine transitions to read / write state 20.

[0088] In read / write state 20, when t2 = 112, the state machine transitions to read / write state 21.

[0089] In read / write state 21, when t2 = 255, the state machine transitions to read / write state 22.

[0090] In read / write state 22, when t2 = 255, the state machine transitions to read / write state 23.

[0091] In read / write state 23, when t2 = 63, the state machine transitions to read / write state 24.

[0092] In read / write state 24, when t2 = 255, the state machine transitions to read / write state 25.

[0093] In read / write state 25, when t2 = 127, the state machine transitions to read / write state 26.

[0094] In read / write state 26, when t2 = 255, the state machine transitions to read / write state 27.

[0095] In read / write state 27, when t2 = 191, the state machine transitions to read / write state 28.

[0096] In read / write state 28, when t2 = 255, the state machine transitions to read / write state 1.

[0097] This process continues in a continuous cycle.

[0098] BRAM read control requires controlling the read address according to t2 during the read / write state of the state machine, and simultaneously reading the L BRAMs at address f. addri The data is in the form of (M1,D1,L,x,i,t2), where f addri f is a function representing the read address and t2 during the i-th read / write sub-state. addri The value is rem((t2+d*D1) / M1). Specifically, in this embodiment, the BRAM readout control is as follows: Figure 9 As shown:

[0099] In read / write state 1, data at address t2 is read from four BRAMs simultaneously;

[0100] In read / write state 2, data at address t2+191 is read from four BRAMs simultaneously;

[0101] In read / write state 3, data at address t2-64 is read simultaneously from 4 BRAMs;

[0102] In read / write state 4, data at address t2+128 is read from 4 BRAMs simultaneously;

[0103] In read / write state 5, data at address t2-128 is read from four BRAMs simultaneously;

[0104] In read / write state 6, data at address t2+64 is read simultaneously from 4 BRAMs;

[0105] In read / write state 7, data at address t2-192 is read from four BRAMs simultaneously;

[0106] In read / write state 8, data at address t2 is read from four BRAMs simultaneously;

[0107] In read / write state 9, data at address t2+191 is read from four BRAMs simultaneously.

[0108] In read / write state 10, data at address t2-64 is read simultaneously from 4 BRAMs;

[0109] In read / write state 11, data at address t2+128 is read from four BRAMs simultaneously.

[0110] In read / write state 12, data at address t2-128 is read from four BRAMs simultaneously;

[0111] In read / write state 13, data at address t2+64 is read from 4 BRAMs simultaneously;

[0112] In read / write state 14, data at address t2-192 is read from four BRAMs simultaneously;

[0113] In read / write state 15, data at address t2 is read from four BRAMs simultaneously.

[0114] In read / write state 16, data at address t2+191 is read from four BRAMs simultaneously.

[0115] In read / write state 17, data at address t2-64 is read from four BRAMs simultaneously.

[0116] In read / write state 18, data at address t2+128 is read from four BRAMs simultaneously.

[0117] In read / write state 19, data at address t2-128 is read from four BRAMs simultaneously;

[0118] In read / write state 20, data at address t2+64 is read from four BRAMs simultaneously.

[0119] In read / write state 21, data at address t2-192 is read from four BRAMs simultaneously;

[0120] In read / write state 22, data at address t2 is read from four BRAMs simultaneously;

[0121] In read / write state 23, data at address t2+191 is read from four BRAMs simultaneously;

[0122] In read / write state 24, data at address t2-64 is read from four BRAMs simultaneously;

[0123] In read / write state 25, data at address t2+128 is read simultaneously from 4 BRAMs;

[0124] In read / write state 26, data at address t2-128 is read from four BRAMs simultaneously;

[0125] In read / write state 27, data at address t2+64 is read simultaneously from 4 BRAMs;

[0126] In read / write state 28, data at address t2-192 is read from four BRAMs simultaneously.

[0127] In order to ensure that the read data corresponds one-to-one with the filter coefficients of the sub-filter and its scheduling module, the data read out of the BRAM at the same time needs to be sorted. The sorting method is to move the numbers read out of the first mod((t2+d*D1) / M1) BRAMs to after the numbers read out of the Lth BRAM.

[0128] Specifically, in this embodiment, assuming the number read from the first BRAM is bram1, the number read from the second BRAM is bram2, the number read from the third BRAM is bram3, and the number read from the fourth BRAM is bram4, then the order of the data read directly from the four BRAMs is [bram1, bram2, bram3, bram4]. The ordered sequence of the read data is as follows: Figure 10 As shown:

[0129] In read / write state 1, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0130] In read / write state 2, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0131] In read / write state 3, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0132] In read / write state 4, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0133] In read / write state 5, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0134] In read / write state 6, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0135] In read / write state 7, the numbers read from the first, second, and third BRAMs are moved to the end in sequence, and the output data is [bram4, bram1, bram2, bram3];

[0136] In read / write state 8, the numbers read from the first, second, and third BRAMs are moved to the end in sequence, and the output data is [bram4, bram1, bram2, bram3];

[0137] In read / write state 9, the numbers read from the first, second, and third BRAMs are moved to the end in sequence, and the output data is [bram4, bram1, bram2, bram3];

[0138] In read / write state 10, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0139] In read / write state 11, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0140] In read / write state 12, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0141] In read / write state 13, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0142] In read / write state 14, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0143] In read / write state 15, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0144] In read / write state 16, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0145] In read / write state 17, the numbers read from the first, second, and third BRAMs are moved to the end in sequence, and the output data is [bram4, bram1, bram2, bram3];

[0146] In read / write state 18, the numbers read from the first, second, and third BRAMs are moved to the end in order, and the output data is [bram4, bram1, bram2, bram3];

[0147] In read / write state 19, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0148] In read / write state 20, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0149] In read / write state 21, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0150] In read / write state 22, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0151] In read / write state 23, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0152] In read / write state 24, the numbers read from the first and second BRAMs are moved to the end in sequence, and the output data is [bram3, bram4, bram1, bram2];

[0153] In read / write state 25, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2;

[0154] In read / write state 26, the numbers read from the first, second, and third BRAMs are moved to the end in sequence, and the output data is [bram4, bram1, bram2, bram3];

[0155] In read / write state 27, the numbers read from the first, second, and third BRAMs are moved to the end in sequence, and the output data is [bram4, bram1, bram2, bram3];

[0156] In read / write state 28, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0157] The ordered data is output to the sub-filter and its scheduling module.

[0158] In a specific embodiment of the present invention, the sub-filter and its scheduling module extract the coefficients of the t2*A+1 to (t2+1)*A sub-filters according to the aforementioned count value t2. These coefficients are pre-stored in the FPGA's ROM and convolved with the output of the input data rearrangement module for filtering. The filtered data is then output to the parallel hierarchical FFT module according to a parallelism degree A. Specifically, in this embodiment, the functional block diagram of the sub-filter and its scheduling module is as follows: Figure 4 As shown: The sub-filter parameters are pre-stored in the FPGA's ROM with a bit width of 4*8*16bit (4 represents the sub-filter length, 8 represents the parallelism, and 16bit represents the bit width of a single filter coefficient). The total address length is 256. The parameters are read out in order according to t2, and the filtered data is obtained by convolving the ordered data with the data. The filtered data is then sent to the parallel hierarchical FFT module.

[0159] In one specific embodiment of the present invention, the parallel hierarchical FFT module divides the filtered data into blocks, each block containing A parallel data streams, totaling M1 clock cycles. First, the data output from the A M1-point FFT modules is multiplied by a rotation factor, and then the A-channel data is fused using an A-point parallel FFT to obtain the frequency-shifted data, which is then output to the phase rotation module. Specifically, in this embodiment, the functional block diagram of the parallel hierarchical FFT module is as follows: Figure 5 As shown: First, eight independent 256-point IP cores are called, then multiplied by a rotation factor, and then fused into 8 channels through an 8-point FFT operation before being fed into the phase rotation module. The 8-point FFT operation is implemented using a 3-level butterfly operation.

[0160] In one specific embodiment of the present invention, the phase rotation module multiplies the frequency-shifted signal by a correction rotation factor to correct the phase, such as... Figure 6 As shown. Furthermore, the functional block diagram of the phase rotation module is as follows. Figure 11 As shown: Generally, the phase rotation factor is stored in the ROM of the FPGA and read out sequentially according to t2; in this embodiment, since D / M = 3 / 4, the rotation factor only has four cases: +1, -1, +i, and -i, corresponding to the data remaining unchanged, inverted, real and imaginary parts swapped and real parts inverted, and real and imaginary parts swapped and imaginary parts inverted, respectively, without the need for complex multiplication. It should be noted that the signal after parallel hierarchical FFT is transposed relative to the input signal according to a 2048-point (8 rows and 256 columns) block transpose relationship, that is, the j-th row of each block is the time domain signal of the (j-1)*256 to j*256-1 sub-channel, j = 1, 2, ..., 8. According to the rotation factor e -j2πnmD / M, where m and n represent the nth timing signal of the mth sub-band, m = 0, 1, ..., M-1, n = 0, 1, ... When n = 0: the rotation factor is +1, and the signal is not rotated. When n = 1: the signal in the first clock cycle is the signal of the (j-1)*256th sub-channel, the rotation factor is +1, and the signal is not rotated; the signal in the second clock cycle is the signal of the (j-1)*256+1th sub-channel, the rotation factor is -i, the real and imaginary parts of the signal are swapped and the imaginary part is inverted; the signal in the third clock cycle is the signal of the (j-1)*256+2th sub-channel, the rotation factor is -1, and the signal is inverted; the signal in the fourth clock cycle is the signal of the (j-1)*256+3th sub-channel, the rotation factor is i, the real and imaginary parts of the signal are swapped and the real part is inverted; the fifth clock cycle is the same as the first cycle, and so on until the 256th clock cycle. When n=2: the signal in the first clock cycle is the signal of the (j-1)*256th sub-channel, with a rotation factor of +1, and the signal is not rotated; the signal in the second clock cycle is the signal of the (j-1)*256+1th sub-channel, with a rotation factor of -1, and the signal is inverted; the third clock cycle is the same as the first cycle, and so on until the 256th clock cycle. When n=3: The signal in the first clock cycle is the signal of the (j-1)*256th sub-channel, with a rotation factor of +1, and the signal is not rotated; the signal in the second clock cycle is the signal of the (j-1)*256+1th sub-channel, with a rotation factor of i, the real and imaginary parts of the signal are swapped and the real part is inverted; the fifth clock cycle is the same as the first cycle, and the cycle continues until the 256th clock cycle; the signal in the third clock cycle is the signal of the (j-1)*256+2th sub-channel, with a rotation factor of -1, and the signal is inverted; the signal in the fourth clock cycle is the signal of the (j-1)*256+3th sub-channel, with a rotation factor of -i, the real and imaginary parts of the signal are swapped and the imaginary part is inverted; the fifth clock cycle is the same as the first cycle, and the cycle continues until the 256th clock cycle. Finally, the channelized data is obtained.

[0161] As can be seen from the above embodiments, the method of the present invention uses a data shaping module to transform the fully input A... in The parallel data from one path is reshaped into A-path parallel data, with an effective data duty cycle of A. in / A; The input data is then rearranged according to M phases by the input data rearrangement module, reusing the (M-D+1)th to Mth phases of each M phase data, and outputting A*L data in parallel per clock cycle, with an effective data duty cycle of 1; After filtering by the sub-filter and its scheduling module according to the parallelism A, the filtering coefficients are called for filtering; Then, the channel frequency is shifted by the parallel hierarchical FFT module; Finally, the phase rotation module corrects the phase deflection caused by oversampling to obtain the channelized result. The method of this invention realizes real-time digital channelization with large bandwidth and multiple channels based on oversampling multiphase filter banks within limited resources. The channel division is flexible and solves the problem of spectrum attenuation in traditional channelization technology based on multiphase filter banks, with low resource consumption. It is beneficial for the FPGA implementation of digital channelization technology with higher accuracy and better performance.

[0162] The embodiments described above are merely specific and detailed examples of the embodiments described in this application, and should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the appended claims.

Claims

1. A digital channelization implementation method based on fractional oversampling polyphase filter banks, characterized in that, The method operates in parallel pipeline mode, with a parallel input path count of A. in The number of parallel output paths is A, the number of channels is M, the length of each phase sub-filter is L, and the total filter length is L×M, where A in < A, A in A and L are all positive integers, and the oversampling factor is A / A. in The method includes the following steps: 1) Fill in the input A in The parallel data from one path is reshaped into A-path parallel data; 2) The input data rearrangement module rearranges the input A-channel parallel data according to M phases, and outputs A×L data in parallel each clock cycle. This includes: using the BRAM write control unit to store the data shaped in step 1) into the BRAM storage space in sequence; using the BRAM read control unit to read the data in the BRAM storage space in sequence; using the data rearrangement control state machine to control the state of the BRAM write control unit and the BRAM read control unit; and using the read data sorting unit to sort the data read from the storage space in each clock cycle according to the order required by the subsequent stage and output it. Step 2) includes: Allocate L bits with a width of A × data bit width × 2 and a depth of M / A × 2. x The BRAM space, where x is the depth coefficient, whose value is an integer greater than or equal to 0; The signal clock of the data after shaping in step 1) is counted, and the count value is t1, t1=0, 1, ..., M1×L -1, where M1 is the intermediate parameter of the channel and M1=M / A; when t1=M1×L-1, the next time step t1=0; the A data input at time t1 is stored in the (l+1)th BRAM at the address rem(t1 / M1), where the BRAM label l=mod(t1 / M1), rem() represents the remainder operation, and mod() represents the modulo operation; The clock of the signal output by the input data rearrangement module is counted, and the count value is t2, where t2 = 0, 1, ..., M1-1. When t2 = M1-1, the next time step is t2 = 0. The input data rearrangement module controls the jump of the data rearrangement control state machine according to the values ​​of t1 and t2. The step of controlling the state machine transition based on the values ​​of t1 and t2 includes: The change in count value t1 causes a change in l. When l = L-1 and rem(t1 / D1) = D1-1, the state machine transitions to the read / write state, and t2 starts counting. The read / write state is divided into I sub-states, initially read / write state 1, transitioning to read / write state 2 when t2 = f1, and so on. i When i = 1, the state transitions to read / write state i+1, where i = 1, 2, ..., I; when i = I, the next state is i = 1, where f i f represents the condition for transitioning from the i-th read / write sub-state to the (i+1)-th read / write sub-state. i The value is M1-1 or rem ((d×(M1-D1)-1) / M1), and the condition is true whichever is counted first in t2. d is the number of times t2 counts to M1 starting from read / write state 1. In the read / write state of the data rearrangement control state machine, L BRAMs at address f are read simultaneously. addri The data is then sorted so that there is a one-to-one correspondence between the data and the filter coefficients, where f addri The function f represents the read address and t2 during the i-th read / write sub-state; addri The value is rem ((t2+ d× D1) / M1); 3) Filter the data output in step 2) according to the parallelism A and the filter coefficients. 4) Perform channel frequency shifting on the filtered data; 5) Multiply the frequency-shifted signal by the correction rotation factor to correct the phase deflection caused by oversampling and obtain the channelized result.

2. The method according to claim 1, characterized in that, In step 1), the input signal at each clock cycle is valid, and the duty cycle of the valid signal is 1; the A signal input at full time slot... in The parallel data from one path is shaped into A parallel data paths, and the duty cycle of the output effective data is A. in / A.

3. The method according to claim 1, characterized in that, The process of reordering the data to be read includes: moving the numbers read from the first mod ((t2+ d× D1) / M1) BRAMs to after the numbers read from the Lth BRAM.

4. The method according to claim 1, characterized in that, Step 3) is as follows: Based on the clock count value t2 of the output signal, extract the coefficients of the t2×A+1~(t2+1)×A sub-filters. The coefficients are pre-stored in the ROM of the FPGA and convolved with the output data of step 2). The filtered data is output according to the parallelism A.

5. The method according to claim 3, characterized in that, Step 4) involves dividing the filtered data from step 3) into blocks, each containing A parallel data streams for a total of M1 clock cycles. First, the data output from the A M1-point FFT modules is multiplied by the rotation factor, and then the A-point parallel FFT is used to fuse the A channels to obtain the frequency-shifted data.

6. The method according to claim 3, characterized in that, In step 5), the value of the corrective rotation factor is: , where m and n represent the nth timing signal of the mth sub-band, m=0, 1, ..., M-1, n=0, 1, ...

7. A digital channelization implementation system based on fractional oversampling polyphase filter banks, implementing the method of any one of claims 1-6, characterized in that, include: The data shaping module is used to shape the input A. in The parallel data from one path is reshaped into A-path parallel data; The input data rearrangement module includes a BRAM write control unit, a BRAM read control unit, a data rearrangement control state machine, and a read data sequencing unit. The BRAM write control unit stores the shaped data sequentially into the BRAM storage space, and the BRAM read control unit reads the data from the BRAM storage space sequentially. The data rearrangement control state machine controls the states of the BRAM write control unit and the BRAM read control unit. The read data sequencing unit rearranges the data read from the storage space in each clock cycle according to the order required by the subsequent stage. The sub-filter and its scheduling module, which calls the filtering coefficients according to the parallelism A, filters the data output by the input data rearrangement module. The parallel hierarchical FFT module performs channel frequency shifting on the data filtered by the sub-filters and their scheduling modules. The phase rotation module multiplies the frequency-shifted signal from the parallel hierarchical FFT module by a correction rotation factor to correct the phase deflection caused by oversampling and obtain the channelized result.

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