Multi-channel CANFD optical conversion communication system and method based on ZYNQ

Abstract

The invention provides a multi-channel CANFD (Controller Area Network Forwarding Detection) communication system and method based on ZYNQ, the communication system comprises an all-programmable system on chip ZYNQ, a DDR (Double Data Rate) memory, an optical transceiver module and a CANFD transceiver module, the all-programmable system on chip ZYNQ comprises a processing system PS and a programmable logic PL, and the PS and the PL are communicated through a GP port and an HP port. And the DDR memory is connected with the ZYNQ and is used for providing an application software running memory and storing CANFD receiving data and SRIO receiving and transmitting data. The PL comprises an SRIO control module, an SRIO IP, an AXI interconnection module and a multi-path CANFD IP module, and the PS and the SRIO control module of the PL are interconnected through a GP0 and an HP0. By means of the method, multi-channel CANFD conversion optical communication is achieved, and the problems that a traditional CANFD bus is not high in transmission rate and limited in transmission distance are solved.

Description

A multi-channel CANFD-to-optical communication system and method based on ZYNQ Technical Field

[0001] This invention relates to the field of computer bus communication technology, specifically to a multi-channel CANFD-to-optical communication system and method based on ZYNQ. Background Technology

[0002] With the advancement of communication technology and the widespread application of bus technology, the requirements for bus bandwidth and transmission rate in fields such as automotive electronics are constantly increasing. The traditional CAN (1Mbit / s, 8-byte payload) can hardly meet the application needs, so CANFD has emerged. Its data frame has been increased from 8 bytes to 64 bytes compared to CAN, and the transmission rate can reach up to 8Mbit / s. It is also backward compatible with the CAN protocol, so it has gradually replaced the CAN bus and is widely used in fields such as industrial control and aerospace.

[0003] Rapid IO is a next-generation high-speed interconnect technology based on packet switching, designed for embedded system development. It offers high reliability and performance, primarily used for internal interconnection within embedded systems, supporting chip-to-chip and board-to-board communication. SRIO (Serial Rapid IO) is a high-speed serial Rapid IO protocol characterized by low latency, high bandwidth (supporting data transmission rates up to 25Gbps), and high reliability. It is commonly used in data centers, communication equipment, and avionics.

[0004] The CANFD bus offers a certain speed improvement compared to the CAN bus, but it is significantly inferior to the SRIO bus. Although the CANFD bus can transmit over distances of tens or even hundreds of meters, the transmission rate drops to tens of Kbps as the transmission distance increases, which cannot meet the requirements for high-speed data transmission. SRIO, on the other hand, is designed for internal interconnection of embedded devices, and its transmission distance is generally less than 1 meter, making it unsuitable for long-distance transmission. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a multi-channel CANFD-to-optical communication system and method based on ZYNQ, thereby solving the problems mentioned in the background. The present invention realizes multi-channel CANFD-to-optical communication, solving the problems of low transmission rate and short transmission distance of traditional CANFD bus.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution: a multi-channel CANFD-to-optical communication system based on ZYNQ, the communication system comprising a fully programmable system-on-a-chip (ZYNQ), a DDR memory, an optical transceiver module, and a CANFD transceiver module, wherein the fully programmable system-on-a-chip (ZYNQ) comprises a processing system (PS) and a programmable logic (PL), and the PS and PL communicate with each other through GP and HP ports;

[0007] The PL includes an SRIO control module, an SRIO IP, an AXI interconnect module, and a multi-channel CANFD IP module. The PS is interconnected with the PL's SRIO control module via GP0 and HP0. The GP0 port is used for command issuance, and the HP0 port is used for SRIO data transmission. The SRIO controller module is connected to the SRIO IP and is used for framing and parsing SRIO data protocols, as well as generating interrupt signals. The SRIO IP is connected to the optical transceiver module. The AXI interconnect module is interconnected with the PS via GP1, and the AXI interconnect module and the multi-channel CANFD IP module are interconnected via the AXI bus. The multi-channel CANFD IP module is connected to the CANFD transceiver module.

[0008] Furthermore, the DDR memory is connected to the ZYNQ and is used to provide application software running memory and storage for CANFD reception and SRIO transmission and reception data.

[0009] Furthermore, the CANFD transceiver module is interconnected with an external system via the CANFD bus, and is used to convert the digital signal output by the CANFD IP module into a CANFD bus differential signal, and to convert the CANFD bus differential signal into a digital signal and input it to the CANFD IP module.

[0010] Furthermore, the optical transceiver module is used to convert SRIO electrical signals into optical signals, and optical signals into electrical signals, and to lead out an optical fiber connector for interconnection with external optical fibers.

[0011] A communication method using the above-described communication system, the communication method comprising PL logic design and PS software design, wherein the PL logic design includes:

[0012] S1.1 Add ZYNQ7 Processing System IP and enable S_AXI_HP0_Interface for the PL-side SRIO control module to access DDR memory data via DMA. The interface clock frequency is 125MHz.

[0013] S1.2 Add 32 CANFD IPs to enable 32-channel CANFD protocol data output and parsing;

[0014] S1.3 Add multiple CANFD IPs to enable CANFD protocol data output and parsing;

[0015] S1.4 Add Processor System Reset IP to realize synchronous processing of asynchronous reset signals and output multiple reset signals;

[0016] S1.5 Add SRIO IP to implement the physical layer, transport layer and logic layer functions of the SRIO interface;

[0017] S1.6 Add an SRIO control module. The SRIO control module receives SRIO transaction type, data length, and data frame memory address configuration information from the PS end through M_AXI_GP0.

[0018] Furthermore, in S1.1, two clocks are set, one as the AXI bus clock and the other as the reference clock for the CANFD IP; the DDR3 memory interface is configured for interconnection with DDR memory; and the M_AXI_GP0 port is enabled for register read / write and control with the SRIO control module.

[0019] Furthermore, enable the M_AXI_GP1 port for interconnection with the AXI to realize register reading, writing and control of the CANFD IP module; set one interrupt, SRIO data reception interrupt.

[0020] Furthermore, in S1.6, the SRIO control module obtains the data frame cached in the DDR memory through the HP0 port, generates the corresponding data packet format and generates an AXI bus data stream, and outputs it to the SRIO IP; the SRIO control module parses the AXI data stream input by the SRIO IP and writes the parsed data into the DDR memory through HP0, while generating an interrupt signal.

[0021] Furthermore, the PS software design includes:

[0022] S2.1 The PS completes the initialization of the clock, DDR controller, interrupt controller, and timer;

[0023] S2.2 The PS initializes the multi-channel CANFD IP via the GP1 port, including the working mode and baud rate;

[0024] S2.3 The PS initializes the SRIO IP through the GP0 port;

[0025] S2.4 The PS periodically queries and receives CANFD data from multiple CANFD IPs, and frames the CANFD data according to the channel number and the specified protocol.

[0026] S2.5 After the PS completes the data framing of all CANFD IP channels, it caches the data at a specified address in DDR memory;

[0027] S2.6 The PS sends the memory address and data length of the CANFD data frame cached in DDR to the SRIO control module through the GP0 port;

[0028] S2.7 After receiving the SRIO message, the SRIO control module generates an interrupt signal. After receiving the interrupt, the PS reads the CANFD data frame from the specified DDR cache space.

[0029] S2.8 The PS parses the CANFD data frame according to the data frame format and sends the CANFD data to the corresponding CANFD IP through the GP1 port according to the channel number information.

[0030] The beneficial effects of this invention are:

[0031] 1. This ZYNQ-based multi-channel CANFD to optical communication system utilizes the PL section of the fully programmable system-on-a-chip ZYNQ to realize multi-channel CANFD data transmission and reception, and implements high-speed SRIO interface protocol and logic control on the PL.

[0032] 2. This ZYNQ-based multi-channel CANFD-to-optical communication method achieves the conversion between electrical and optical signals by utilizing an optical transceiver module, enabling long-distance high-speed transmission. Moreover, optical fiber transmission has advantages such as high bandwidth, low loss, and strong anti-interference. Attached Figure Description

[0033] Figure 1 is a schematic diagram of a multi-channel CANFD-to-optical communication system based on ZYNQ according to the present invention;

[0034] Figure 2 is a data transmission flow diagram of the CANFD-to-optical communication system of the present invention;

[0035] Figure 3 is a data reception flow diagram of the CANFD-to-optical communication system of the present invention. Detailed Implementation

[0036] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0037] Please refer to Figures 1 to 3. This invention provides the following technical solution: a multi-channel CANFD-to-optical communication system based on ZYNQ. This communication system utilizes the PL (Programmable Logic Controller) section of the fully programmable system-on-a-chip (ZYNQ) to realize multi-channel CANFD data transmission and reception, and implements a high-speed SRIO interface protocol and logic control on the PL. Specifically, it includes:

[0038] The ZYNQ fully programmable system-on-a-chip includes DDR memory, optical transceiver modules, and CANFD transceiver modules.

[0039] The fully programmable system-on-a-chip (ZYNQ) comprises a processing system (PS) and a programmable logic unit (PL). The PS and PL communicate via GP and HP ports. The PL includes an SRIO control module, SRIO IP, an AXI interconnect module, and a multi-channel CANFD IP module. The PS and the PL's SRIO control module are interconnected via GP0 and HP0, where GP0 is used for command issuance and HP0 for SRIO data transmission. The SRIO controller module is connected to the SRIO IP and is used for framing and parsing SRIO data protocols, as well as generating interrupt signals. The SRIO IP is connected to the optical transceiver module. The AXI interconnect module is interconnected with the PS via GP1, and the AXI interconnect module and the multi-channel CANFD IP module are interconnected via an AXI bus. The multi-channel CANFD IP module is connected to the CANFD transceiver module.

[0040] The DDR memory is connected to the ZYNQ and is used to provide application software running memory and storage for CANFD reception and SRIO transmission and reception data.

[0041] The CANFD transceiver module is interconnected with an external system via the CANFD bus. It is used to convert the digital signal output by the CANFD IP module into a CANFD bus differential signal, and to convert the CANFD bus differential signal into a digital signal and input it to the CANFD IP module.

[0042] The optical transceiver module converts SRIO electrical signals into optical signals and optical signals into electrical signals, and leads out an optical fiber connector to interconnect with external optical fibers to achieve long-distance high-speed transmission. The optical transceiver module selected is model HTA8545A, with a working wavelength of 850nm.

[0043] This embodiment also provides a multi-channel CANFD to optical communication method based on ZYNQ, including PL logic design and PS software design;

[0044] PL logic design includes:

[0045] 1. Add a ZYNQ7 Processing System IP, enable S_AXI_HP0_Interface for the PL-side SRIO control module to access DDR memory data via DMA, with an interface clock frequency of 125MHz; configure two clocks, one as the AXI bus clock at 100MHz and the other as the CANFD IP reference clock at 80MHz; configure a DDR3 memory interface for interconnection with DDR memory, with a DDR clock frequency of 533.333MHz; enable the M_AXI_GP0 port for register read / write and control of the SRIO control module, with an interface clock frequency of 100MHz; enable the M_AXI_GP1 port for interconnection with the AXI to realize register read / write and control of the CANFD IP module, with an interface clock frequency of 100MHz; configure one interrupt, the SRIO data reception interrupt;

[0046] 2. Add 32 CANFD IPs to enable 32-channel CANFD protocol data output and parsing;

[0047] 3. Add AXI Interconnect IP and configure it as 32 AXI master interfaces (M00_AXI~M31_AXI) and 1 slave interface (S00_AXI). The 32 master interfaces are connected to the AXI slave interfaces of the 32 CANFD IPs respectively, and the 1 slave interface (S00_AXI) is connected to the M_AXI_GP1 port to realize the configuration and data transmission and reception of multiple CANFD IPs on the PS side.

[0048] 4. Add Processor System Reset IP to realize synchronous processing of asynchronous reset signals and output multiple reset signals;

[0049] 5. Add SRIO IP to implement the physical layer, transport layer and logic layer functions of the SRIO interface. Set the lane width to 2x, the link speed to 2.5Gb / s, the reference clock to 125MHz, use the HELLO Format, support Write / Read / Doorbell / SWrite transactions, and set the device ID width to 16 bits.

[0050] 6. Add an SRIO control module. The SRIO control module receives configuration information such as SRIO transaction type, data length, and data frame memory address from the PS end through M_AXI_GP0. It obtains the data frame cached in the DDR memory through the HP0 port, generates the corresponding data packet format, generates an AXI bus data stream, and outputs it to the SRIO IP. The SRIO control module parses the AXI data stream input by the SRIO IP and writes the parsed data into the DDR memory through HP0, while generating an interrupt signal.

[0051] PS software design:

[0052] 1. The PS completes the initialization of the clock, DDR controller, interrupt controller, timers, etc.

[0053] 2. The PS initializes the multi-channel CANFD IP via the GP1 port, including the working mode and baud rate. The arbitration domain baud rate is set to 1 Mbps, and the data domain baud rate is set to 4 Mbps.

[0054] 3. The PS initializes the SRIO IP via the GP0 port;

[0055] 4. The PS periodically queries and receives CANFD data from multiple CANFD IPs, and frames the CANFD data according to the channel number and the specified protocol. The periodic query period is 5ms.

[0056] 5. After the PS completes the data framing of all CANFD IP channels, it caches the data at a specified address in DDR memory;

[0057] 6. The PS sends the memory address and data length of the CANFD data frame cached in DDR to the SRIO control module through the GP0 port. The data flow diagram is shown in Figure 2.

[0058] 7. After receiving the Doorbell message, the SRIO control module generates an interrupt signal. Upon receiving the interrupt, the PS reads the CANFD data frame from the specified DDR cache space.

[0059] 8. The PS parses the CANFD data frame according to the data frame format, and sends the CANFD data to the corresponding CANFD IP through the GP1 port according to the channel number information. The data flow diagram is shown in Figure 3.

[0060] This invention uses the above method to realize multi-channel CANFD data transmission and reception, and implements high-speed SRIO interface protocol and logic control on PL. By using optical transceiver module to realize the conversion of electrical signals and optical signals, long-distance high-speed transmission is achieved.

[0061] The above method achieves the conversion between electrical and optical signals by using an optical transceiver module, enabling long-distance high-speed transmission. Moreover, optical fiber transmission has advantages such as high bandwidth, low loss, and strong anti-interference.

[0062] The foregoing has shown and described the basic principles and main features of the present invention and its advantages. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0063] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A multi-channel CANFD-to-optical communication system based on ZYNQ, characterized in that: The communication system includes a fully programmable system-on-a-chip (ZYNQ), DDR memory, an optical transceiver module, and a CANFD transceiver module. The ZYNQ comprises a processing system (PS) and a programmable logic unit (PL). The PS and PL communicate via GP and HP ports. The PL includes an SRIO control module, SRIO IP, an AXI interconnect module, and a multi-channel CANFD IP module. The PS and the PL's SRIO control module are interconnected via GP0 and HP0. The GP0 port is used for command issuance, and the HP0 port is used for SRIO data transmission. The SRIO controller module is connected to the SRIO IP and is used for framing and parsing SRIO data protocols, as well as generating interrupt signals. The SRIO IP is connected to the optical transceiver module. The AXI interconnect module is interconnected with the PS via GP1, and the AXI interconnect module and the multi-channel CANFD IP module are interconnected via the AXI bus. The multi-channel CANFD IP module is connected to the CANFD transceiver module.

2. The ZYNQ-based multi-channel CANFD-to-optical communication system according to claim 1, characterized in that: The DDR memory is connected to the ZYNQ and is used to provide application software running memory and storage for CANFD reception and SRIO transmission and reception data.

3. The ZYNQ-based multi-channel CANFD-to-optical communication system according to claim 1, characterized in that: The CANFD transceiver module is interconnected with an external system via the CANFD bus. It is used to convert the digital signal output by the CANFD IP module into a CANFD bus differential signal, and to convert the CANFD bus differential signal into a digital signal and input it to the CANFD IP module.

4. A multi-channel CANFD-to-optical communication system based on ZYNQ according to claim 1, characterized in that: The optical transceiver module is used to convert SRIO electrical signals into optical signals, and optical signals into electrical signals, and to lead out an optical fiber connector for interconnection with external optical fibers.

5. A communication method using the communication system as described in claim 1, characterized in that: The communication method includes PL logic design and PS software design. The PL logic design includes: S1.1 Adding a ZYNQ7 Processing System IP and enabling S_AXI_HP0_Interface for the PL-side SRIO control module to access DDR memory data via DMA; the interface clock frequency is 125MHz. S1.2 Adding a 32-channel CANFD IP to implement 32-channel CANFD protocol data output and parsing. S1.3 Adding multiple CANFD IPs to implement CANFD protocol data output and parsing. S1.4 Adding a Processor System Reset IP to implement synchronous processing of asynchronous reset signals and output multiple reset signals. S1.5 Adding an SRIO IP to implement the physical layer, transport layer, and logic layer functions of the SRIO interface. S1.6 Adding an SRIO control module, which receives SRIO transaction type, data length, and data frame memory address configuration information from the PS side via M_AXI_GP0.

6. The communication method according to claim 5, characterized in that: In S1.1, two clocks are set, one as the AXI bus clock and the other as the reference clock for the CANFD IP; the DDR3 memory interface is configured for interconnection with DDR memory; and the M_AXI_GP0 port is enabled for register read / write and control with the SRIO control module.

7. The communication method according to claim 6, characterized in that: Enable the M_AXI_GP1 port for interconnection with the AXI to enable register reading, writing, and control of the CANFD IP module; set one interrupt for receiving SRIO data.

8. The communication method according to claim 6, characterized in that: In S1.6, the SRIO control module obtains the data frame cached in the DDR memory through the HP0 port, generates the corresponding data packet format and generates the AXI bus data stream, and outputs it to the SRIO IP; the SRIO control module parses the AXI data stream input by the SRIO IP and writes the parsed data into the DDR memory through HP0, while generating an interrupt signal.

9. The communication and method according to claim 5, characterized in that: The PS software design includes: S2.1, the PS initializes the clock, DDR controller, interrupt controller, and timer; S2.2, the PS initializes the multi-channel CANFD IP via GP1 port, including the working mode and baud rate; S2.3, the PS initializes the SRIO IP via GP0 port; S2.4, the PS periodically queries and receives CANFD data from the multi-channel CANFD IP, and frames the CANFD data according to the channel number and the specified protocol; S2.5, after framing all CANFD IP channels, the PS caches the data at a specified address in the DDR memory; S2.6, the PS sends the memory address and data length of the cached CANFD data frame in the DDR to the SRIO control module via GP0 port; S2.7, after receiving the SRIO message, the SRIO control module generates an interrupt signal, and the PS, upon receiving the interrupt, reads the CANFD data frame from the specified DDR cache space; S2.8, the PS parses the CANFD data frame according to the data frame format, and sends the CANFD data to the corresponding CANFD via GP1 port according to the channel number information. IP.

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