Pulse width modulation signal driver

Abstract

An isolated driver circuit for a pulse width modulated signal. The isolation driver circuit comprises a rising edge detection circuit, a falling edge detection circuit and a decoder. The rising edge detection circuit and the falling edge detection circuit detect a rising edge and a falling edge of an input pulse width modulation signal respectively, and output a corresponding rising edge detection signal and a falling edge detection signal capacitively isolated from the input pulse width modulation signal respectively. The decoder receives the rising edge detection signal and the falling edge detection signal, and outputs respective rising and falling edges of the output pulse width modulated signal that are temporally aligned with respective rising and falling edges of the input pulse width modulated signal. Accordingly, information stored in the pulse width of the input pulse width modulated signal is retained in the output pulse width modulated signal with high fidelity.

Description

Technical Field

[0001] Electronic circuits are often used to perform a variety of functions, one example of which is analog signal amplification. Analog signal amplification can be useful when the original analog signal does not have enough power to properly drive an output device. Accordingly, in order to properly drive such an output device, the analog input signal can pass through some kind of analog signal amplification circuit. Background Art

[0002] One type of analog signal amplification circuit is known as a "Class D amplifier" and is commonly used to amplify audio signals to drive speakers and the like. Class D amplifiers use pulse width modulation (PWM) to digitally convert a relatively small analog input signal into an amplified analog output signal. In the case of a Class D amplifier, a relatively small analog input signal (audio analog signal) is compared to a repetitive triangular waveform to generate a pulse width modulated signal, where the pulse width at any given time represents the value of the analog input signal. The pulse width modulated signal itself is then amplified, for example, using a half-bridge driver. The resulting amplified pulse width modulated signal is then passed through a low pass filter to extract the analog output signal, which is ideally an amplified form of the analog input signal. This amplified analog output signal has much greater power than the analog input signal and can then be used to properly drive the audio output device.

[0003] The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as described above.Rather, this background is merely provided to illustrate one example technology area in which some embodiments described herein may be practiced. Summary of the invention

[0004] This Summary is provided to introduce selected concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] Embodiments described herein relate to an isolation driver circuit for a pulse width modulated signal. The isolation driver circuit is configured to generate a rising edge of an output pulse width modulated signal in response to detecting a rising edge of an input pulse width modulated signal, and to generate a falling edge of an output pulse width modulated signal in response to detecting a falling edge of the input pulse width modulated signal. In addition, the generation of the rising edge and the falling edge is performed so that the time between the rising edge and the falling edge of the output pulse width modulated signal is closer to the time between the rising edge and the falling edge of the input pulse width modulated signal. In other words, the pulse width of the input pulse width modulated signal is highly accurately maintained in the pulse width of the output pulse width modulated signal. Since information is represented in the pulse width modulated signal using the pulse width, this means that the information present in the input pulse width modulated signal is retained in the output pulse width modulated signal with high fidelity.

[0006] The isolation driver circuit includes a rising edge detection circuit, a falling edge detection circuit and a decoder. The rising edge detection circuit detects the rising edge of the input pulse width modulation signal and outputs a corresponding rising edge detection signal capacitively isolated from the input pulse width modulation signal. This can be achieved by using a clock to modulate the input pulse width modulation signal, wherein the clock signal has a rising edge that is consistent with the rising edge of the input pulse width modulation signal.

[0007] Similarly, the falling edge detection circuit detects the falling edge of the input pulse width modulated signal and outputs a corresponding falling edge detection signal capacitively isolated from the input pulse width modulated signal. However, this is achieved by modulating the input pulse width modulated signal using a separate clock signal, wherein the separate clock signal has a rising edge that coincides with the falling edge of the input pulse width modulated signal (and the rising edge of the other clock signal coincides with the rising edge of the input pulse width modulated signal).

[0008] When the decoder receives the rising edge detection signal from the rising edge detection circuit, the decoder outputs the rising edge of the output pulse width modulation signal. Similarly, when the decoder receives the falling edge detection signal from the falling edge detection circuit, the decoder outputs the falling edge of the output pulse width modulation signal. Accordingly, the decoder generates a rising edge in the output signal that is aligned in time with the rising edge of the input signal, and generates a falling edge in the output signal that is aligned in time with the falling edge of the input signal. This more accurately maintains the pulse width, and therefore allows information to be transmitted with higher fidelity when using pulse width modulation signals.

[0009] Recall that the rising edge detection signal and the falling edge detection signal are capacitively isolated from the input PWM signal. This capacitive isolation allows the output PWM signal to be generated using a power supply different from the power supply used to generate the input PWM signal. Thus, the isolated driver circuit provides isolation, thereby achieving high power drive of the output PWM signal even if the input PWM signal has a low power.

[0010] By way of example only, the output pulse width modulated signal may be used to drive one or more power transistors to accurately generate an amplified output pulse width modulated signal that is an amplified version of the input pulse width modulated signal. This may occur, for example, if the isolated driver circuit is included in a class D amplifier. In this case, since the pulse width is highly maintained, the analog input signal to the class D amplifier will be amplified with high fidelity in the class D amplifier.

[0011] Additional features and advantages will be set forth in the following description, and in part will be apparent from the description, or may be learned by practicing the teachings herein. The features and advantages of the present invention may be realized and obtained by the instruments and combinations particularly pointed out in the appended claims. The features of the present invention will become more apparent from the following description and the appended claims, or may be learned by practicing the present invention as described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to describe the manner in which the advantages and features of the circuits, systems, and methods described herein can be obtained, a more particular description of the embodiments briefly described herein will be presented by reference to specific embodiments illustrated in the accompanying drawings. It should be understood that these drawings depict only typical embodiments of the circuits, systems, and methods described herein and are, therefore, not to be considered limiting of their scope. Certain circuits, systems, and methods will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0013] Figure 1 An isolated driver circuit is shown that can practice the principles described herein and is merely one example of an isolated driver circuit consistent with the principles described herein.

[0014] Figure 2 shows an isolated driver circuit that is Figure 1 An example of an isolated driver circuit.

[0015] Figure 3 A signal diagram showing an input signal before modulation, a first modulated signal, a second modulated signal, and an output signal representing the input signal and generated by using the first modulated signal and the second modulated signal is shown.

[0016] FIG. 4 illustrates a signal diagram showing an example of signals involved in modulating an input signal to generate an output signal according to the prior art, wherein only one clock signal and one modulator are used.

[0017] Figure 5 shows the fast start clock, which is Figure 2 Examples of each of the clocks in the .

[0018] Figure 6 An isolated driver circuit based on the principles described herein is presented, including Figure 2 Multiple instances of isolated driver circuits.

[0019] Figure 7 shows an isolated driver circuit that is Figure 2 An example of an isolated driver circuit. DETAILED DESCRIPTION

[0020] Embodiments described herein relate to an isolation driver circuit for a pulse width modulated signal. The isolation driver circuit is configured to generate a rising edge of an output pulse width modulated signal in response to detecting a rising edge of an input pulse width modulated signal, and to generate a falling edge of an output pulse width modulated signal in response to detecting a falling edge of the input pulse width modulated signal. In addition, the generation of the rising edge and the falling edge is performed so that the time between the rising edge and the falling edge of the output pulse width modulated signal is closer to the time between the rising edge and the falling edge of the input pulse width modulated signal. In other words, the pulse width of the input pulse width modulated signal is highly accurately maintained in the pulse width of the output pulse width modulated signal. Since information is represented in the pulse width modulated signal using the pulse width, this means that the information present in the input pulse width modulated signal is retained in the output pulse width modulated signal with high fidelity.

[0021] The isolation driver circuit includes a rising edge detection circuit, a falling edge detection circuit and a decoder. The rising edge detection circuit detects the rising edge of the input pulse width modulation signal and outputs a corresponding rising edge detection signal capacitively isolated from the input pulse width modulation signal. This can be achieved by using a clock to modulate the input pulse width modulation signal, wherein the clock signal has a rising edge that is consistent with the rising edge of the input pulse width modulation signal.

[0022] Similarly, the falling edge detection circuit detects the falling edge of the input pulse width modulated signal and outputs a corresponding falling edge detection signal capacitively isolated from the input pulse width modulated signal. However, this is achieved by modulating the input pulse width modulated signal using a separate clock signal, wherein the separate clock signal has a rising edge that coincides with the falling edge of the input pulse width modulated signal (and the rising edge of the other clock signal coincides with the rising edge of the input pulse width modulated signal).

[0023] When the decoder receives the rising edge detection signal from the rising edge detection circuit, the decoder outputs the rising edge of the output pulse width modulation signal. Similarly, when the decoder receives the falling edge detection signal from the falling edge detection circuit, the decoder outputs the falling edge of the output pulse width modulation signal. Accordingly, the decoder generates a rising edge in the output signal that is aligned in time with the rising edge of the input signal, and generates a falling edge in the output signal that is aligned in time with the falling edge of the input signal. This more accurately maintains the pulse width, and therefore allows information to be transmitted with higher fidelity when using pulse width modulation signals.

[0024] Recall that the rising edge detection signal and the falling edge detection signal are capacitively isolated from the input PWM signal. This capacitive isolation allows the output PWM signal to be generated using a power supply different from the power supply used to generate the input PWM signal. Thus, the isolated driver circuit provides isolation, thereby achieving high power drive of the output PWM signal even if the input PWM signal has a low power.

[0025] By way of example only, the output pulse width modulated signal may be used to drive one or more power transistors to accurately generate an amplified output pulse width modulated signal that is an amplified version of the input pulse width modulated signal. This may occur, for example, if the isolated driver circuit is included in a class D amplifier. In this case, since the pulse width is highly maintained, the analog input signal to the class D amplifier will be amplified with high fidelity in the class D amplifier.

[0026] Figure 1 An isolated driver circuit 100 is shown that can practice the principles described herein and is merely one example of an isolated driver circuit consistent with the principles described herein. The isolated driver circuit 100 processes an input pulse width modulated signal 101 to generate an output pulse width modulated signal 102 .

[0027] A pulse width modulated signal is a signal in which information is represented by the width of a pulse. As an example only, an input pulse width modulated signal 101 shows three pulses 101A, 101B, and 101C. The pulse width of pulse 101A is relatively wide, the pulse width of pulse 101C is relatively narrow, and the pulse width of pulse 101B is somewhere in between. The width of each of pulses 101A, 101B, and 101C represents information, and therefore information can be extracted based on the value of the pulse width.

[0028] The principles described herein are not limited to what the information represented actually is. However, by way of example only, the information may be an analog waveform, wherein the width of a pulse at any given time corresponds to the amplitude of the analog waveform at that given time. That is, a higher duty cycle of the pulse width may correspond to a higher amplitude of the analog waveform, while a lower duty cycle of the pulse width may correspond to a lower amplitude of the analog waveform. Thus, in this case, an analog waveform may be generated from a pulse train based on the pulse width of the pulses.

[0029] The isolated driver circuit 100 can be used to process an input pulse width modulated signal 101 into an output pulse width modulated signal 102 in such a manner that the power supply of the output pulse width modulated signal 102 is isolated from the power supply of the input pulse width modulated signal 101, hence the term "isolated driver circuit". Isolating the power supply of the output pulse width modulated signal 102 from the power supply of the input pulse width modulated signal 101 enables high power driving of the output pulse width modulated signal 102, even if the input pulse width modulated signal 101 is low power. Therefore, sensitive components contained within the input side of the isolated driver circuit 100 can be protected from the much higher power present within the output side of the isolated driver 100.

[0030] Ideally, the isolated driver circuit 100 ensures that the pulse width in the input pulse width modulated signal 101 is substantially the same as the pulse width in the output pulse width modulated signal 102. For example, pulses 102A to 102C of the output pulse width modulated signal 102 correspond to corresponding pulses 101A to 101C of the input pulse width modulated signal 101. As shown, the pulse width of pulse 102A is approximately the same as the pulse width of pulse 101A, the pulse width of pulse 102B is approximately the same as the pulse width of pulse 101B, and the pulse width of pulse 102C is approximately the same as the pulse width of pulse 101C. Therefore, the information represented by the pulse width in the input pulse width modulated signal 101 is also represented in the output pulse width modulated signal 102. Of course, a perfect match of the output pulse width to the input pulse width is actually impossible. However, according to the principles described herein, the output pulse width closely matches the input pulse width.

[0031] According to the principles described herein, this is achieved by closely aligning the rising and falling edges of the input pulse width modulated signal 101 in time with the corresponding rising and falling edges of the output pulse width modulated signal 102. To this end, the isolated driver circuit 100 generates a rising edge of the output pulse width modulated signal 102 in response to detecting a rising edge of the input pulse width modulated signal 101, and generates a falling edge of the output pulse width modulated signal 102 in response to detecting a falling edge of the input pulse width modulated signal 101 having a modulated signal.

[0032] The generation of the rising and falling edges is performed such that the amount of time between the rising and falling edges of the output pulse width modulated signal 102 is substantially close to the amount of time between the rising and falling edges of the input pulse width modulated signal 101. As an example, in response to detecting the rising edge of pulse 101A of the input pulse width modulated signal 101, the isolated driver circuit 100 will generate the rising edge of pulse 102A of the output pulse width modulated signal 102. Further, in response to detecting the falling edge of pulse 101A of the input pulse width modulated signal 101, the isolated driver circuit 100 will generate the falling edge of pulse 102A of the output pulse width modulated signal 102. Importantly, this is done such that the amount of time between the rising and falling edges of pulse 102A is very close to the amount of time between the rising and falling edges of pulse 101A.

[0033] The same operation can also be performed for any corresponding pulses of the input pulse width modulation signal 101 and the output pulse width modulation signal 102 to align the appropriate rising and falling edges. Accordingly, the pulse width of the input pulse width modulation signal 101 is highly accurately maintained in the pulse width of the output pulse width modulation signal 102. Therefore, the information represented by the pulse width of the input pulse width modulation signal 101 is retained in the output pulse width modulation signal 102 with high fidelity.

[0034] In order to process the input pulse width modulated signal 101 into the output pulse width modulated signal 102, the isolation driver circuit 100 includes a rising edge detection circuit 110, a falling edge detection circuit 120 and a decoder 130. As shown by the arrow line 111, the rising edge detection circuit 110 detects the rising edge of the input pulse width modulated signal 101. In response, as shown by the arrow line 112, the rising edge detection circuit 110 outputs a corresponding rising edge detection signal to the decoder 130. This can be achieved by modulating the input pulse width modulated signal 101 with a clock, wherein the clock signal has a rising edge that coincides with the rising edge of the input pulse width modulated signal 101.

[0035] In the specification and claims, if the edge of the first signal is at approximately the same time as the edge of the second signal, the edge of the signal is said to be "coincident" with the edge of the second signal. Therefore, if the first signal and the second signal appear at almost the same time, their rising edges are coincident.

[0036] When the isolation driver circuit 100 performs isolation, the power supply of the rising edge detection signal is capacitively isolated from the power supply of the input pulse width modulation signal 101. This also means that the power supply of the output pulse width modulation signal 102 is isolated from the power supply of the input pulse width modulation signal 101, thereby achieving the isolation function in the isolation driver circuit 100.

[0037] On the other hand, as shown by arrow line 121, the falling edge detection circuit 120 detects the falling edge of the input pulse width modulated signal 101. In response, as shown by arrow line 122, the falling edge detection circuit 120 outputs a corresponding falling edge detection signal to the decoder 130. This can be achieved by using a separate clock signal to modulate the inverted signal of the input pulse width modulated signal 101, wherein the separate clock signal has a rising edge that coincides with the falling edge of the input pulse width modulated signal 101 (and therefore coincides with the rising edge of the inverted signal of the input pulse width modulated signal 101). This is in contrast to the clock signal used by the rising edge detection circuit 110, which has a rising edge that coincides with the rising edge of the input pulse width modulated signal 101.

[0038] Again, when the isolation driver circuit 100 performs isolation, the power supply of the falling edge detection signal is capacitively isolated from the power supply of the input pulse width modulation signal 101. This also means that the power supply of the output pulse width modulation signal 102 is isolated from the power supply of the input pulse width modulation signal 101, thereby achieving the isolation function in the isolation driver circuit 100.

[0039] When the decoder 130 receives the rising edge detection signal from the rising edge detection circuit 110, the decoder 130 outputs the rising edge of the output pulse width modulated signal 102. Similarly, when the decoder 130 receives the falling edge detection signal from the falling edge detection circuit 120, the decoder 130 outputs the falling edge of the output pulse width modulated signal 102. Accordingly, the decoder 130 generates a rising edge in the output pulse width modulated signal 102 that is aligned in time with the rising edge of the input pulse width modulated signal 101, and generates a falling edge in the output pulse width modulated signal 102 that is aligned in time with the falling edge of the input pulse width modulated signal 101.

[0040] Since the rising and falling edges in the output PWM signal 102 are substantially aligned in time with the corresponding rising and falling edges in the input PWM signal 101, the pulse widths of the input PWM signal 101 are substantially preserved in the output PWM signal 102. Therefore, the information stored in these pulse widths can be transmitted with higher fidelity.

[0041] By way of example only, the output pulse width modulated signal may be used to drive one or more power transistors to accurately generate an amplified output pulse width modulated signal that is an amplified version of the input pulse width modulated signal. This may occur, for example, if the isolated driver circuit is included in a class D amplifier. In this case, since the pulse width is highly maintained, the analog input signal to the class D amplifier will be amplified with high fidelity in the class D amplifier.

[0042] Figure 2 An isolated driver circuit 200 is shown. Figure 1 The isolated driver circuit 200 includes a rising edge detection circuit 210 and a falling edge detection circuit 220, wherein the rising edge detection circuit and the falling edge detection circuit are respectively Figure 1 An example of a rising edge detection circuit 110 and a falling edge detection circuit 120 .

[0043] The rising edge detection circuit 210 includes a modulator 211, a demodulator 212, and capacitors 213 and 214. Similarly, the falling edge detection circuit 220 includes a modulator 221, a demodulator 222, and capacitors 223 and 224. The modulator 211 of the rising edge detection circuit 210 modulates the input pulse width modulation signal 101 using a clock signal from a clock 215, while the modulator 221 of the falling edge detection circuit 220 modulates the input pulse width modulation signal 101 using a different clock signal from a clock 225.

[0044] As previously mentioned, the isolation driver circuit (e.g. Figure 2 The isolated driver circuit 200 may use an isolation device (e.g., Figure 2 The capacitors 213, 214, 223 and 224 of FIG. 2 are used to isolate the low power of the input signal from the high power of the output signal. In order for the input signal to pass through, for example, the capacitors 213, 214, 223 and 224, the input signal is first converted into an AC signal of sufficiently high frequency to pass through the capacitors. This can be achieved using, for example, modulators 211 and 221.

[0045] For example, when the input signal is high, modulator 211 can use the clock signal from clock 215 to output an oscillating signal by modulating the input signal with the clock signal, and when the input signal is low, the modulator stops outputting the oscillating signal (because modulation without a signal still results in no signal). In contrast, when the input signal is low, modulator 221 can use the clock signal from clock 225 to output an oscillating signal by modulating the inverted signal of the input signal with the clock signal, and when the input signal is high, the modulator stops outputting the oscillating signal (because the inverted signal of the input signal is low).

[0046] Figure 3A signal diagram 300 is shown, which shows an input signal 301 before modulation, a first modulated signal 302 and a second modulated signal 303, and an output signal 304. The output signal 304 is decoded from the demodulated form of the first modulated signal 302 and the second modulated signal 303. The horizontal axis represents the time passed from left to right, where the same horizontal position in each of the four signals 301 to 304 represents the same time of the corresponding signal. For example, the time T1 to the time T7 is specially marked with a vertical dotted line extending through all of the four signals 301 to 304. The time is divided into three time periods 311, 312 and 313. Each time period includes a pulse period of pulse width information.

[0047] Signal 301 represents an input signal, which is Figure 1 and Figure 2 An example of an input pulse width modulated signal 101 is shown. Accordingly, recall that information is transmitted in the pulse width of each pulse period. In this example, the duty cycle of the input signal 301 in the first time period 311 is about 75%, the duty cycle of the input signal 301 in the second time period 312 is about 50%, and the duty cycle of the input signal 301 in the third time period 313 is about 25%.

[0048] Signal 302 represents a first modulated signal 302, which represents the use of Figure 2 The input signal 301 is modulated by the clock signal of the clock 215. Specifically, the clock signal coincides with the rising edge of the input signal 301. Accordingly, the first modulated signal 302 may also be referred to as a modulated rising edge signal 302. By detecting the rising edge of the first pulse in the pulse sequence of the modulated rising edge signal 302, the rising edge is detectable (for each time period). The rising edge of the pulse sequence will appear as a rising edge of the demodulated form of the modulated rising edge signal 302. The rising edge of the demodulated signal can therefore be a rising edge detection signal.

[0049] For example, the rising edge of the first pulse in the pulse sequence that appears in the first time period 311 appears at time T1. Correspondingly, the rising edge in the demodulated signal also appears substantially at time T1. In addition, the rising edge of the first pulse in the pulse sequence that appears in the second time period 312 (and therefore the rising edge of the demodulated signal) appears at time T3. Finally, the rising edge of the first pulse in the pulse sequence that appears in the third time period 313 (and therefore the rising edge of the demodulated signal) appears at time T5.

[0050] Signal 303 represents a second modulated signal 303, which represents the use of Figure 2The clock signal of the clock 225 modulates the inverted form of the input signal 301. Specifically, the clock signal coincides with the falling edge of the input signal 301. Accordingly, the second modulated signal 303 may also be referred to as a modulated falling edge signal 303. The falling edge is detectable (for each time period) by detecting the rising edge of the first pulse in the pulse sequence of the modulated falling edge signal 303. For example, the rising edge of the first pulse in the pulse sequence (of the modulated falling edge signal 303) that appears in the first time period 311 (and therefore the rising edge of the demodulated signal) appears at time T2. The rising edge of the first pulse in the pulse sequence (of the modulated falling edge signal 303) that appears in the second time period 312 (and therefore the rising edge of the demodulated signal) appears at time T4. Finally, the rising edge of the first pulse in the pulse sequence (of the modulated falling edge signal 303) that appears in the third time period 313 (and therefore the rising edge of the demodulated signal) appears at time T6.

[0051] Signal 304 represents an output signal output by decoder 130 when receiving a rising edge detection signal from demodulator 212 and a falling edge detection signal from demodulator 222. The output signal is Figure 1 and Figure 2 1. An example of an output pulse width modulation signal 102. For example, rising edges are detected as occurring at times T1, T3, and T5, and falling edges are detected as occurring at times T2, T4, and T6.

[0052] This description will now be described in detail in Figure 3 The situation that occurs at each time T1 to T7 in the example of . At time T1, in the first time period 311, the input signal 301 has a rising edge 301A in which the input signal 301 switches from a low voltage (e.g., 0 volts) to a high voltage (e.g., 5 volts). In response to this transition, in order to ensure consistency with the rising edge 301A, the clock 215 starts by generating a clock signal (not shown) having a rising edge soon after the rising edge 301A of the input signal 301. In addition, because the modulator 211 is driven by the clock 215 to modulate the input signal 301 to generate the modulated rising edge signal 302, the modulated rising edge signal 302 also has a rising edge 302A that occurs soon after the rising edge 301A of the input signal 301. In fact, this response is so fast that the rising edge 302A of the modulated rising edge signal 302 occurs at 500 Hz. Figure 3 It appears that the rising edge 301A of the input signal 301 occurs at substantially the same time (at time T1).

[0053] Brief reference Figure 2, the demodulator 212 receives the modulated rising edge signal 302 via the capacitor 213. The demodulator 212 demodulates the modulated rising edge signal 302 and will therefore output a transition high in response to receiving the first rising edge 302A in the pulse train in the modulated rising edge signal 302 that occurs in the first time period 311. This rising edge detection signal may simply be the rising edge of the demodulated signal output by the demodulator 212. In response thereto, the decoder 130 generates a rising edge 304A in the output signal 304. Again, this occurs so quickly that in Figure 3 , rising edge 304A is shown as occurring at substantially the same time T1 as rising edge 302A of modulated rising edge signal 302 and rising edge 301A of input signal 301 .

[0054] Between time T1 and T2, input signal 301 remains at a high voltage. Accordingly, modulator 211 continues to generate pulses in modulated rising edge signal 302. Figure 3 , there are four pulses in the modulated rising edge signal 302 that occurs in the time period 311. Note that there are no pulses in the modulated falling edge signal 301 between times T1 and T2 because the modulated falling edge signal 303 is modulated using the inverted signal of the input signal 301. And since the input signal 301 is high between times T1 and T2, the inverted signal of the input signal 301 is low between times T1 and T2.

[0055] At time T2 in the first time period 311, the input signal 301 has a falling edge 301B in which the input signal 301 switches from a high voltage to a low voltage. In response to this transition, in order to ensure consistency with the falling edge 301B, the clock 225 starts by generating a clock signal with a rising edge soon after the falling edge 301B of the input signal 301. In addition, because the modulator 221 is driven by the clock 225 to modulate the input signal 301 to generate the modulated falling edge signal 303, the modulated falling edge signal 303 also has a rising edge 303A that appears soon after the falling edge 301B of the input signal 301. Again, this response is so fast that the rising edge 303A of the modulated falling edge signal 303 occurs at 303A. Figure 3 It appears that the falling edge 301B of the input signal 301 occurs at substantially the same time (at time T2).

[0056] Reference again Figure 2, the demodulator 222 receives the modulated falling edge signal 303 via the capacitor 223. The demodulator 222 demodulates the modulated falling edge signal 303 and will therefore output a transition high in response to receiving the first rising edge 303A in the pulse sequence in the modulated falling edge signal 303 that occurs in the first time period 311. The falling edge detection signal may simply be the rising edge of the demodulated signal output by the demodulator 222. In response thereto, the decoder 130 generates a falling edge 304B in the output signal 304. Again, this occurs so quickly that in Figure 3 , the falling edge 304B is shown as occurring at substantially the same time T2 as the rising edge 303A of the modulated falling edge signal 303 and the falling edge 301B of the input signal 301 .

[0057] Between time T2 and T3, the input signal 301 remains at a low voltage. Accordingly, the modulator 221 continues to generate pulses in the modulated falling edge signal 303. Figure 3 , there are two pulses that appear at least partially in the modulated falling edge signal 303 during the time period 311. Note that the modulator 211 has stopped generating pulses in the modulated rising edge signal 302 between times T2 and T3 because the modulated rising edge signal 302 is modulated using the input signal 301 instead of the inverse signal of the input signal 301.

[0058] Based on the rising edges (e.g., rising edges 301C, 301E, and 301G) and falling edges (e.g., falling edges 301D and 301F) in the input signal 301, the process of generating the rising edges (e.g., rising edges 304C, 304E, and 304G) and falling edges (e.g., falling edges 304D and 304F) in the output signal 304 via the corresponding modulated rising edge detection signal 302 and the modulated falling edge detection signal 303 is repeated in the remaining time periods 312 and 313. That is, based on the rising edge of the first pulse in the pulse sequence of the modulated rising edge signal 302 in the second time period 312 occurring at time T3, the rising edge 304C is generated at time T3. Thereafter, based on the rising edge of the first pulse in the pulse sequence of the modulated falling edge signal 303 in the second time period 312 occurring at time T4, the falling edge 304D is generated at time T4. Subsequently, a rising edge 304E is generated at time T5 based on the rising edge of the first pulse in the pulse train of the modulated rising edge signal 302 in the third time period 313 occurring at time T5. Thereafter, a falling edge 304F is generated at time T6 based on the rising edge of the first pulse in the pulse train of the modulated falling edge signal 303 in the third time period 313 occurring at time T6. This may continue indefinitely, as represented by edge 301G of the input signal 301 and edge 304G of the output signal 304.

[0059] During the transmission of the modulated rising edge signal 302 via capacitor 213 and the transmission of the modulated falling edge signal 303 via capacitor 223, the corresponding common-mode signal may be transmitted through capacitors 214 and 224. As an example, when the modulated rising edge signal 302 is transmitted through capacitor 213, the common-mode signal transmitted through capacitor 214 may be an inverted form of the modulated rising edge signal 302. Similarly, when the modulated falling edge signal 303 is transmitted through capacitor 223, the common-mode signal transmitted through capacitor 224 may be an inverted form of the modulated falling edge signal 303. Accordingly, the signals transmitted via capacitors 213 and 214 may together represent a pair of differential signals. In addition, the signals transmitted via capacitors 223 and 224 may together represent a pair of differential signals. The demodulators 212 and 222 may use these common mode signals to cancel unwanted noise that may appear in the corresponding modulated rising edge signal 302 and the modulated falling edge signal 303 , and thus the demodulators 212 and 222 may generate the corresponding rising edge detection signal and the falling edge detection signal more accurately.

[0060] Further, there will always be some delay between the time an edge is detected in the input signal 301 and the time a corresponding edge is generated in the output signal 304. However, because the isolated driver circuit 100 is a solid-state device, this delay is negligible compared to the pulse period. However, even if the delay is large, the pulse width in the output signal 304 will still closely match the pulse width in the input signal 301 as long as the delay is relatively constant from edge to edge. Therefore, even if there is a delay, the information will be preserved as long as the delay is relatively constant.

[0061] In addition, for any given time period, only the rising edge of the first pulse in the corresponding pulse sequence of the modulated rising edge signal 302 is actually used to detect the rising edge of the input signal 301 for that pulse period (because this is the rising edge that causes the rising edge in the demodulated signal). Similarly, only the rising edge of the first pulse in the corresponding pulse sequence of the modulated falling edge signal 303 is actually used to detect the falling edge of the input signal 301 for that pulse period (because this is the rising edge that causes the rising edge in the demodulated signal). The remaining pulses of the modulated rising edge signal 302 and the modulated falling edge signal 303 for that time period are redundant. However, for a specific implementation, it is much more difficult to generate only a single pulse than to simply let the modulation continue to the next edge. Accordingly, it is harmless to generate these redundant pulses. Additionally, the pulse width between the rising edge and the falling edge of the input signal 301 is substantially maintained in the pulse width between the rising edge and the falling edge of the output signal 303, regardless of the frequency of the clock signal provided by the clocks 215 and 225.

[0062] According to the principle described herein, an output signal is obtained by using two different modulation signals, that is, one modulation signal (modulated rising edge signal) is used to detect the rising edge of the input signal, and the other modulation signal (modulated falling edge signal) is used to detect the falling edge of the input signal. In addition, by making the modulated clock of the rising edge signal of the driving modulation consistent with the rising edge of the input signal, and by making the modulation of the other clock of the falling edge signal of the driving modulation consistent with the falling edge of the input signal, the high-precision time alignment of the edge is achieved. Therefore, the demodulated form of the modulated rising edge signal will have a rising edge aligned with the rising edge of the input pulse width modulation signal, and is therefore regarded as a rising edge detection signal. In addition, the demodulated form of the modulated falling edge signal will have a rising edge aligned with the falling edge of the input pulse width modulation signal, and is therefore regarded as a falling edge detection signal. By considering the corresponding rising edge as a detection signal, the pulse width is retained to a greater extent than by using a single clock signal and a single modulation signal, where the clock is inconsistent with the input signal. The reason for doing this will become clear from the following description of Figure 4.

[0063] FIG. 4 shows a signal diagram 400, which illustrates an example of signals involved in modulating an input signal to generate an output signal according to the prior art, wherein only one clock signal and one modulator are used. Four signals 401, 402, 403, and 404 are shown. The horizontal axis represents the time elapsed from left to right, wherein the same horizontal position in each of the four signals 401 to 404 represents the same moment of the corresponding signal. For example, the moment T1 to the moment T7 is specifically marked. The time is divided into three time periods 411, 412, and 413.

[0064] Signal 401 represents an input signal, which for comparison purposes is similar to Figure 3 402 represents a clock signal that is inconsistent with the input signal 401, although sometimes the edges of the signals 401 and 402 do align accidentally. Signal 403 represents a modulated signal in which the input signal is modulated with the clock signal 402. Signal 404 represents an output signal that has been demodulated from the modulated signal 403. Generally, a time period in which the modulated signal 403 has a pulse is demodulated to a high state in the output signal 404, while a time period without such a pulse is demodulated to a low state in the output signal 404.

[0065] By using only one modulator that uses only one clock signal, the rising and falling edges of the clock signal may not be aligned in time with the rising and falling edges of the input signal. For example, in this particular example, the edges 401A, 401B, and 401F of the input signal 401 are aligned with the corresponding edges 404A, 404B, and 404F of the output signal 404. However, the edges 404C, 404D, and 404E are not well aligned with the corresponding edges 401C, 401D, and 401E. Therefore, compared with the input signal 401, the output signal 404 demodulated from the modulation signal 403 has an inconsistency in pulse width. This results in information loss and jitter.

[0066] For example, in the first time period 411, by chance, the rising edge 401A and the falling edge 401B of the input signal 401 are aligned with the rising edge 404A and the falling edge 404B of the output signal 404. However, this is only due to a lucky situation, where the rising edge 401A of the input signal 401 happens to be aligned with the rising edge of the clock signal 402, and the falling edge 401B of the input signal 401 happens to be aligned with the falling edge of the clock signal 402. When the clock signal 402 and the input signal 401 are inconsistent, this luck cannot continue.

[0067] For example, at time T3, the clock signal 402 is already high and therefore does not have a rising edge that is substantially aligned with the rising edge 401C of the input signal 401. Accordingly, the modulated signal 403 may have a very narrow pulse 403A that may not be properly detected by the demodulator, and therefore the demodulator may not output a rising edge 404C in the output signal 404 until the next rising edge of the clock signal 402. In addition, the last pulse in the second time period 412 within the modulated signal 403 occurs before time T4, and therefore, the demodulated pulse of the second time period 412 has a falling edge 404D that occurs before time T4.

[0068] Likewise, at time T5, clock signal 402 is low and therefore does not have a rising edge that is substantially aligned with rising edge 401E of input signal 401. Therefore, modulated signal 403 may not begin generating pulses until the next rising edge of clock signal 402, and the demodulator may not output rising edge 404E in output signal 404 until the next rising edge of clock signal 402. However, again, fortunately, falling edge 401F of input signal 401 is aligned with the falling edge of clock signal 402, and therefore falling edge 404F of output signal 404 is aligned with falling edge 401F of input signal 401.

[0069] Figure 4 shows that when modulated with a single clock signal that is inconsistent with the input signal, there is an error between the pulse widths of the output PWM signal compared to the input PWM signal. A higher frequency clock (shorter period between clock pulses) can reduce the error. However, the error in pulse width still exists, but on the order of the period of the clock signal. According to the principles described in this article, the pulse width accuracy is more precise and does not depend on the frequency of the clock signal.

[0070] Return to reference Figure 2 and Figure 3 , recall that, to ensure consistency with the rising edge 301A of the input signal 301, the clock 215 starts by generating a clock signal having a rising edge soon after the rising edge 301A of the input signal 301. Similarly, to ensure consistency with the falling edge 301B of the input signal 301, the clock 225 starts by generating a clock signal having a rising edge soon after the falling edge 301B of the input signal 301. In order to start generating such a clock signal soon after the rising edge 301A or the falling edge 301B of the input signal, a fast start clock may be used, such as Figure 5 shown.

[0071] Figure 5 A fast start clock 500 is shown, which is Figure 2 The fast start clock 500 includes an auxiliary oscillator 510 and a main oscillator 520. Assuming that power is supplied to the fast start clock 500, the auxiliary oscillator 510 is a low power oscillator that is kept on. On the other hand, the main oscillator 520 is a low power oscillator that supplies power to a modulator (e.g., Figure 2 The modulator 211 or 221) provides a high power oscillator of the actual clock signal. Figure 2 In the case where the clock 215 is working, only when the input pulse width modulation signal (for example, Figure 1 and Figure 2 The input pulse width modulation signal 101, or Figure 3 The main oscillator 520 is turned on only when the input signal 301 of the clock source is high. Of course, if the fast start clock 500 is used as Figure 2 If the clock 225 is working, the main oscillator 520 will instead be turned on only when the inverted signal of the input pulse width modulated signal is high, and therefore turned on when the input pulse width modulated signal is low.

[0072] A high power oscillator (such as the main oscillator 520) itself may require significant startup time whenever the input pulse width modulated signal goes high (or when the inverted signal of the input pulse width modulated signal goes high). Such a significant startup time may cause a significant delay between the edge of the input pulse width modulated signal and the initial rising edge of the clock signal, and thus may not ensure the consistency between the rising edge or falling edge of the input signal and the rising edge of the clock signal. Accordingly, when the input pulse width modulated signal (or the inverted signal of the input pulse width modulated signal) goes high, the fast start clock 500 quickly starts the main oscillator 520 using the auxiliary oscillator 510 that is already running, thereby overcoming this significant startup delay. Therefore, the fast start clock 500 is able to provide a clock signal with an initial rising edge that is substantially consistent with the rising edge (or falling edge) of the input pulse width modulated signal.

[0073] Before discussing the operation of the fast start clock 500, some additional structures of the fast start clock 500 will now be described. The fast start clock 500 also includes transistors 530, 540 and 550 and a current source 560, which together act as a current mirror. As an example, transistors 530 and 540 can have substantially the same gate width, while transistor 550 can have a gate width that is N times greater than the gate width of transistors 530 and 540 (where N is much greater than 1). Accordingly, transistors 530 and 540 can have an internal resistance that is N times greater than the internal resistance of transistor 550.

[0074] The auxiliary oscillator 510 includes a local power supply node 511, a ground node 512, intermediate nodes 513 to 516, p-type transistors 517A to 517C, and n-type transistors 518A to 518C. Similarly, the main oscillator 520 includes a local power supply node 521, a ground node 522, intermediate nodes 523 to 526, p-type transistors 527A to 527C, and n-type transistors 528A to 528C. The local power supply node 511 of the auxiliary oscillator 510 and the local power supply node 521 of the main oscillator 520 are coupled together via an operational amplifier 560 and a switch 570.

[0075] Each of transistors 530, 540, and 550 may be a p-type transistor having a source node, each source node being connected to a voltage source 580 providing a source voltage. A drain node of transistor 540 is connected to a local power supply node 511 of the auxiliary oscillator 510. Accordingly, the local power supply node 511 receives charge from the voltage source 580 via transistor 540 and provides an auxiliary local power supply voltage thereon, which is a portion of the source voltage from the voltage source 580. Similarly, a drain node of transistor 550 is connected to a local power supply node 521 of the main oscillator 520. Accordingly, the local power supply node 511 receives charge from the voltage source 580 via transistor 550 and provides a main local power supply voltage thereon, which is a portion of the source voltage from the voltage source 580. Further, when switch 570 is closed and switches 529A and 529B are open, operational amplifier 560 may allow a primary local supply voltage present on local supply node 521 of primary oscillator 520 to approach an auxiliary local supply voltage present on local voltage supply node 511 of auxiliary oscillator 510 .

[0076] In operation, with respect to the auxiliary oscillator 510, when power is provided, the transistors 517A to 517C and 518A to 518C alternate between being turned on and off. More specifically, when the intermediate node 513 is provided with a high voltage, the intermediate node 514 is low, the intermediate node 515 is high, and the intermediate node 516 is low. Therefore, applying a high voltage to the node 513 will (with some delay) result in applying a low voltage to the node 513. On the other hand, when the intermediate node 513 is low, the intermediate node 514 is high, the intermediate node 515 is low, and the intermediate node 516 is high. Therefore, the delay of propagating the alternating state through the transistors results in the generation of a clock signal at the node 516 (where the frequency is inversely proportional to the delay).

[0077] The master oscillator 520 operates in a similar manner. However, if the master oscillator 520 is used as Figure 2If the clock 215 is turned on, then when a rising edge in the input pulse width modulated signal 101 is detected, switch 529A will be closed (and switches 570 and 529B will be opened). Capacitor 590 is also charged to a suitable high voltage, and therefore the intermediate node 523 is already high, resulting in the immediate generation of a clock signal high. Therefore, when the input pulse width modulated signal 101 transitions to high, the clock 215 quickly generates a rising edge in the clock signal. On the other hand, when the input pulse width modulated signal goes low, switch 570 causes capacitor 590 to recharge, so that power is immediately available when the next transition of the input pulse width modulated signal is high. In addition, switch 529B is closed to force a high voltage to be applied at node 523, and thereby force a low clock value to be applied at node 526. Therefore, when the input pulse width modulated signal 101 is low, the clock 215 does not work.

[0078] The master oscillator 520 can also be used as Figure 5 The operation will be the same except that switch 529A will be closed and switches 570 and 529B will be opened at the falling edge of the input pulse width modulated signal. In addition, at the rising edge of the input pulse width modulated signal, switch 529A will be opened and switches 570 and 529B will be closed.

[0079] Figure 6 An isolated driver circuit 600 is shown according to the principles described herein. The isolated driver circuit comprises Figure 2 200A and 200B of the isolated driver circuit 200. Further, the isolated driver circuit 600 includes a buffer 610, an inverter 620, a dead time circuit 630, drivers 640 and 650, and transistors 660 and 670. One instance of the isolated driver circuit 200 is labeled as isolated driver circuit 200A, and the other instance of the isolated driver circuit 200 is labeled as isolated driver circuit 200B. Figure 6 The components of the isolated driver circuit 200A are labeled with Figure 2 The components of the isolated driver circuit 200 are the same, but with the addition of the suffix "A". In addition, Figure 6 The components of the isolated driver circuit 200B are Figure 2 The components of the secondary side circuit 200 are labeled the same, but with the suffix "B" added.

[0080] Buffer 610 generates an input pulse width modulated signal 602 which is a buffered version of input pulse width modulated signal 601. Dead time circuit 630 and inverter 620 work together so that inverter 620 generates a complementary input pulse width modulated signal 603 that is complementary to input pulse width modulated signal 602 but has some dead time so that input pulse width modulated signal 602 and complementary input pulse width modulated signal 603 are not high at the same time. Isolation driver circuit 200A operates on input pulse width modulated signal 602 in the same manner as isolation driver circuit 20 described above operates on input pulse width modulated signal 101. Likewise, isolation driver circuit 200B operates on complementary input pulse width modulated signal 603 in the same manner as isolation driver circuit 200A described above operates on input pulse width modulated signal 101.

[0081] In addition, the output pulse width modulated signal 604 is provided to the driver 640, which responds by driving the gate terminal of the field effect transistor 660. Similarly, the complementary output pulse width modulated signal 605 is provided to the driver 650, which responds by driving the gate terminal of the field effect transistor 670. Due to the dead time introduced by the dead time circuit 60, the drive signals from the drivers 640 and 650 will not turn on the transistor 660 at the same time, thereby avoiding the high current from the high voltage power supply +Vcc to the low voltage power supply -Vcc. The resulting output signal 606 is an amplified high power pulse width modulated signal, which is an amplified version of the input pulse width modulated signal 601.

[0082] Figure 7 An isolated driver circuit 700 is shown. Figure 2 However, instead of using capacitors 214 and 224 to generate a single combined common-mode signal, the isolated driver circuit 700 uses a common-mode transmitter 710 to generate a single combined common-mode signal. Figure 2 The combined common-mode signal is then transmitted from the common-mode transmitter 710 to the common-mode receiver 720 via the common-mode capacitor 730. The demodulators 212 and 222 can then use the combined common-mode signal to eliminate the rising edge signals (e.g., Figure 3 The modulated rising edge signal 302 in the example and the modulated falling edge signal (eg, Figure 3 Accordingly, demodulators 212 and 222 can more accurately generate corresponding rising edge detection signals and falling edge detection signals, ie, a single combined common mode signal, rather than separate common mode signals.

[0083] Accordingly, in accordance with the principles described herein, an isolated driver circuit allows information represented by the pulse width of an input pulse width modulated signal to be retained with high fidelity in an output pulse width modulated signal by using multiple clock signals to track rising and falling edges in the input pulse width modulated signal, and further by generating rising and falling edges in the output pulse width modulated signal that are substantially aligned in time with corresponding rising and falling edges in the output pulse width modulated signal, in accordance with the principles described herein.

[0084] Text support part

[0085] Item 1: An isolation driver circuit for a pulse width modulated signal, the isolation driver circuit comprising: a rising edge detection circuit, configured to detect a rising edge of an input pulse width modulated signal and output a corresponding rising edge detection signal so as to be capacitively isolated from the input pulse width modulated signal; a falling edge detection circuit, configured to detect a falling edge of the input pulse width modulated signal and output a corresponding falling edge detection signal so as to be capacitively isolated from the input pulse width modulated signal; and a decoder, configured to generate an output pulse width modulated signal by generating a rising edge of the output pulse width modulated signal corresponding in time to the detected rising edge of the input pulse width modulated signal, and by generating a falling edge of the output pulse width modulated signal corresponding in time to the detected falling edge of the input pulse width modulated signal.

[0086] Item 2: According to the isolation driver circuit described in Item 1, the rising edge detection circuit includes: a clock, configured to coincide with the rising edge of the input pulse width modulated signal; a modulator, configured to receive the input pulse width modulated signal and modulate the input pulse width modulated signal using a clock signal from the clock to generate a modulated pulse width modulated signal; a capacitor; and a demodulator, configured to receive the modulated pulse width modulated signal via the capacitor and configured to demodulate the modulated pulse width modulated signal to generate a demodulated pulse width modulated signal, the rising edge of the demodulated pulse width modulated signal being one of the corresponding rising edge detection signals.

[0087] Item 3: According to the isolation driver circuit described in Item 2, the clock is a first clock, the modulator is a first modulator, the modulated pulse width modulated signal is a first modulated pulse width modulated signal, the capacitor is a first capacitor, the demodulator is a first demodulator, the demodulated pulse width modulated signal is a first demodulated pulse width modulated signal, and the falling edge detection circuit includes: a second clock, configured to coincide with the falling edge of the input pulse width modulated signal; a second modulator, configured to receive the input pulse width modulated signal and modulate the input pulse width modulated signal using a clock signal from the second clock to generate a second modulated pulse width modulated signal, the second modulated pulse width modulated signal being a modulation of an inverted signal of the input pulse width modulated signal; a second capacitor; and a second demodulator, configured to receive the second modulated pulse width modulated signal via the second capacitor and configured to demodulate the second modulated pulse width modulated signal to generate a second demodulated pulse width modulated signal, the rising edge of the second demodulated pulse width modulated signal being one of the corresponding falling edge detection signals.

[0088] Item 4: According to the isolation driver circuit described in Item 3, the rising edge detection circuit is a first rising edge detection circuit, the falling edge detection circuit is a first falling edge detection circuit, the decoder is a first decoder, and the isolation driver circuit further includes: a dead time circuit configured to generate a complementary input pulse width modulation signal that is complementary to the input pulse width modulation signal but has some dead time, so that the input pulse width modulation signal and the complementary input pulse width modulation signal are not high at the same time; a second rising edge detection circuit configured to detect the rising edge of the complementary input pulse width modulation signal and output a corresponding complementary rising edge detection signal so as to be high with the complementary input pulse width modulation signal; a second falling edge detection circuit, the second falling edge detection circuit being configured to detect the falling edge of the complementary input pulse width modulation signal and output a corresponding complementary falling edge detection signal so as to be capacitively isolated from the complementary input pulse width modulation signal; and a second decoder being configured to generate the complementary output pulse width modulation signal by generating a rising edge of the complementary output pulse width modulation signal corresponding in time to the detected rising edge of the complementary input pulse width modulation signal, and by generating a falling edge of the complementary output pulse width modulation signal corresponding in time to the detected falling edge of the complementary input pulse width modulation signal.

[0089] Item 5: According to the isolation driver circuit described in Item 4, the second rising edge detection circuit includes: a third clock, configured to coincide with the rising edge of the complementary input pulse width modulated signal; a third modulator, configured to receive the complementary input pulse width modulated signal and modulate the complementary input pulse width modulated signal using a clock signal from the third clock to generate a third modulated pulse width modulated signal; a third capacitor; and a third demodulator, configured to receive the third modulated pulse width modulated signal via the third capacitor and configured to demodulate the third modulated pulse width modulated signal to generate a third demodulated pulse width modulated signal, the rising edge of the third demodulated pulse width modulated signal being one of the corresponding complementary rising edge detection signals.

[0090] Item 6: According to the isolation driver circuit described in Item 5, the second falling edge detection circuit includes: a fourth clock, configured to coincide with the falling edge of the complementary input pulse width modulated signal; a fourth modulator, configured to receive the complementary input pulse width modulated signal and modulate the complementary input pulse width modulated signal using a clock signal from the fourth clock to generate a fourth modulated pulse width modulated signal; a fourth capacitor; and a fourth demodulator, configured to receive the fourth modulated pulse width modulated signal via the fourth capacitor and configured to demodulate the fourth modulated pulse width modulated signal to generate a fourth demodulated pulse width modulated signal, the fourth demodulated pulse width modulated signal being a modulation of an inverted signal of the complementary input pulse width modulated signal, the rising edge of the fourth demodulated pulse width modulated signal being one of the corresponding complementary falling edge detection signals.

[0091] Item 7: The isolation driver circuit according to Item 6, further comprising: a first driver configured to output a high drive signal to the gate terminal of the first field effect transistor when the first decoder generates a rising edge of the output pulse width modulated signal, and configured to output a low drive signal to the gate terminal of the first field effect transistor when the first decoder generates a falling edge of the output pulse width modulated signal; and a second driver configured to output a high drive signal to the gate terminal of the second field effect transistor when the second decoder generates a rising edge of the complementary output pulse width modulated signal, and configured to output a low drive signal to the gate terminal of the second field effect transistor when the second decoder generates a falling edge of the complementary output pulse width modulated signal.

[0092] Item 8: The isolation driver circuit of Item 3, further comprising a driver configured to output a high drive signal to a gate terminal of a field effect transistor when the decoder generates a rising edge of the output pulse width modulated signal, and configured to output a low drive signal to the gate terminal of the field effect transistor when the decoder generates a falling edge of the output pulse width modulated signal.

[0093] Item 9: According to the isolation driver circuit described in Item 3, the isolation driver circuit also includes a third capacitor, the first modulator is further configured to generate a common-mode signal corresponding to the first modulated pulse-width modulation signal, the first demodulator is further configured to receive the common-mode signal via the third capacitor, and is configured to use the common-mode signal to generate the first demodulated pulse-width modulation signal.

[0094] Item 10: According to the isolation driver circuit described in Item 9, the common-mode signal is a first common-mode signal, the isolation driver circuit also includes a fourth capacitor, the second modulator is further configured to generate a second common-mode signal corresponding to the second modulated pulse-width modulated signal, and the second demodulator is further configured to receive the second common-mode signal via the fourth capacitor, and is configured to generate the second demodulated pulse-width modulated signal using the second common-mode signal.

[0095] Item 11: The isolation driver circuit of Item 1, further comprising: a dead time circuit configured to generate a complementary input pulse width modulated signal that is complementary to the input pulse width modulated signal but has some dead time, so that the input pulse width modulated signal and the complementary input pulse width modulated signal are not high at the same time.

[0096] Item 12: According to the isolation driver circuit described in Item 11, the rising edge detection circuit is a first rising edge detection circuit, the falling edge detection circuit is a first falling edge detection circuit, the decoder is a first decoder, and the isolation driver circuit also includes: a second rising edge detection circuit, configured to detect the rising edge of the complementary input pulse width modulated signal and output a corresponding complementary rising edge detection signal so as to be capacitively isolated from the complementary input pulse width modulated signal; a second falling edge detection circuit, configured to detect the falling edge of the complementary input pulse width modulated signal and output a corresponding complementary falling edge detection signal so as to be capacitively isolated from the complementary input pulse width modulated signal; and a second decoder, configured to generate the complementary output pulse width modulated signal by generating a rising edge of the complementary output pulse width modulated signal corresponding in time to the detected rising edge of the complementary input pulse width modulated signal, and by generating a falling edge of the complementary output pulse width modulated signal corresponding in time to the detected falling edge of the complementary input pulse width modulated signal.

[0097] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the above-described features or acts, or the order of the above-described acts. Instead, the described features and acts are disclosed as example forms of implementing the claims.

[0098] The present disclosure may be implemented in other specific forms without departing from its essential features. The described embodiments are considered in all respects to be illustrative and not restrictive. All changes within the meaning and scope of the equivalent scheme of the claims are included within the scope of the claims.

[0099] When introducing elements in the appended claims, the articles “a,” “an,” “the,” and “said” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Claims

1. An isolation driver circuit for a pulse width modulated signal, the isolation driver circuit comprising: a rising edge detection circuit configured to detect a rising edge of an input pulse width modulation signal and output a corresponding rising edge detection signal so as to be capacitively isolated from the input pulse width modulation signal; a falling edge detection circuit configured to detect a falling edge of the input pulse width modulation signal and output a corresponding falling edge detection signal so as to be capacitively isolated from the input pulse width modulation signal; as well as A decoder is configured to generate the output pulse width modulated signal by generating a rising edge of the output pulse width modulated signal corresponding in time to a detected rising edge of the input pulse width modulated signal, and by generating a falling edge of the output pulse width modulated signal corresponding in time to a detected falling edge of the input pulse width modulated signal.

2. The isolated driver circuit according to claim 1, wherein the rising edge detection circuit comprises: a clock configured to coincide with a rising edge of the input pulse width modulation signal; a modulator configured to receive the input pulse width modulated signal and modulate the input pulse width modulated signal using a clock signal from the clock to generate a modulated pulse width modulated signal; Capacitors; as well as A demodulator is configured to receive the modulated pulse width modulation signal via the capacitor and to demodulate the modulated pulse width modulation signal to generate a demodulated pulse width modulation signal, wherein a rising edge of the demodulated pulse width modulation signal is one of the corresponding rising edge detection signals.

3. The isolated driver circuit according to claim 2, wherein the clock is a first clock, the modulator is a first modulator, the modulated pulse width modulation signal is a first modulated pulse width modulation signal, the capacitor is a first capacitor, the demodulator is a first demodulator, the demodulated pulse width modulation signal is a first demodulated pulse width modulation signal, and the falling edge detection circuit comprises: a second clock configured to coincide with a falling edge of the input pulse width modulation signal; a second modulator configured to receive the input pulse width modulation signal and modulate the input pulse width modulation signal using a clock signal from the second clock, thereby generating a second modulated pulse width modulation signal, the second modulated pulse width modulation signal being a modulation of an inverted signal of the input pulse width modulation signal; a second capacitor; as well as A second demodulator is configured to receive the second modulated pulse width modulation signal via the second capacitor, and is configured to demodulate the second modulated pulse width modulation signal to generate a second demodulated pulse width modulation signal, wherein the rising edge of the second demodulated pulse width modulation signal is one of the corresponding falling edge detection signals.

4. The isolated driver circuit according to claim 3, wherein the rising edge detection circuit is a first rising edge detection circuit, the falling edge detection circuit is a first falling edge detection circuit, the decoder is a first decoder, and the isolated driver circuit further comprises: a dead time circuit configured to generate a complementary input pulse width modulated signal that is complementary to the input pulse width modulated signal but has some dead time so that the input pulse width modulated signal and the complementary input pulse width modulated signal are not high at the same time; a second rising edge detection circuit configured to detect a rising edge of the complementary input pulse width modulation signal and output a corresponding complementary rising edge detection signal so as to be capacitively isolated from the complementary input pulse width modulation signal; a second falling edge detection circuit configured to detect a falling edge of the complementary input pulse width modulation signal and output a corresponding complementary falling edge detection signal so as to be capacitively isolated from the complementary input pulse width modulation signal; as well as A second decoder is configured to generate the complementary output pulse width modulated signal by generating a rising edge of the complementary output pulse width modulated signal corresponding in time to a detected rising edge of the complementary input pulse width modulated signal, and by generating a falling edge of the complementary output pulse width modulated signal corresponding in time to a detected falling edge of the complementary input pulse width modulated signal.

5. The isolated driver circuit according to claim 4, wherein the second rising edge detection circuit comprises: a third clock configured to coincide with a rising edge of the complementary input pulse width modulation signal; a third modulator configured to receive the complementary input pulse width modulated signal and modulate the complementary input pulse width modulated signal using a clock signal from the third clock to generate a third modulated pulse width modulated signal; A third capacitor; as well as A third demodulator is configured to receive the third modulated pulse width modulation signal via the third capacitor, and is configured to demodulate the third modulated pulse width modulation signal to generate a third demodulated pulse width modulation signal, and the rising edge of the third demodulated pulse width modulation signal is one of the corresponding complementary rising edge detection signals.

6. The isolated driver circuit according to claim 5, wherein the second falling edge detection circuit comprises: a fourth clock configured to coincide with a falling edge of the complementary input pulse width modulation signal; a fourth modulator configured to receive the complementary input pulse width modulated signal and modulate the complementary input pulse width modulated signal using a clock signal from the fourth clock to generate a fourth modulated pulse width modulated signal; a fourth capacitor; as well as A fourth demodulator is configured to receive the fourth modulated pulse width modulation signal via the fourth capacitor, and is configured to demodulate the fourth modulated pulse width modulation signal to generate a fourth demodulated pulse width modulation signal, wherein the fourth demodulated pulse width modulation signal is a modulation of the inverted signal of the complementary input pulse width modulation signal, and the rising edge of the fourth demodulated pulse width modulation signal is one of the corresponding complementary falling edge detection signals.

7. The isolated driver circuit according to claim 6, further comprising: a first driver configured to output a high drive signal to a gate terminal of a first field effect transistor when the first decoder generates a rising edge of the output pulse width modulated signal, and configured to output a low drive signal to the gate terminal of the first field effect transistor when the first decoder generates a falling edge of the output pulse width modulated signal; as well as a second driver configured to output a high drive signal to a gate terminal of a second field effect transistor when the second decoder generates a rising edge of the complementary output pulse width modulated signal, and configured to output a low drive signal to the gate terminal of the second field effect transistor when the second decoder generates a falling edge of the complementary output pulse width modulated signal.

8. The isolation driver circuit of claim 3 , further comprising a driver configured to output a high drive signal to a gate terminal of a field effect transistor when the decoder generates a rising edge of the output pulse width modulated signal, and configured to output a low drive signal to the gate terminal of the field effect transistor when the decoder generates a falling edge of the output pulse width modulated signal.

9. The isolation driver circuit of claim 3, further comprising a third capacitor, the first modulator further configured to generate a common-mode signal corresponding to the first modulated pulse-width modulation signal, the first demodulator further configured to receive the common-mode signal via the third capacitor, and configured to generate the first demodulated pulse-width modulation signal using the common-mode signal.

10. The isolation driver circuit of claim 9, wherein the common-mode signal is a first common-mode signal, the isolation driver circuit further comprising a fourth capacitor, the second modulator further configured to generate a second common-mode signal corresponding to the second modulated pulse-width modulation signal, the second demodulator further configured to receive the second common-mode signal via the fourth capacitor, and configured to generate the second demodulated pulse-width modulation signal using the second common-mode signal.

11. The isolated driver circuit of claim 1 , further comprising: A dead time circuit is configured to generate a complementary input pulse width modulated signal that is complementary to the input pulse width modulated signal but has some dead time so that the input pulse width modulated signal and the complementary input pulse width modulated signal are not high at the same time.

12. The isolated driver circuit according to claim 11, wherein the rising edge detection circuit is a first rising edge detection circuit, the falling edge detection circuit is a first falling edge detection circuit, the decoder is a first decoder, and the isolated driver circuit further comprises: a second rising edge detection circuit configured to detect a rising edge of the complementary input pulse width modulation signal and output a corresponding complementary rising edge detection signal so as to be capacitively isolated from the complementary input pulse width modulation signal; a second falling edge detection circuit configured to detect a falling edge of the complementary input pulse width modulation signal and output a corresponding complementary falling edge detection signal so as to be capacitively isolated from the complementary input pulse width modulation signal; as well as A second decoder is configured to generate the complementary output pulse width modulated signal by generating a rising edge of the complementary output pulse width modulated signal corresponding in time to a detected rising edge of the complementary input pulse width modulated signal, and by generating a falling edge of the complementary output pulse width modulated signal corresponding in time to a detected falling edge of the complementary input pulse width modulated signal.

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