Semiconductor chip circuit

Abstract

The invention provides a semiconductor chip circuit. Comprising a power supply, a plurality of RC filters, a plurality of Schmidt circuits, a plurality of filter circuits, a plurality of level switching circuits, a dead zone interlocking circuit, a pulse circuit, a delay circuit, a bootstrap circuit, an undervoltage protection circuit, a temperature protection circuit, a fault logic control circuit, an overcurrent protection circuit, a high-side driving circuit and an AND gate. An anti-backflow protection circuit and a fault output circuit; the input end of the overcurrent protection circuit is connected with the output ends of the plurality of level conversion circuits, the input end of the anti-backflow protection circuit is connected with the output end of the high-side driving circuit, and the output end of the anti-backflow protection circuit is connected with the input end of the fault logic control circuit; when current flows back into the output end of the high-side driving circuit, the voltage of the output end of the anti-flow-back protection circuit is high level, and the fault logic control circuit controls the HO port and the LO port of the semiconductor chip to be switched off at the same time. The system is low in power consumption and high in reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor chip circuit. Background Art

[0002] High voltage integrated circuit, or HVIC, is a semiconductor chip product that converts MCU signals into integrated circuits that drive IGBT or MOS signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage level, high voltage level, pulse generation circuit, delay circuit, filter circuit, overcurrent protection circuit, overheat protection circuit, undervoltage protection circuit, bootstrap circuit and other circuits. The single pulse GEN circuit in the high-side drive circuit of the existing HVIC generates pulses at the rising and falling edges of the HIN signal to drive DMOS. The pulse width is generally several hundred nanoseconds, so that HIN corresponds to HO.

[0003] The driving signal of the traditional HVIC driver chip is converted from a low voltage level to a high voltage level. In order to realize the signal conversion from the low voltage domain to which VCC-GND belongs to the high voltage domain to which VCCA-VS belongs, a laterally diffused metal oxide semiconductor (LDMOS) device in the high and low voltage integration process is usually used for level shifting. However, since LDMOS is directly connected between the high voltage power supply and the ground, and is in a short circuit state (i.e., high voltage and large current at the drain) during normal operation, it is easy to cause thermal breakdown damage to the device. Therefore, in the HVIC driver chip structure, the rising edge and falling edge of the input signal are usually converted into two narrow pulse signals respectively, and the two narrow pulse signals are used to drive two LDMOS to transmit the signal to the high voltage area.

[0004] However, the above-mentioned high-voltage integrated chip HVIC has no internal detection and protection circuit for the output current, and the chip may be burned out due to the reverse current at the output end, and the reliability is poor. Summary of the invention

[0005] The present invention provides a semiconductor chip circuit, aiming to solve the problems of poor protection effect and reliability of existing high-voltage integrated chips.

[0006] An embodiment of the present invention provides a semiconductor chip circuit, including: a power supply, multiple RC filters, multiple Schmitt circuits, multiple filter circuits, multiple level conversion circuits, a dead zone interlocking circuit, a pulse circuit, a delay circuit, a bootstrap circuit, an undervoltage protection circuit, a temperature protection circuit, a fault logic control circuit, an overcurrent protection circuit, a high-side drive circuit, an AND gate, an anti-backfeed protection circuit, and a fault output circuit;

[0007] The plurality of RC filters are electrically connected to the plurality of Schmitt circuits, the plurality of filter circuits, the plurality of level conversion circuits and the dead zone interlocking circuit in sequence; the output end of the dead zone interlocking circuit is respectively connected to the input end of the pulse circuit and the input end of the delay circuit, the output end of the pulse circuit is connected to the input end of the high-side drive circuit, and the output end of the high-side drive circuit is used to connect a load; the output end of the delay circuit is connected to the first input end of the AND gate, the input end of the pulse circuit is also connected to the second input end of the AND gate, and the output end of the AND gate is connected to the high-side drive circuit; the input end of the bootstrap circuit and the input end of the undervoltage protection circuit are commonly connected to the power supply; the output end of the bootstrap circuit is connected to the high-side drive circuit; the output end of the undervoltage protection circuit is connected to The input end of the fault logic control circuit is connected to the output end of the AND gate and the fault output circuit respectively; the input end of the overcurrent protection circuit is connected to the output ends of the multiple level conversion circuits, and the output end of the overcurrent protection circuit is connected to the input end of the fault logic control circuit; the input end of the anti-backfeed protection circuit is connected to the output end of the high-side drive circuit, and the output end of the anti-backfeed protection circuit is connected to the input end of the fault logic control circuit; when the output end of the high-side drive circuit has current backfeeding, the voltage of the output end of the anti-backfeed protection circuit is high level, so as to control the operation of the fault logic control circuit, and the fault logic control circuit controls the HO port and LO port of the semiconductor chip to be turned off at the same time through the pulse circuit and the AND gate;

[0008] The anti-backfeeding protection circuit includes a startup module, a reference module, a comparison module, an inverter module and an anti-backfeeding module; the power supply is used to respectively power the startup module, the reference module, the comparison module, the anti-backfeeding module and the acquisition module; the startup module is electrically connected to the reference module, the comparison module, the inverter module and the anti-backfeeding module in sequence; the input end of the startup module serves as the input end of the anti-backfeeding protection circuit, and the output end of the anti-backfeeding module serves as the output end of the anti-backfeeding protection circuit.

[0009] Preferably, the startup module includes a first MOS tube, a second MOS tube and a third MOS tube;

[0010] The source of the first MOS tube serves as the input end of the startup module, and the gate of the first MOS tube is used to connect the output voltage of the reference module; the drain of the first MOS tube is respectively connected to the drain of the second MOS tube and the gate of the second MOS tube, the gate of the second MOS tube is also connected to the gate of the third MOS tube, and the source of the second MOS tube and the source of the third MOS tube are respectively grounded; the drain of the third MOS tube is connected to the input end of the reference module as the output end of the startup module.

[0011] Preferably, the reference module includes a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and a first resistor;

[0012] The source of the fourth MOS tube and the source of the fifth MOS tube are respectively connected to the power supply; the gate of the fourth MOS tube is respectively connected to the gate of the fifth MOS tube, the drain of the sixth MOS tube and the drain of the fifth MOS tube; the gate of the fourth MOS tube also serves as the input end of the reference module; the drain of the fourth MOS tube is respectively connected to the drain of the sixth MOS tube and the gate of the sixth MOS tube, the gate of the sixth MOS tube is also connected to the gate of the seventh MOS tube, the drain of the seventh MOS tube is connected to the drain of the fifth MOS tube and serves as the output end of the reference module; the source of the sixth MOS tube is grounded, and the source of the seventh MOS tube is connected to the first resistor and then grounded.

[0013] Preferably, the comparison module includes an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a twelfth MOS tube;

[0014] The source of the eighth MOS tube is connected to the source of the ninth MOS tube and connected to the power supply; the gate of the eighth MOS tube is respectively connected to the gate of the ninth MOS tube and the drain of the tenth MOS tube, the drain of the eighth MOS tube is connected to the drain of the tenth MOS tube, and the gate of the tenth MOS tube is connected to the drain of the seventh MOS tube as the input end of the comparison module; the source of the tenth MOS tube is respectively connected to the source of the eleventh MOS tube and the drain of the twelfth MOS tube, and the gate of the twelfth MOS tube is used to connect the output voltage of the reference module; the source of the twelfth MOS tube is grounded; the drain of the eleventh MOS tube is connected to the drain of the ninth MOS tube and serves as the output end of the comparison module, and the gate of the eleventh MOS tube is used to connect to the anti-backflow module.

[0015] Preferably, the inverter module includes a thirteenth MOS tube and a fourteenth MOS tube;

[0016] The source of the thirteenth MOS tube is connected to the source of the ninth MOS tube, the gate of the thirteenth MOS tube serves as the input end of the inverter module, and the drain of the thirteenth MOS tube serves as the output end of the inverter module;

[0017] The gate of the thirteenth MOS tube is respectively connected to the drain of the ninth MOS tube and the gate of the fourteenth MOS tube, the drain of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube, and the source of the fourteenth MOS tube is grounded.

[0018] Preferably, the anti-backflow module includes a fifteenth MOS tube, a sixteenth MOS tube, a second resistor, a third resistor, a fourth resistor and a triode;

[0019] The drain of the sixteenth MOS tube is connected to the first end of the fourth resistor and serves as the input end of the anti-backflow module, and the gate of the sixteenth MOS tube is respectively connected to the second end of the fourth resistor and the collector of the transistor; the gate of the fifteenth MOS tube is connected to the base of the transistor and serves as the output end of the anti-backflow module together, and the emitter of the transistor is grounded; the source of the fifteenth MOS tube and the drain of the fifteenth MOS tube are respectively grounded; the source of the sixteenth MOS tube is connected to the first end of the third resistor, the second end of the third resistor is respectively connected to the gate of the eleventh MOS tube and the first end of the second resistor, and the second end of the second resistor is grounded.

[0020] Preferably, the fifteenth MOS tube and the sixteenth MOS tube are both NMOS tubes.

[0021] Compared with the prior art, the beneficial effect of the present invention lies in that the output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the second input end of the AND gate and the fault output circuit; the input end of the overcurrent protection circuit is connected to the output ends of multiple level conversion circuits, and the output end of the overcurrent protection circuit is connected to the input end of the fault logic control circuit; the input end of the anti-backfeed protection circuit is connected to the output end of the high-side drive circuit, and the output end of the anti-backfeed protection circuit is connected to the input end of the fault logic control circuit; when current is backfed into the output end of the high-side drive circuit, the voltage of the output end of the anti-backfeed protection circuit is high level, thereby controlling the operation of the fault logic control circuit, and the fault logic control circuit controls the HO port and the LO port of the semiconductor chip to be turned off at the same time through the pulse circuit and the AND gate; in this way, the high-voltage driver chip with integrated anti-backfeed protection function can directly detect and protect the output end current of the driver chip in the power module, avoid the high-voltage driver chip from burning out due to excessive load current and current backfed, and extend the life of the high-voltage driver chip. At the same time, the chip's integrated anti-backflow protection circuit does not require a voltage regulator tube, which can reduce power consumption, improve noise resistance, and improve product stability and adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0023] Figure 1 is a circuit diagram of a semiconductor chip circuit provided by an embodiment of the present invention;

[0024] Figure 2 4 is a circuit diagram of an anti-backfeed protection circuit provided by an embodiment of the present invention.

[0025] In the figure, 1. RC filter, 2. Schmitt circuit, 3. filter circuit, 4. level conversion circuit, 5. dead zone interlock circuit, 6. pulse circuit, 7. delay circuit, 8. bootstrap circuit, 9. undervoltage protection circuit, 10. temperature protection circuit, 11. fault logic control circuit, 12. overcurrent protection circuit, 13. high-side drive circuit, 14. AND gate, 15. anti-backflow protection circuit, 151. startup module, 152. reference module, 153. comparison module, 154. inverter module, 155. anti-backflow module, 16. fault output circuit. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] Combined with Figure 1-Figure 2 As shown, an embodiment of the present invention provides a semiconductor chip circuit, including: a power supply VCC, multiple RC filters 1, multiple Schmitt circuits 2, multiple filter circuits 3, multiple level conversion circuits 4, a dead zone interlocking circuit 5, a pulse circuit 6, a delay circuit 7, a bootstrap circuit 8, an undervoltage protection circuit 9, a temperature protection circuit 10, a fault logic control circuit 11, an overcurrent protection circuit 12, a high-side drive circuit 13, an AND gate 14, an anti-backflow protection circuit 15 and a fault output circuit 16.

[0028] The multiple RC filters 1 are electrically connected to the multiple Schmitt circuits 2, the multiple filter circuits 3, the multiple level conversion circuits 4 and the dead zone interlocking circuit 5 in sequence; the output end of the dead zone interlocking circuit 5 is respectively connected to the input end of the pulse circuit 6 and the input end of the delay circuit 7, the output end of the pulse circuit 6 is connected to the input end of the high-side driving circuit 13, and the output end of the high-side driving circuit 13 is used to connect the load; the output end of the delay circuit 7 is connected to the first input end of the AND gate 14, the input end of the pulse circuit 6 is also connected to the second input end of the AND gate 14, and the output end of the AND gate 14 is connected to the high-side driving circuit 13; the input end of the bootstrap circuit 8 and the input end of the undervoltage protection circuit 9 are commonly connected to the power supply VCC; the output end of the bootstrap circuit 8 is connected to the high-side driving circuit 13; the output end of the undervoltage protection circuit 9 is connected to the The input end of the fault logic control circuit 11, the output end of the fault logic control circuit 11 is respectively connected to the second input end of the AND gate 14 and the fault output circuit 16; the input end of the overcurrent protection circuit 12 is connected to the output ends of the multiple level conversion circuits 4, and the output end of the overcurrent protection circuit 12 is connected to the input end of the fault logic control circuit 11; the input end of the anti-backfeed protection circuit 15 is connected to the output end of the high-side drive circuit 13, and the output end of the anti-backfeed protection circuit 15 is connected to the input end of the fault logic control circuit 11; when the output end of the high-side drive circuit 13 has current backfeeding, the voltage at the output end of the anti-backfeed protection circuit 15 is high level, thereby controlling the fault logic control circuit 11 to work, and the fault logic control circuit 11 controls the HO port and LO port of the semiconductor chip to be turned off at the same time through the pulse circuit 6 and the AND gate 14. Wherein, when the output end of the HVIC is normal, the voltage at the output end of the anti-backfeed protection circuit 15 is low level, which has no effect on the fault logic control circuit 11, and no anti-backfeed protection is performed.

[0029] Specifically, HIN and LIN input drive signals, pass through RC filter 1, Schmitt circuit 2, filter circuit 3, level conversion circuit 4, and dead zone interlock circuit 5 to output HINa pulse signal, and pulse circuit 6 outputs ON_PLUSE / SET and OFF_PLUSE / RESET short pulse signals through the rising edge and falling edge of the HINa pulse signal respectively to drive UVWQ1 and UVWQ2 high-voltage LDMOS, and the high-voltage LDMOS is turned on and off to trigger the RS trigger to output the pulse signal, and control HO to output the drive pulse signal; the LINa pulse signal is output, and passes through the delay circuit and AND gate 14 to control LO to output the drive pulse signal.

[0030] The outputs of the drive signals HO and LO are protected by the undervoltage protection circuit 9, the temperature protection circuit 10, the overcurrent protection circuit 12 (ITRIP circuit) and the fault logic control circuit 11. The bootstrap circuit 8 provides the bootstrap voltage to HO. The fault output circuit 16 is used to output the fault signal of the fault logic control circuit 11.

[0031] Specifically, the anti-backflow protection circuit 15 includes a startup module 151, a reference module 152, a comparison module 153, an inverter module 154 and an anti-backflow module 155; the power supply VCC is used to supply power to the startup module 151, the reference module 152, the comparison module 153, the anti-backflow module 155 and the acquisition module respectively; the startup module 151 is electrically connected to the reference module 152, the comparison module 153, the inverter module 154 and the anti-backflow module 155 in sequence; the input end of the startup module 151 serves as the input end of the anti-backflow protection circuit 15, and the output end of the anti-backflow module 155 serves as the output end of the anti-backflow protection circuit 15. In this way, the high-voltage driver chip with integrated anti-backflow protection function can directly detect and protect the output end current of the driver chip in the power module, avoid the high-voltage driver chip from burning out due to excessive load current and current backflow, and extend the life of the high-voltage driver chip. At the same time, the chip's integrated anti-reverse feeding protection circuit 15 does not require a voltage regulator tube, which can reduce power consumption, improve noise resistance, and improve product stability and adaptability. 1. The design of the anti-reverse feeding protection circuit 15 uses CADENCE's VIRTUOSO for layout design and CALIBRE for DRC and LVS error checking; the anti-reverse feeding protection circuit 15 is integrated into the HVIC, and the circuit function simulation of the HVIC complete circuit and CALIBRE for DRC and LVS error checking are performed; the circuit layout of the anti-reverse feeding protection circuit 15 is integrated into the HVIC layout, and the layout circuit connection is connected according to the circuit schematic diagram.

[0032] In this embodiment, the startup module 151 includes a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3;

[0033] The source of the first MOS tube M1 serves as the input end of the startup module 151, and the gate of the first MOS tube M1 is used to connect the output voltage of the reference module 152; the drain of the first MOS tube M1 is respectively connected to the drain of the second MOS tube M2 and the gate of the second MOS tube M2, the gate of the second MOS tube M2 is also connected to the gate of the third MOS tube M3, and the source of the second MOS tube M2 and the source of the third MOS tube M3 are respectively grounded; the drain of the third MOS tube M3, as the output end of the startup module 151, is connected to the input end of the reference module 152.

[0034] In this embodiment, the reference module 152 includes a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7 and a first resistor R1;

[0035] The source of the fourth MOS tube M4 and the source of the fifth MOS tube M5 are respectively connected to the power supply VCC; the gate of the fourth MOS tube M4 is respectively connected to the gate of the fifth MOS tube M5, the drain of the sixth MOS tube M6 and the drain of the fifth MOS tube M5; the gate of the fourth MOS tube M4 also serves as the input end of the reference module 152; the drain of the fourth MOS tube M4 is respectively connected to the drain of the sixth MOS tube M6 and the gate of the sixth MOS tube M6, the gate of the sixth MOS tube M6 is also connected to the gate of the seventh MOS tube M7, the drain of the seventh MOS tube M7 is connected to the drain of the fifth MOS tube M5 and serves as the output end of the reference module 152; the source of the sixth MOS tube M6 is grounded, and the source of the seventh MOS tube M7 is connected to the first resistor R1 and then grounded.

[0036] In this embodiment, the comparison module 153 includes an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11 and a twelfth MOS tube M12;

[0037] The source of the eighth MOS tube M8 is connected to the source of the ninth MOS tube M9 and to the power supply VCC; the gate of the eighth MOS tube M8 is respectively connected to the gate of the ninth MOS tube M9 and the drain of the tenth MOS tube M10, the drain of the eighth MOS tube M8 is connected to the drain of the tenth MOS tube M10, and the gate of the tenth MOS tube M10 is connected to the drain of the seventh MOS tube M7 as the input end of the comparison module 153; the source of the tenth MOS tube M10 is respectively connected to the source of the eleventh MOS tube M11 and the drain of the twelfth MOS tube M12, and the gate of the twelfth MOS tube M12 is used to connect the output voltage of the reference module 152; the source of the twelfth MOS tube M12 is grounded; the drain of the eleventh MOS tube M11 is connected to the drain of the ninth MOS tube M9 and serves as the output end of the comparison module 153, and the gate of the eleventh MOS tube M11 is used to connect to the anti-backflow module 155.

[0038] In this embodiment, the inverter module 154 includes a thirteenth MOS transistor M13 and a fourteenth MOS transistor M14;

[0039] The source of the thirteenth MOS transistor M13 is connected to the source of the ninth MOS transistor M9, the gate of the thirteenth MOS transistor M13 serves as the input end of the inverter module 154, and the drain of the thirteenth MOS transistor M13 serves as the output end of the inverter module 154;

[0040] The gate of the thirteenth MOS tube M13 is respectively connected to the drain of the ninth MOS tube M9 and the gate of the fourteenth MOS tube M14, the drain of the thirteenth MOS tube M13 is connected to the drain of the fourteenth MOS tube M14, and the source of the fourteenth MOS tube M14 is grounded.

[0041] In this embodiment, the anti-backflow module 155 includes a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor Q1;

[0042] The drain of the sixteenth MOS tube M16 is connected to the first end of the fourth resistor R4 and serves as the input end of the anti-backflow module 155, and the gate of the sixteenth MOS tube M16 is respectively connected to the second end of the fourth resistor R4 and the collector of the transistor Q1; the gate of the fifteenth MOS tube M15 is connected to the base of the transistor and serves as the output end of the anti-backflow module 155, and the emitter of the transistor is grounded; the source of the fifteenth MOS tube M15 and the drain of the fifteenth MOS tube M15 are respectively grounded; the source of the sixteenth MOS tube M16 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is respectively connected to the gate of the eleventh MOS tube M11 and the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0043] In this embodiment, the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are both NMOS transistors.

[0044] Specifically, the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 form the startup module 151. The gate of the first MOS transistor M1 of the startup module 151 is connected to the point b of the reference module 152 and is driven by Vb. The drain of the third MOS transistor M3 is connected to the point a. The first MOS transistor M1 is a PMOS transistor, and the second MOS transistor M2 and the third MOS transistor M3 are NMOS transistors.

[0045] The sixth MOS tube M6 and the seventh MOS tube M7 of the NMOS tube, the fourth MOS tube M4 and the fifth MOS tube M5 of the PMOS tube and the first resistor R1 form a reference module 152. The sixth MOS tube M6 and the seventh MOS tube M7 have the same width-to-length ratio, and the fourth MOS tube M4 and the fifth MOS tube M5 have the same width-to-length ratio. The output voltage V b =2(R1+r O7 ) / u n C ox (W / L)7R1R1……(1), from the above formula, it can be seen that the output voltage Vb at point b is a fixed value and is not affected by the power supply voltage VCC. Among them, R1 is the resistance of resistor R1, ro7 is the equivalent internal resistance of the seventh MOS tube M7, un is the electron mobility, Cox is the gate oxide layer capacitance, and W / L is the width-to-length ratio of the MOS tube.

[0046] The tenth MOS tube M10, the eleventh MOS tube M11, the twelfth MOS tube M12 of the NMOS tube and the eighth MOS tube M8, the ninth MOS tube M9 of the PMOS tube form a comparison module 153, which is a differential amplifier circuit, and can amplify and output the difference between the gate voltage Ve of the eleventh MOS tube M11 and the gate voltage Vb of the tenth MOS tube M10 from point c; the voltage at point c is Vc =g m11 (r O11 / / r O9 )(V b -V e )……(2), it can be seen from the above formula that the voltage Ve at point e increases and the voltage Vc at point c decreases; wherein, gm11 is the transconductance of the eleventh MOS tube M11, ro11 is the equivalent internal resistance of the eleventh MOS tube M11, ro9 is the equivalent internal resistance of the ninth MOS tube M9, and ro11 / / ro9 represents the parallel connection of two equivalent internal resistances.

[0047] The fourteenth MOS tube M14 of the NMOS tube and the thirteenth MOS tube M13 of the PMOS tube form an inverter module 154 , which transmits the signal detected by the comparison module 153 to the fault logic control circuit 11 .

[0048] The fifteenth MOS tube M15 of the NMOS tube, the transistor Q1, and the fourth resistor R4 form an anti-backflow module 155, which is used to prevent the load voltage from being too large to damage the circuit. The base of the transistor Q1 is connected to point c, the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the gates of the thirteenth MOS tube M13 and the fourteenth MOS tube M14; the thirteenth MOS tube M13 of the PMOS tube is reversely connected in the circuit, the drain is connected to VCC, and the source is connected to the source of the fourteenth MOS tube M14 of the PMOS tube. The two thirteenth MOS tubes M13 and the fourteenth MOS tube M14 are reversely connected, which can reduce the influence of the MOS tube body diode on the circuit.

[0049] The second resistor R2, the third resistor R3, the fourth resistor R4 and the fifteenth MOS tube M15, the sixteenth MOS tube M16 and the triode Q1 of the NMOS tube form a backfeed detection module, the sixteenth MOS tube M16 controls the current flowing through the second resistor R2 and the third resistor R3, the second resistor R2 and the third resistor R3 divide the voltage and sample, collect the voltage Ve at point e, and transmit it to the gate of the eleventh MOS tube M11 of the comparison module 153; the drain and source of the fifteenth MOS tube M15 are both grounded, and the gate is connected to point c, which is used as a capacitor to prevent the instantaneous fluctuation of the voltage at point c from affecting the triode Q1 and causing false triggering. The triode Q1 controls the on and off of the sixteenth MOS tube M16, and the fourth resistor R4 protects the sixteenth MOS tube M16 to prevent the sixteenth MOS tube M16 from being damaged by excessive backfeed current.

[0050] When no current backflow occurs, the voltage Ve at point e is 0, which is a low level, the voltage at point c is a high level, the transistor Q1 is turned on, the sixteenth MOS tube M16 is in the off state, and at the same time, the OUT terminal outputs a low level.

[0051] When current backflow occurs, the gate voltage of the sixteenth MOS tube M16 increases, and the sixteenth MOS tube M16 is turned on. At this time, the backflow current passes through the second resistor R2 and the third resistor R3 to the ground, the voltage at point e increases to a high level, the voltage at point c decreases to a low level, the transistor Q1 is turned off, and the OUT terminal outputs a high level.

[0052] When the reverse current is discharged to the ground, the sixteenth MOS tube M16 is turned off, and the voltage at point e returns to a low level. At this time, the circuit returns to a normal state, and the OUT terminal outputs a low level. In this way, the high-voltage driver chip with an integrated anti-reverse protection circuit 15 can directly detect and protect the output current of the driver chip in the traditional power module, avoiding the burning of the high-voltage driver chip due to the reverse current at the output end, and extending the life of the high-voltage driver chip. At the same time, the anti-reverse protection circuit 15 integrated in the chip does not require a voltage regulator tube, which can reduce power consumption, improve noise resistance, and improve product stability and adaptability.

[0053] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0054] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A semiconductor chip circuit, characterized in that: include: Power supply, multiple RC filters, multiple Schmitt circuits, multiple filter circuits, multiple level conversion circuits, dead zone interlock circuits, pulse circuits, delay circuits, bootstrap circuits, undervoltage protection circuits, temperature protection circuits, fault logic control circuits, overcurrent protection circuits, high-side drive circuits, AND gates, anti-backfeed protection circuits, and fault output circuits; The plurality of RC filters are electrically connected to the plurality of Schmitt circuits, the plurality of filter circuits, the plurality of level conversion circuits and the dead zone interlocking circuit in sequence; the output end of the dead zone interlocking circuit is respectively connected to the input end of the pulse circuit and the input end of the delay circuit, the output end of the pulse circuit is connected to the input end of the high-side drive circuit, and the output end of the high-side drive circuit is used to connect a load; the output end of the delay circuit is connected to the first input end of the AND gate, the input end of the pulse circuit is also connected to the second input end of the AND gate, and the output end of the AND gate is connected to the high-side drive circuit; the input end of the bootstrap circuit and the input end of the undervoltage protection circuit are commonly connected to the power supply; The output end of the bootstrap circuit is connected to the high-side drive circuit; The output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the second input end of the AND gate and the fault output circuit; The input end of the overcurrent protection circuit is connected to the output ends of the multiple level conversion circuits, and the output end of the overcurrent protection circuit is connected to the input end of the fault logic control circuit; the input end of the anti-backfeed protection circuit is connected to the output end of the high-side drive circuit, and the output end of the anti-backfeed protection circuit is connected to the input end of the fault logic control circuit; when current is backfed into the output end of the high-side drive circuit, the voltage of the output end of the anti-backfeed protection circuit is high level, so as to control the operation of the fault logic control circuit, and the fault logic control circuit controls the HO port and LO port of the semiconductor chip to be turned off at the same time through the pulse circuit and the AND gate; The anti-backfeeding protection circuit includes a startup module, a reference module, a comparison module, an inverter module and an anti-backfeeding module; the power supply is used to respectively power the startup module, the reference module, the comparison module, the anti-backfeeding module and the acquisition module; the startup module is electrically connected to the reference module, the comparison module, the inverter module and the anti-backfeeding module in sequence; the input end of the startup module serves as the input end of the anti-backfeeding protection circuit, and the output end of the anti-backfeeding module serves as the output end of the anti-backfeeding protection circuit.

2. The semiconductor chip circuit according to claim 1, characterized in that: The startup module includes a first MOS tube, a second MOS tube and a third MOS tube; The source of the first MOS tube serves as the input end of the startup module, and the gate of the first MOS tube is used to connect the output voltage of the reference module; the drain of the first MOS tube is respectively connected to the drain of the second MOS tube and the gate of the second MOS tube, the gate of the second MOS tube is also connected to the gate of the third MOS tube, and the source of the second MOS tube and the source of the third MOS tube are respectively grounded; the drain of the third MOS tube is connected to the input end of the reference module as the output end of the startup module.

3. The semiconductor chip circuit according to claim 2, characterized in that: The reference module includes a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and a first resistor; The source of the fourth MOS tube and the source of the fifth MOS tube are respectively connected to the power supply; the gate of the fourth MOS tube is respectively connected to the gate of the fifth MOS tube, the drain of the sixth MOS tube and the drain of the fifth MOS tube; the gate of the fourth MOS tube also serves as the input end of the reference module; the drain of the fourth MOS tube is respectively connected to the drain of the sixth MOS tube and the gate of the sixth MOS tube, the gate of the sixth MOS tube is also connected to the gate of the seventh MOS tube, the drain of the seventh MOS tube is connected to the drain of the fifth MOS tube and serves as the output end of the reference module; the source of the sixth MOS tube is grounded, and the source of the seventh MOS tube is connected to the first resistor and then grounded.

4. The semiconductor chip circuit according to claim 3, characterized in that: The comparison module includes an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a twelfth MOS tube; The source of the eighth MOS tube is connected to the source of the ninth MOS tube and to the power supply; the gate of the eighth MOS tube is respectively connected to the gate of the ninth MOS tube and the drain of the tenth MOS tube, the drain of the eighth MOS tube is connected to the drain of the tenth MOS tube, and the gate of the tenth MOS tube is connected to the drain of the seventh MOS tube as the input end of the comparison module; The source of the tenth MOS tube is respectively connected to the source of the eleventh MOS tube and the drain of the twelfth MOS tube, and the gate of the twelfth MOS tube is used to connect the output voltage of the reference module; the source of the twelfth MOS tube is grounded; the drain of the eleventh MOS tube is connected to the drain of the ninth MOS tube and serves as the output end of the comparison module, and the gate of the eleventh MOS tube is used to connect to the anti-backflow module.

5. The semiconductor chip circuit according to claim 4, characterized in that: The inverter module includes a thirteenth MOS tube and a fourteenth MOS tube; The source of the thirteenth MOS tube is connected to the source of the ninth MOS tube, the gate of the thirteenth MOS tube serves as the input end of the inverter module, and the drain of the thirteenth MOS tube serves as the output end of the inverter module; The gate of the thirteenth MOS tube is respectively connected to the drain of the ninth MOS tube and the gate of the fourteenth MOS tube, the drain of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube, and the source of the fourteenth MOS tube is grounded.

6. The semiconductor chip circuit according to claim 1, wherein: The anti-backflow module includes a fifteenth MOS tube, a sixteenth MOS tube, a second resistor, a third resistor, a fourth resistor and a triode; The drain of the sixteenth MOS tube is connected to the first end of the fourth resistor and serves as the input end of the anti-backflow module, and the gate of the sixteenth MOS tube is respectively connected to the second end of the fourth resistor and the collector of the transistor; the gate of the fifteenth MOS tube is connected to the base of the transistor and serves as the output end of the anti-backflow module together, and the emitter of the transistor is grounded; the source of the fifteenth MOS tube and the drain of the fifteenth MOS tube are respectively grounded; the source of the sixteenth MOS tube is connected to the first end of the third resistor, the second end of the third resistor is respectively connected to the gate of the eleventh MOS tube and the first end of the second resistor, and the second end of the second resistor is grounded.

7. The semiconductor chip circuit according to claim 6, characterized in that: The fifteenth MOS tube and the sixteenth MOS tube are both NMOS tubes.

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