Signal delay setting circuit, isolated integrated circuit and power conversion circuit system

Abstract

The invention provides a signal delay setting circuit, an isolated integrated circuit and a power conversion circuit system. The isolation type integrated circuit comprises a primary side circuit, an isolation circuit and a secondary side circuit. The primary side circuit generates a primary side signal according to a first input signal and a second input signal. The isolation circuit converts the primary side signal into a secondary side signal. The secondary side circuit generates an output signal according to the secondary side signal. The signal delay setting circuit is coupled to the secondary side circuit and the replaceable end and the secondary side grounding end of the isolated integrated circuit, calculates delay time according to the voltage difference between the replaceable end and the secondary side grounding end, and delays the secondary side signal according to the delay time so as to control the duty ratio of the output signal. The duty ratio of the output signal of the isolated integrated circuit is controlled through the signal delay setting circuit, the power conversion circuit system effectively generates dead time to protect the high-side switch and the low-side switch, and the power conversion circuit system has the advantages of being low in deviation, high in reliability, small in circuit area requirement and the like.

Description

Technical Field

[0001] The present disclosure relates to a signal delay setting circuit, and more particularly to a signal delay setting circuit applied to an isolated integrated circuit. Background Art

[0002] In a circuit structure composed of a high-side switch and a low-side switch, it is usually necessary to turn on the high-side switch and the low-side switch alternately to complete the operation. However, due to some non-ideal factors, the high-side switch and the low-side switch may be turned on at the same time, which may cause the high-side switch and the low-side switch to be damaged due to the large current flowing through them.

[0003] Some related technologies use a resistor-capacitor circuit (RC circuit) to set or use a trimming method to generate a dead zone or dead time to ensure that the high-side switch and the low-side switch are not turned on at the same time, but these related technologies each have their own problems. For example, the dead time generated by the related technology using a resistor-capacitor circuit may have a higher deviation due to the physical properties of the resistor and / or capacitor. For another example, the related technology using the trimming method may increase the complexity of the entire system. Therefore, it is necessary to propose a new method to solve the above problems. Summary of the invention

[0004] One aspect of the present disclosure is a signal delay setting circuit suitable for an isolated integrated circuit. The isolated integrated circuit includes a primary side circuit, an isolation circuit and a secondary side circuit, wherein the isolation circuit is used to convert the primary side signal from the primary side circuit into a secondary side signal, and the secondary side circuit is coupled to the replaceable end and the secondary side ground end of the isolated integrated circuit. The signal delay setting circuit includes a voltage drop generating circuit, a delay time calculating circuit and a signal delay circuit. The voltage drop generating circuit is coupled to the replaceable end and the secondary side ground end, and generates a voltage difference between the replaceable end and the secondary side ground end. The delay time calculating circuit is coupled to the voltage drop generating circuit, and calculates the delay time according to the voltage difference. The signal delay circuit is coupled to the delay time calculating circuit, and delays the secondary side signal received by the secondary side circuit from the isolation circuit according to the delay time, so as to control the duty cycle of the output signal generated by the secondary side circuit according to the secondary side signal, wherein the primary side signal is generated by the primary side circuit according to the first input signal and the second input signal.

[0005] In some embodiments, the voltage drop generating circuit includes a resistor element and a current generating circuit. The resistor element is coupled between the replaceable end and the secondary side grounding end. The current generating circuit and the resistor element are coupled to the replaceable end, and are used to receive the secondary side power supply voltage provided to the secondary side circuit, and to output a detection current flowing through the resistor element according to the secondary side power supply voltage, so that the voltage difference is generated between the replaceable end and the secondary side grounding end.

[0006] In some embodiments, the resistor element is disposed outside the isolated integrated circuit, and the current generating circuit is disposed inside the isolated integrated circuit.

[0007] In some embodiments, the delay time calculation circuit and the signal delay circuit are integrated into a control logic circuit of the secondary side circuit, and the voltage drop generation circuit is coupled to the control logic circuit via a buffer gate.

[0008] In some embodiments, the signal delay circuit is used to delay a plurality of rising edges of the secondary-side signal by the delay time.

[0009] In some embodiments, the delay time calculation circuit calculates the delay time according to the voltage difference by table lookup or formula calculation.

[0010] In some embodiments, the secondary side circuit is used to receive the secondary side power supply voltage through the secondary side power supply terminal of the isolated integrated circuit, and the voltage drop generating circuit is used to generate the voltage difference when the secondary side power supply voltage exceeds the power-on reset voltage.

[0011] In some embodiments, the signal delay circuit is used to delay the secondary-side signal according to the delay time when the secondary-side power supply voltage exceeds an under-voltage lockout voltage, wherein the under-voltage lockout voltage is greater than the power-on reset voltage.

[0012] Another aspect of the present disclosure is an isolated integrated circuit. The isolated integrated circuit includes a primary side circuit, an isolation circuit, a secondary side circuit and a signal delay setting circuit. The primary side circuit receives a first input signal and a second input signal, and generates a primary side signal according to the first input signal and the second input signal. The isolation circuit is coupled to the primary side circuit and converts the primary side signal into a secondary side signal. The secondary side circuit is coupled to the isolation circuit, receives the secondary side signal through the isolation circuit, generates an output signal according to the secondary side signal, and receives the secondary side power supply voltage. The signal delay setting circuit is coupled to the replaceable end and the secondary side ground end of the secondary side circuit and the isolated integrated circuit, detects the voltage difference between the replaceable end and the secondary side ground end when the secondary side power supply voltage exceeds the preset voltage, calculates the delay time according to the voltage difference, and delays the secondary side signal according to the delay time to control the duty cycle of the output signal.

[0013] Another aspect of the present disclosure is a power conversion circuit system. The power conversion circuit system includes a high-side switch, a low-side switch, a controller circuit, a first isolated integrated circuit and a second isolated integrated circuit. The controller circuit outputs a first input signal and a second input signal. The first isolated integrated circuit is coupled to the controller circuit and the high-side switch, and includes a first signal delay setting circuit, a first signal input terminal, a second signal input terminal, a first alternative terminal and a first secondary side ground terminal. The first input signal is received through the first signal input terminal, and the second input signal is received through the second signal input terminal to generate a first output signal for driving the high-side switch. The second isolated integrated circuit is coupled to the controller circuit and the low-side switch, and includes a second signal delay setting circuit, a third signal input terminal, a fourth signal input terminal, a second alternative terminal and a second secondary side ground terminal. The second input signal is received through the third signal input terminal, and the first input signal is received through the fourth signal input terminal to generate a second output signal for driving the low-side switch. When the first secondary power supply voltage received by the first isolated integrated circuit and the second secondary power supply voltage received by the second isolated integrated circuit exceed the preset voltage, the first signal delay setting circuit calculates the first delay time according to the first voltage difference between the first alternative terminal and the first secondary ground terminal, and the second signal delay setting circuit calculates the second delay time according to the second voltage difference between the second alternative terminal and the second secondary ground terminal. When the first secondary power supply voltage and the second secondary power supply voltage exceed the protection voltage greater than the preset voltage, the first signal delay setting circuit delays the first secondary signal generated by the first isolated integrated circuit according to the first input signal and the second input signal according to the first delay time to control the duty cycle of the first output signal, and the second signal delay setting circuit delays the second secondary signal generated by the second isolated integrated circuit according to the first input signal and the second input signal according to the second delay time to control the duty cycle of the second output signal, so that the high-side switch and the low-side switch will not be turned on at the same time.

[0014] In summary, by controlling the duty cycle of the output signal generated by the isolated integrated circuit through the signal delay setting circuit, the power conversion circuit system of the present disclosure can effectively generate dead time to protect the high-side switch and the low-side switch. In addition, compared with some related technologies that generate dead time by using resistor and capacitor circuit settings or using trimming methods, the isolated integrated circuit and power conversion circuit system of the present disclosure have the advantages of low deviation, high reliability, and small circuit area requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The invention is a circuit block diagram of a power conversion circuit system according to some embodiments of the present disclosure.

[0016] Figure 2The invention is a circuit diagram of an isolated integrated circuit according to some embodiments of the present disclosure.

[0017] Figure 3 The invention is a circuit block diagram of a control logic circuit, an amplifier circuit, a receiving circuit, a buffer gate and a voltage drop generating circuit according to some embodiments of the present disclosure.

[0018] Figure 4 The figure is a signal timing diagram of an isolated integrated circuit according to some embodiments of the present disclosure.

[0019] Figure 5 The figure is a signal timing diagram of an isolated integrated circuit according to some embodiments of the present disclosure.

[0020] Figure 6 FIG. 1 is a timing diagram of output signals of two isolated integrated circuits according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] The following is a detailed description of the embodiments with the accompanying drawings, but the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operation is not used to limit the order of its execution. Any structure recombined by the elements to produce a device with equal functions is within the scope of the present disclosure.

[0022] The terms used throughout the specification and claims generally have the ordinary meanings of each term used in the art, in the context of this disclosure, and in the specific context, unless otherwise noted.

[0023] As used herein, “coupled” or “connected” may refer to direct physical or electrical contact between two or more elements, or indirect physical or electrical contact between two or more elements, or may refer to mutual operation or action between two or more elements.

[0024] See also Figure 1 , Figure 1 FIG. 1 is a circuit block diagram of a power conversion circuit system 100 according to some embodiments of the present disclosure. In some embodiments, the power conversion circuit system 100 includes a controller circuit 11, an isolated integrated circuit 13, an isolated integrated circuit 15, a high-side switch 17, and a low-side switch 19. Specifically, the power conversion circuit system 100 may be, for example but not limited to, a buck converter.

[0025] In some embodiments, such as Figure 1As shown, the controller circuit 11 is electrically coupled to the isolated integrated circuit 13 and the isolated integrated circuit 15. The isolated integrated circuit 13 is electrically coupled to the high-side switch 17, and the isolated integrated circuit 15 is electrically coupled to the low-side switch 19. In addition, the high-side switch 17 is connected in series with the low-side switch 19. It should be understood that in some embodiments, the connection node between the high-side switch 17 and the low-side switch 19 can be electrically coupled to a load circuit (not shown).

[0026] According to the circuit architecture of the power conversion circuit system 100, in some embodiments, the controller circuit 11 is used to output the first input signal IN+ and the second input signal IN- to the isolated integrated circuit 13 and the isolated integrated circuit 15, wherein the first input signal IN+ and the second input signal IN- are inverted to each other, but the present invention is not limited thereto. The isolated integrated circuit 13 is used to generate the output signal OUT1 to the high-side switch 17 according to the first input signal IN+ and the second input signal IN-. The isolated integrated circuit 15 is used to generate the output signal OUT2 to the low-side switch 19 according to the first input signal IN+ and the second input signal IN-. By driving the output signal OUT1 and the output signal OUT2, the high-side switch 17 and the low-side switch 19 will be turned on alternately to generate an output current (not shown) flowing through the aforementioned load circuit. In some embodiments, the first input signal IN+, the second input signal IN-, the output signal OUT1 and the output signal OUT2 are all periodic signals. In addition, the output signal OUT1 and the output signal OUT2 are substantially inversely phased to each other, and thus can drive the high-side switch 17 and the low-side switch 19 to be turned on alternately.

[0027] In some embodiments, the isolated integrated circuit 13 includes a primary side power supply terminal P31, a first signal input terminal P32, a second signal input terminal P33, a primary side ground terminal P34, a secondary side power supply terminal P35, a signal output terminal P36, an alternative terminal P37, and a secondary side ground terminal P38. Figure 1 As shown, the isolated integrated circuit 13 receives the primary side power supply voltage VCC through the primary side power supply terminal P31, receives the first input signal IN+ through the first signal input terminal P32, receives the second input signal IN- through the second signal input terminal P33, receives the primary side ground voltage GND through the primary side ground terminal P34, receives the secondary side power supply voltage VDD1 through the secondary side power supply terminal P35, outputs the output signal OUT1 through the signal output terminal P36, and receives the secondary side ground voltage VEE1 through the secondary side ground terminal P38.

[0028] In some embodiments, the isolated integrated circuit 15 includes a primary side power supply terminal P51, a first signal input terminal P52, a second signal input terminal P53, a primary side ground terminal P54, a secondary side power supply terminal P55, a signal output terminal P56, a replaceable terminal P57, and a secondary side ground terminal P58. Figure 1 As shown, the isolated integrated circuit 15 receives the primary side power supply voltage VCC through the primary side power supply terminal P51, receives the second input signal IN- through the first signal input terminal P52, receives the first input signal IN+ through the second signal input terminal P53, receives the primary side ground voltage GND through the primary side ground terminal P54, receives the secondary side power supply voltage VDD2 through the secondary side power supply terminal P55, outputs the output signal OUT2 through the signal output terminal P56, and receives the secondary side ground voltage VEE2 through the secondary side ground terminal P58.

[0029] In the above embodiment, if Figure 1 As shown, the high-side switch 17 is coupled to the third power supply voltage HVDC, and the low-side switch 19 is coupled to the secondary-side ground voltage VEE2. That is, the high-side switch 17 and the low-side switch 19 are connected in series between the third power supply voltage HVDC and the secondary-side ground voltage VEE2. In the above embodiment, the voltage values ​​of the primary-side power supply voltage VCC, the secondary-side power supply voltage VDD1, the secondary-side power supply voltage VDD2 and the third power supply voltage HVDC may be all the same, all different, or partially the same and partially different, and the voltage values ​​of the primary-side ground voltage GND, the secondary-side ground voltage VEE1 and the secondary-side ground voltage VEE2 may be all the same or all different.

[0030] Generally speaking, the high-side switch 17 and the low-side switch 19 can each be implemented by one or more transistors (e.g., metal oxide semiconductor (MOS) transistors). Therefore, if the high-side switch 17 and the low-side switch 19 are turned on at the same time due to some non-ideal factors, a large current may flow through the high-side switch 17 and the low-side switch 19, which further causes the high-side switch 17 and the low-side switch 19 themselves or the internal transistors to burn out.

[0031] In view of this, in some embodiments, the isolated integrated circuit 13 is configured with a signal delay setting circuit 131, and the isolated integrated circuit 15 is configured with a signal delay setting circuit 151. It is worth noting that the signal delay setting circuit 131 and the signal delay setting circuit 151 are respectively used to control the duty ratio of the output signal OUT1 and the duty ratio of the output signal OUT2, thereby ensuring that the high-side switch 17 and the low-side switch 19 are not turned on at the same time.

[0032] Then match Figure 2Describe the isolated integrated circuit 13 in detail, Figure 2 1 is a circuit diagram of an isolated integrated circuit 13 according to some embodiments of the present disclosure. In some embodiments, the isolated integrated circuit 13 includes the aforementioned signal delay setting circuit 131, a primary side circuit 133, an isolation circuit 135, and a secondary side circuit 137. Specifically, the isolated integrated circuit 13 can be, for example but not limited to, a gate driver. That is, in some embodiments, the output signal OUT1 is output to the gate of the transistor in the high-side switch 17.

[0033] In some embodiments, the signal delay setting circuit 131 includes a voltage drop generating circuit 311, a delay time calculating circuit 313, and a signal delay circuit 315. In some further embodiments, the voltage drop generating circuit 311 includes a current generating circuit ICS and a resistance element RDT. Specifically, the current generating circuit ICS can be implemented by a current source (e.g., a current mirror circuit), and the resistance element RDT can be implemented by a resistor. It should be understood that in some embodiments, the resistance element RDT can also be replaced by other suitable passive elements (e.g., capacitors, inductors, etc.).

[0034] In some embodiments, the primary circuit 133 includes a logic control circuit 331, a buffer gate 333, a NOT gate 335, and an undervoltage lockout circuit 337. Specifically, the logic control circuit 331 can be implemented by a logic circuit, an oscillator, a modulator, a transmitter, or a combination thereof. In some embodiments, the logic circuit in the logic control circuit 331 can include an AND gate (not shown).

[0035] In some embodiments, the buffer gate 333 is coupled between the first signal input terminal P32 and the first data input terminal of the AND gate in the logic control circuit 331. The reverse gate 335 is coupled between the second signal input terminal P33 and the second data input terminal of the AND gate in the logic control circuit 331. The undervoltage lockout circuit 337 is coupled between the primary side power supply terminal P31 and the logic control circuit 331. Moreover, the logic control circuit 331 is coupled to the primary side power supply terminal P31 to directly receive the primary side power supply voltage VCC.

[0036] In some embodiments, one end of the isolation circuit 135 is coupled to the output end of the primary circuit 133 (i.e., the data output end of the logic control circuit 331), and the other end of the isolation circuit 135 is coupled to the input end of the secondary circuit 137, so as to provide electrical insulation between the primary circuit 133 and the secondary circuit 137 in the isolated integrated circuit 13 in response to system requirements. Accordingly, the operating voltage of the primary circuit 133 (i.e., the primary power supply voltage VCC and the primary ground voltage GND) may be different from the operating voltage of the secondary circuit 137 (i.e., the secondary power supply voltage VDD1 and the secondary ground voltage VEE1). Specifically, the isolation circuit 135 may be implemented by a passive element (e.g., a capacitor 351) or an insulating element (e.g., a transformer).

[0037] In some embodiments, while ensuring voltage isolation between the primary side circuit 133 and the secondary side circuit 137 (i.e., the aforementioned electrical insulation), the isolation circuit 135 is also used as a communication interface between the primary side circuit 133 and the secondary side circuit 137 to allow data, signals and / or information to be transmitted from the primary side circuit 133 to the secondary side circuit 137 through, for example, voltage coupling phenomenon.

[0038] In some embodiments, the secondary side circuit 137 includes a control logic circuit 371, an amplifier circuit 373, a receiving circuit 375, and an under-voltage lockout circuit 377. Figure 2 As shown, the receiving circuit 375 is coupled to the isolation circuit 135, the undervoltage lockout circuit 377 and the control logic circuit 371. The amplifier circuit 373 is coupled to the control logic circuit 371, the secondary power supply terminal P35 and the signal output terminal P36. In addition, the undervoltage lockout circuit 377 is coupled to the receiving circuit 375 and the secondary power supply terminal P35.

[0039] In some embodiments, the receiving circuit 375 includes a buffer gate G2 and an AND gate G3. The buffer gate G2 is coupled to the isolation circuit 135 and the first input terminal of the AND gate G3, the undervoltage lockout circuit 377 is coupled to the second input terminal of the AND gate G3, and the control logic circuit 371 is coupled to the output terminal of the AND gate G3.

[0040] In some embodiments, the amplifier circuit 373 includes a reverse gate G4, a buffer gate G5, a transistor M1, a transistor M2, a transistor M3, and a resistor R1. The first data output terminal of the control logic circuit 371 is directly coupled to the control terminal (e.g., gate terminal) of the transistor M1, and is coupled to the control terminal of the transistor M2 through the reverse gate G4. The second data output terminal of the control logic circuit 371 is coupled to the control terminal of the transistor M3 through the buffer gate G5. The first terminal (e.g., source terminal) of the transistor M1, the second terminal (e.g., drain terminal) of the transistor M2, and the second terminal of the transistor M3 are all coupled to the signal output terminal P36. The second terminal of the transistor M1 and the first terminal of the transistor M2 are both coupled to the secondary power supply terminal P35. The first terminal of the transistor M3 is grounded, and the resistor R1 is coupled between the signal output terminal P36 and the control terminal of the transistor M3.

[0041] In some embodiments, the resistor RDT in the voltage drop generating circuit 311 is coupled between the alternative terminal P37 and the secondary side ground terminal P38. The current generating circuit ICS in the voltage drop generating circuit 311 is coupled to the secondary side power supply terminal P35 to receive the secondary side power supply voltage VDD1. The current generating circuit ICS is also coupled to the resistor RDT via the alternative terminal P37. In some further embodiments, Figure 2 As shown, the resistor RDT in the signal delay setting circuit 131 is configured outside the isolated integrated circuit 13 , while the current generating circuit ICS, the delay time calculating circuit 313 and the signal delay circuit 315 in the signal delay setting circuit 131 are configured inside the isolated integrated circuit 13 .

[0042] In the embodiment where the delay time calculation circuit 313 and the signal delay circuit 315 are configured inside the isolated integrated circuit 13, Figure 2 As shown, the delay time calculation circuit 313 and the signal delay circuit 315 can be integrated into the control logic circuit 371 of the secondary side circuit 137, and the voltage drop generating circuit 311 can be coupled to the control logic circuit 371 through the buffer gate G1, thereby being coupled to the delay time calculation circuit 313. From the above description of the signal delay setting circuit 131 and the secondary side circuit 137, it can be known that the signal delay setting circuit 131 is coupled to the secondary side circuit 137, the alternative terminal P37 and the secondary side ground terminal P38.

[0043] At Figure 2 In the embodiment of the present invention, since the current generating circuit ICS and the resistor element RDT are equivalent to being coupled in series between the secondary power supply terminal P35 and the secondary ground terminal P38, a current path is formed between the secondary power supply voltage VDD1 and the secondary ground voltage VEE1. Specifically, the current path includes the secondary power supply terminal P35, the current generating circuit ICS, the replaceable terminal P37, the resistor element RDT and the secondary ground terminal P38.

[0044] In some embodiments, the primary power voltage VCC and the secondary power voltage VDD1 start to rise from 0 V. After the primary power voltage VCC and the secondary power voltage VDD1 rise to a power-on reset voltage POR (e.g., 1.2-1.8 V), the isolated integrated circuit 13 will be initialized to a preset state to facilitate logic operations in the isolated integrated circuit 13.

[0045] Following the embodiment in which the secondary power supply voltage VDD1 exceeds the power-on reset voltage POR, in some embodiments, the current generating circuit ICS generates a detection current Id according to the secondary power supply voltage VDD1 exceeding the power-on reset voltage POR, wherein the detection current Id may be a constant current. Through the aforementioned current path, the detection current Id will sequentially flow through the secondary power supply terminal P35, the current generating circuit ICS, the alternative terminal P37 and the resistor element RDT, and flow to the secondary ground terminal P38. It can be known from Ohm's law that the detection current Id flows through the resistor element RDT, which will cause a voltage difference VDT to be generated at both ends of the resistor element RDT (i.e., the alternative terminal P37 and the secondary ground terminal P38).

[0046] See also Figure 3 , Figure 3 FIG. 1 is a circuit block diagram of a control logic circuit 371, an amplifier circuit 373, a receiving circuit 375, a buffer gate G1, and a voltage drop generating circuit 311 according to some embodiments of the present disclosure. In some embodiments, the voltage difference VDT generated by the voltage drop generating circuit 311 can be transmitted to the control logic circuit 371 through the buffer gate G1 in the form of a voltage signal. In the embodiment where the delay time calculation circuit 313 and the signal delay circuit 315 are integrated into the control logic circuit 371, as shown in FIG. Figure 3 As shown, the delay time calculation circuit 313 is coupled to the voltage drop generation circuit 311 through the buffer gate G1 , and the signal delay circuit 315 is coupled to the delay time calculation circuit 313 , the receiving circuit 375 and the amplifying circuit 373 .

[0047] In some embodiments, the delay time calculation circuit 313 is used to calculate the delay time DT according to the voltage difference VDT. To further explain, the voltage difference VDT can be converted into a detection voltage value by the delay time calculation circuit 313 (or the control logic circuit 371). Specifically, the aforementioned detection voltage value is the current value of the detection current Id (e.g., 0.1 to 100 microamperes (μA)) multiplied by the resistance value of the resistor RDT (e.g., 1 to 500 kiloohms (kΩ)).

[0048] Following the embodiment of converting the voltage difference VDT into a detection voltage value, the control logic circuit 371 can pre-store a lookup table (not shown) through one or more storage circuits (e.g., memory), wherein the lookup table records multiple voltage values ​​and corresponding multiple durations. Therefore, the delay time calculation circuit 313 can find the voltage value that is the same as the detection voltage value among the multiple voltage values ​​by comparing the multiple voltage values ​​in the lookup table with the detection voltage value, and use the duration corresponding to the voltage value as the delay time DT. It should be understood that in the case where the voltage value that is the same as the detection voltage value is not found from the multiple voltage values, the delay time calculation circuit 313 can further calculate the delay time DT by (for example but not limited to) interpolation method.

[0049] The method of calculating the delay time DT is not limited to the above-mentioned embodiments. For example, in some embodiments, the delay time calculation circuit 313 calculates the delay time DT by substituting the detection voltage value into the following formula (1), wherein a and b can each be any pre-set numerical value, and VSEN represents the detection voltage value. It should be understood that the delay time calculation circuit 313 is not limited to using formula (1) to calculate the delay time DT, and any formula that can describe the relationship between the detection voltage value and the delay time DT can be used by the delay time calculation circuit 313 to calculate the delay time DT.

[0050] DT=a×VSEN+b…(1)

[0051] In some embodiments, such as Figure 3 As shown, after calculating the delay time DT, the delay time calculation circuit 313 provides the delay time DT to the signal delay circuit 315.

[0052] From the description of the voltage drop generating circuit 311 and the delay time calculating circuit 313, it can be seen that the signal delay setting circuit 131 of the present disclosure can detect the voltage difference VDT between the replaceable terminal P37 and the secondary side ground terminal P38 when the secondary side power supply voltage VDD1 exceeds the power-on reset voltage POR, and can generate a delay time DT according to the voltage difference VDT.

[0053] In some embodiments, after the primary power supply voltage VCC and the secondary power supply voltage VDD1 continue to rise and reach an undervoltage lockout voltage UVLO (e.g., 3, 5, 8 volts) greater than the power-on reset voltage POR, the isolated integrated circuit 13 then operates according to the first input signal IN+ and the second input signal IN-. Figure 2 to Figure 4 The operation of the isolated integrated circuit 13 according to the first input signal IN+ and the second input signal IN- is described. Figure 4FIG. 1 is a timing diagram of some signals related to the isolated integrated circuit 13 according to some embodiments of the present disclosure.

[0054] In some embodiments, such as Figure 2 As shown, after detecting that the primary side power supply voltage VCC exceeds the under-voltage lockout voltage UVLO, the under-voltage lockout circuit 337 in the primary side circuit 133 enables the logic control circuit 331. Thereafter, the primary side circuit 133 receives the first input signal IN+ from the first signal input terminal P32 through the buffer gate 333, and receives the second input signal IN- from the second signal input terminal P33 through the anti-gate 335.

[0055] At Figure 2 In the embodiment of the present invention, the buffer gate 333 buffers the first input signal IN+ and transmits it to the AND gate in the logic control circuit 331, and the inverting gate 335 inverts the second input signal IN- and transmits it to the AND gate in the logic control circuit 331. Moreover, the AND gate in the logic control circuit 331 generates the primary side signal SFP according to the first input signal IN+ and the inverted second input signal IN-. In some embodiments, the logic control circuit 331 can couple the primary side signal SFP to the isolation circuit 135 after selectively processing (e.g., buffering, amplifying, etc.) the primary side signal SFP.

[0056] In some embodiments, such as Figure 2 As shown, the isolation circuit 135 is used to convert the primary-side signal SFP received from the primary-side circuit 133 into a secondary-side signal SFS, and transmit the secondary-side signal SFS to the secondary-side circuit 137, so that the secondary-side circuit 137 generates an output signal OUT1 according to the secondary-side signal SFS. It can be seen that the secondary-side signal SFS is also equivalent to the signal generated by the isolation integrated circuit 13 according to the first input signal IN+ and the second input signal IN-.

[0057] In some embodiments, such as Figure 2 As shown, after detecting that the secondary side power supply voltage VDD1 exceeds the under-voltage lockout voltage UVLO, the under-voltage lockout circuit 377 in the secondary side circuit 137 enables the receiving circuit 375. In detail, the under-voltage lockout circuit 377 is used to output the enable signal SEN to the AND gate G3 in the receiving circuit 375 when the secondary side power supply voltage VDD1 exceeds the under-voltage lockout voltage UVLO. In addition, the buffer gate G2 in the receiving circuit 375 receives the secondary side signal SFS from the isolation circuit 135, and transmits the secondary side signal SFS to the AND gate G3 after buffering.

[0058] Depend on Figure 4 From the waveform of the secondary side signal SFS, it can be seen that the secondary side signal SFS is a periodic signal, and each period of the secondary side signal SFS has an enabling period (corresponding to an enabling level (for example: Figure 4The secondary side signal SFS) of the high voltage level in the middle) and the disable period (corresponding to the disable level (for example: Figure 4 In some embodiments, when the secondary power supply voltage VDD1 exceeds the under-voltage lockout voltage UVLO, the enable signal SEN is maintained at the enable level. Therefore, the AND gate G3 generates an enable level signal when the secondary signal SFS has the enable level, and generates a disable level signal when the secondary signal SFS has the disable level. This is equivalent to the receiving circuit 375 being enabled by the under-voltage lockout circuit 377, and transmitting the secondary signal SFS from the isolation circuit 135 to the control logic circuit 371.

[0059] When the secondary side signal SFS is transmitted to the control logic circuit 371 through the receiving circuit 375, as shown in FIG. Figure 3 As shown, the signal delay circuit 315 delays the secondary side signal SFS according to the delay time DT to output the delayed secondary side signal SFSD (ie, the delayed secondary side signal SFS) to the amplifier circuit 373. In some further embodiments, as Figure 4 As shown, the signal delay circuit 315 delays the rising edge RE of the secondary side signal SFS according to the delay time DT to generate the delayed secondary side signal SFSD. Figure 4 In the embodiment, the rising edge DRE of the delayed secondary signal SFSD will lag behind the rising edge RE of the secondary signal SFS by about the delay time DT. In this embodiment, the signal delay circuit 315 can be a digital circuit, which is convenient for delaying only the rising edge RE of the secondary signal SFS, but the present invention is not limited thereto. In addition, in some variations of the present invention, the signal delay circuit 315 can be changed to delay the falling edge of the secondary signal SFS, which can also achieve the same effect.

[0060] In addition, if Figure 2 As shown, the control logic circuit 371 is further used to invert the delayed secondary signal SFSD to output the inverted delayed secondary signal SFSD′ to the amplifier circuit 373. As can be seen from the above description, the control logic circuit 371 simultaneously outputs the delayed secondary signal SFSD and the inverted delayed secondary signal SFSD′ to the amplifier circuit 373.

[0061] In some embodiments, such as Figure 2 or Figure 3 As shown, the amplifier circuit 373 generates the output signal OUT1 according to the delayed secondary signal SFSD and the inverted delayed secondary signal SFSD'. Specifically, the transistors M1 and M3 can be implemented by N-type metal oxide semiconductor transistors, and the transistor M2 can be implemented by P-type metal oxide semiconductor transistors.

[0062] The delayed secondary side signal SFSD has the following Figure 4 In the case of a high voltage level as shown (i.e., the inverted delayed secondary-side signal SFSD' has a low voltage level), the control end of the transistor M1 directly receives the delayed secondary-side signal SFSD of the high voltage level, so that the transistor M1 is turned on. The inverting gate G4 inverts the delayed secondary-side signal SFSD of the high voltage level to generate a delayed secondary-side signal SFSD of the low voltage level to the control end of the transistor M2, so that the transistor M2 is turned on. The buffer gate G5 buffers the inverted delayed secondary-side signal SFSD' of the low voltage level to generate the inverted delayed secondary-side signal SFSD' of the low voltage level to the control end of the transistor M3, so that the transistor M3 is turned off. Accordingly, the secondary-side power supply voltage VDD1 is transmitted to the signal output end P36 through the turned-on transistors M1 and M2 to serve as the output signal OUT1 during its enabling period DTEN1 (such as Figure 4 ), (ie, the enabling level of the output signal OUT1).

[0063] When the delayed secondary-side signal SFSD has a low voltage level (at this time, the inverted delayed secondary-side signal SFSD' has a high voltage level), the control end of the transistor M1 directly receives the delayed secondary-side signal SFSD of the low voltage level, so that the transistor M1 is turned off. The reverse gate G4 inverts the delayed secondary-side signal SFSD of the low voltage level to generate a delayed secondary-side signal SFSD of the high voltage level to the control end of the transistor M2, so that the transistor M2 is turned off. The buffer gate G5 buffers the inverted delayed secondary-side signal SFSD' of the high voltage level to generate the inverted delayed secondary-side signal SFSD' of the high voltage level to the control end of the transistor M3, so that the transistor M3 is turned on. Accordingly, the signal output terminal P36 is grounded through the turned-on transistor M3 to serve as the output signal OUT1 during its disable period DTDE1 (such as Figure 4 ) (ie, the disable level of the output signal OUT1).

[0064] As can be seen from the above description of the amplifier circuit 373, the waveform of the output signal OUT1 is the same as the waveform of the delayed secondary-side signal SFSD in frequency and / or period (eg Figure 4 ), but the amplitude is different. Specifically, the amplitude of the output signal OUT1 is greater than the amplitude of the delayed secondary-side signal SFSD. That is, in some embodiments, the amplifier circuit 373 is used to amplify the delayed secondary-side signal SFSD to generate the output signal OUT1.

[0065] again, Figure 4The thick dashed lines in FIG. 1 also indicate waveforms of multiple signals that the secondary circuit 137 should have when the secondary signal SFS is not delayed in the secondary circuit 137 of the isolated integrated circuit 13. In this case, each cycle of the signal output by the isolated integrated circuit 13 through the signal output terminal P36 has an enable period TEN1 and a disable period TDE1. Figure 4 It can be seen that compared with the signal output when the secondary side signal SFS is not delayed in the secondary side circuit 137, the Figure 2 The output signal OUT1 generated by the circuit architecture has a lower duty cycle (ie, the enable period DTEN1 divided by the period of the output signal OUT1). The aforementioned “lower duty cycle” can avoid Figure 1 The high-side switch 17 and the low-side switch 19 are turned on at the same time, which will be discussed in the following paragraphs. Figure 6 Detailed description.

[0066] See also Figure 5 , Figure 5 1 is a timing diagram of some signals related to the isolated integrated circuit 15 according to some embodiments of the present disclosure. It should be understood that Figure 1 The isolated integrated circuit 15 in the embodiment can be used with Figure 2 The isolated integrated circuit 13 in the embodiment has the same or similar circuit structure, so the detailed description of the isolated integrated circuit 15 is omitted here.

[0067] like Figure 1 As shown, the difference between the isolated integrated circuit 15 and the isolated integrated circuit 13 is that the isolated integrated circuit 15 receives the second input signal IN- through the first signal input terminal P52, and receives the first input signal IN+ through the second signal input terminal P53. In this case, the waveform of the output signal OUT2 generated by the isolated integrated circuit 15 is as follows: Figure 5 Each cycle of the output signal OUT2 has an enable period DTEN2 (corresponding to the output signal OUT2 at the enable level) and a disable period DTDE2 (corresponding to the output signal OUT2 at the disable level).

[0068] also, Figure 5 The thick dashed line in FIG. 1 also shows the waveform of the signal output by the isolated integrated circuit 15 when the secondary-side signal is not delayed in the secondary-side circuit of the isolated integrated circuit 15. In this case, each cycle of the signal output by the isolated integrated circuit 15 has an enable period TEN2 and a disable period TDE2. Figure 5It can be seen that, compared with the signal output without delaying the secondary side signal in the secondary side circuit of the isolated integrated circuit 15, the output signal OUT2 generated when the secondary side signal is delayed in the secondary side circuit of the isolated integrated circuit 15 has a lower duty cycle (i.e., the enable period DTEN2 divided by the period of the output signal OUT2). The aforementioned “lower duty cycle” can prevent the high-side switch 17 and the low-side switch 19 from being turned on at the same time, which will be discussed in the following paragraphs. Figure 6 Detailed description.

[0069] In the above embodiment, Figure 1 The high-side switch 17 is based on the output signal OUT1 (corresponding to the enable level) Figure 4 The enable period DTEN1) is turned on and the output signal OUT1 (corresponding to the disable level) Figure 4 During the disable period, DTDE1 is turned off. Figure 1 The low-side switch 19 is based on the output signal OUT2 (corresponding to the enable level) Figure 5 The enable period DTEN2) is turned on and the output signal OUT2 (corresponding to the disable level) Figure 5 DTDE2) is turned off during the disable period.

[0070] Then match Figure 6 To further explain the relationship between the output signal OUT1 and the output signal OUT2, Figure 6 1 is a timing diagram of the output signal OUT1 and the output signal OUT2 according to some embodiments of the present disclosure. As can be seen from the above description, the signal delay setting circuit 131 controls the isolated integrated circuit 13 to generate the output signal OUT1 with a lower duty cycle, and the signal delay setting circuit 151 controls the isolated integrated circuit 15 to generate the output signal OUT2 with a lower duty cycle. Figure 6 As shown, the high-side switch 17 is turned on during the period QON1 (corresponding to the enable period DTEN1 of the output signal OUT1), and the low-side switch 19 is turned on during the period QON2 (corresponding to the enable period DTEN2 of the output signal OUT2). The period QON1 and the period QON2 do not overlap, which means that the high-side switch 17 and the low-side switch 19 are not turned on at the same time. The period DZ between the period QON1 and the period QON2 is usually called a dead zone or dead time.

[0071] It can be seen from the above description that when the secondary side power supply voltage VDD1 exceeds the power-on reset voltage POR, the signal delay setting circuit 131 of the present disclosure can generate a delay time DT according to the voltage difference VDT between the replaceable terminal P37 and the secondary side ground terminal P38. In addition, when the secondary side power supply voltage VDD1 exceeds the under-voltage lockout voltage UVLO, the signal delay setting circuit 131 of the present disclosure can delay the secondary side signal SFS according to the delay time DT to control the duty cycle of the output signal OUT1. It should be understood that the description of the above signal delay setting circuit 131 is also applicable to the signal delay setting circuit 151 in the isolated integrated circuit 15, so the description of the signal delay setting circuit 151 is omitted here. In some embodiments, the power-on reset voltage POR can be regarded as a preset voltage, and the under-voltage lockout voltage UVLO can be regarded as a protection voltage.

[0072] The voltage drop generating circuit 311, the delay time calculating circuit 313 and the signal delay circuit 315 in the signal delay setting circuit 131 are not limited to Figure 2 and Figure 3 The circuit architecture shown, any circuit architecture that can achieve the above-mentioned operations (for example, when the secondary side power supply voltage VDD1 exceeds the power-on reset voltage POR, a voltage difference VDT is generated between the alternative terminal P37 and the secondary side ground terminal P38, a delay time DT is generated according to the voltage difference VDT, the secondary side signal SFS is delayed according to the delay time DT, etc.) can be used to implement the signal delay setting circuit 131.

[0073] It should be understood that the operation of the control logic circuit 371 and the amplifier circuit 373 is not limited to Figure 2 In some embodiments, the buffer gate G5 in the amplifier circuit 373 is replaced by another anti-gate, and a data output terminal of the control logic circuit 371 is directly coupled to the control terminal of the transistor M1, coupled to the control terminal of the transistor M2 through the anti-gate G4, and coupled to the control terminal of the transistor M3 through the other anti-gate. During operation, the control logic circuit 371 can output the delayed secondary side signal SFSD to the control terminal of the transistor M1, the anti-gate G4 and the other anti-gate through the one data output terminal, so that the amplifier circuit 373 amplifies the delayed secondary side signal SFSD to generate the output signal OUT1.

[0074] It should be understood that the operations of the primary side circuit 133, the isolation circuit 135, and the secondary side circuit 137 are not limited to the above-mentioned embodiments. In some embodiments, the logic control circuit 331 modulates the primary side signal SFP according to the baseband signal provided by the oscillator through a modulator to generate a primary side modulated signal. The isolation circuit 135 converts the primary side modulated signal into a secondary side modulated signal and outputs the secondary side modulated signal to the secondary side circuit 137. The secondary side circuit 137 may also include a demodulator, and the demodulator may demodulate the secondary side modulated signal to generate a signal substantially the same as the secondary side signal SFS to the receiving circuit 375.

[0075] As can be seen from the above-mentioned implementation of the present disclosure, the duty cycle of the output signal OUT1 generated by the isolated integrated circuit 13 and the duty cycle of the output signal OUT2 generated by the isolated integrated circuit 15 are controlled by the signal delay setting circuit 131 and the signal delay setting circuit 151 respectively. The power conversion circuit system 100 of the present disclosure can effectively generate dead time to prevent the high-side switch 17 and the low-side switch 19 from being turned on at the same time, so as to achieve the effect of protecting the high-side switch 17 and the low-side switch 19. In addition, compared with some related technologies that generate dead time by using resistor-capacitor circuit settings or using trimming methods, the isolated integrated circuit 13, the isolated integrated circuit 15 and the power conversion circuit system 100 of the present disclosure have the advantages of low deviation, high reliability, and small circuit area requirements.

[0076] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0077]

Explanation of symbols

[0078] 11: Controller circuit

[0079] 13,15:Isolated integrated circuits

[0080] 17: High-side switch

[0081] 19: Low-side switch

[0082] 100: Power conversion circuit system

[0083] 131,151:Signal delay setting circuit

[0084] 133: Primary circuit

[0085] 135: Isolation circuit

[0086] 137: Secondary circuit

[0087] 311: Voltage drop generating circuit

[0088] 313: Delay time calculation circuit

[0089] 315:Signal delay circuit

[0090] 331:Logic control circuit

[0091] 333,G1,G2,G5: Buffer gate

[0092] 335,G4:Reverse Gate

[0093] 337,377: Undervoltage lockout circuit

[0094] 351:Capacitor

[0095] 371: Control logic circuit

[0096] 373: Amplifier Circuit

[0097] 375: Receiving circuit

[0098] DT: Delay time

[0099] G3: and gate

[0100] GND: primary side ground voltage

[0101] HVDC: Third supply voltage

[0102] ICS: Current generating circuit

[0103] Id: Detection current

[0104] IN+: First input signal

[0105] IN-: Second input signal

[0106] M1, M2, M3: transistors

[0107] OUT1, OUT2: output signal

[0108] P31, P51: primary power supply terminal

[0109] P32, P52: First signal input terminal

[0110] P33, P53: Second signal input terminal

[0111] P34, P54: primary side grounding terminal

[0112] P35, P55: Secondary power supply terminal

[0113] P36, P56: signal output terminal

[0114] P37, P57: Alternative end

[0115] P38, P58: Secondary side grounding terminal

[0116] POR: Power-on reset voltage

[0117] QON1,QON2,DZ: Period

[0118] R1: Resistor

[0119] RDT: Resistor

[0120] RE,DRE: rising edge

[0121] SEN: Enable signal

[0122] SFP: primary side signal

[0123] SFS: Secondary side signal

[0124] SFSD: Delayed secondary signal

[0125] SFSD': Inverted delayed secondary signal

[0126] TDE1, TDE2, DTDE1, DTDE2: Disable period

[0127] TEN1, TEN2, DTEN1, DTEN2: Enable period

[0128] UVLO: Under Voltage Lockout Voltage

[0129] VCC: primary side power supply voltage

[0130] VDD1, VDD2: Secondary side power supply voltage

[0131] VDT: Voltage difference

[0132] VEE1, VEE2: Secondary side ground voltage.

Claims

1. A signal delay setting circuit, suitable for an isolated integrated circuit, characterized in that: The isolated integrated circuit comprises a primary side circuit, an isolation circuit and a secondary side circuit, wherein the secondary side circuit is coupled to a replaceable terminal and a secondary side ground terminal of the isolated integrated circuit, the isolation circuit is used to convert a primary side signal from the primary side circuit into a secondary side signal, and the signal delay setting circuit comprises: A voltage drop generating circuit is coupled to the replaceable end and the secondary side ground end and is used to generate a voltage difference between the replaceable end and the secondary side ground end; A delay time calculation circuit is coupled to the voltage drop generation circuit and is used to calculate the delay time according to the voltage difference; as well as A signal delay circuit is coupled to the delay time calculation circuit, and is used to delay the secondary side signal received by the secondary side circuit from the isolation circuit according to the delay time, so as to control the duty cycle of the output signal generated by the secondary side circuit according to the secondary side signal, wherein the primary side signal is generated by the primary side circuit according to the first input signal and the second input signal.

2. The signal delay setting circuit according to claim 1, characterized in that: The voltage drop generating circuit comprises: A resistor element coupled between the replaceable terminal and the secondary side ground terminal; as well as The current generating circuit is coupled to the resistor element at the replaceable end, and is used to receive the secondary side power supply voltage provided to the secondary side circuit, and is used to output a detection current flowing through the resistor element according to the secondary side power supply voltage, so that the voltage difference is generated between the replaceable end and the secondary side ground end.

3. The signal delay setting circuit according to claim 2, characterized in that: The resistor element is arranged outside the isolated integrated circuit, and the current generating circuit is arranged inside the isolated integrated circuit.

4. The signal delay setting circuit according to claim 1, characterized in that: The delay time calculation circuit and the signal delay circuit are integrated into the control logic circuit of the secondary side circuit, and the voltage drop generating circuit is coupled to the control logic circuit through a buffer gate.

5. The signal delay setting circuit according to claim 1, characterized in that: The signal delay circuit is used for delaying a plurality of rising edges of the secondary side signal by the delay time.

6. The signal delay setting circuit according to claim 1, characterized in that: The delay time calculation circuit calculates the delay time according to the voltage difference by using a table lookup or formula calculation method.

7. The signal delay setting circuit according to claim 1, characterized in that: The secondary side circuit is used for receiving the secondary side power supply voltage through the secondary side power supply terminal of the isolation type integrated circuit, and the voltage drop generating circuit is used for generating the voltage difference when the secondary side power supply voltage exceeds the power-on reset voltage.

8. The signal delay setting circuit according to claim 7, characterized in that: The signal delay circuit is used for delaying the secondary side signal according to the delay time when the secondary side power supply voltage exceeds the under-voltage lockout voltage, wherein the under-voltage lockout voltage is greater than the power-on reset voltage.

9. An isolated integrated circuit, characterized in that: Include: A primary side circuit, used for receiving a first input signal and a second input signal, and for generating a primary side signal according to the first input signal and the second input signal; An isolation circuit, coupled to the primary side circuit, and used to convert the primary side signal into a secondary side signal; A secondary side circuit, coupled to the isolation circuit, for receiving the secondary side signal through the isolation circuit, for generating an output signal according to the secondary side signal, and for receiving a secondary side power supply voltage; as well as A signal delay setting circuit is coupled to the replaceable end and the secondary ground end of the secondary circuit and the isolated integrated circuit, and is used to detect the voltage difference between the replaceable end and the secondary ground end when the secondary power supply voltage exceeds a preset voltage, to calculate a delay time based on the voltage difference, and to delay the secondary signal based on the delay time to control the duty cycle of the output signal.

10. A power conversion circuit system, characterized in that: Include: High-side switch; Low-side switch; A controller circuit, configured to output a first input signal and a second input signal; A first isolated integrated circuit is coupled between the controller circuit and the high-side switch, and comprises a first signal delay setting circuit, a first signal input terminal, a second signal input terminal, a first replaceable terminal and a first secondary side ground terminal, wherein the first isolated integrated circuit is used to receive the first input signal through the first signal input terminal, and is used to receive the second input signal through the second signal input terminal to generate a first output signal for driving the high-side switch; as well as A second isolated integrated circuit is coupled between the controller circuit and the low-side switch, and comprises a second signal delay setting circuit, a third signal input terminal, a fourth signal input terminal, a second replaceable terminal and a second secondary side ground terminal, wherein the second isolated integrated circuit is used to receive the second input signal through the third signal input terminal, and is used to receive the first input signal through the fourth signal input terminal to generate a second output signal for driving the low-side switch; Wherein, when the first secondary-side power supply voltage received by the first isolated integrated circuit and the second secondary-side power supply voltage received by the second isolated integrated circuit exceed a preset voltage, the first signal delay setting circuit calculates a first delay time according to a first voltage difference between the first replaceable terminal and the first secondary-side ground terminal, and the second signal delay setting circuit calculates a second delay time according to a second voltage difference between the second replaceable terminal and the second secondary-side ground terminal; When the first secondary-side power supply voltage and the second secondary-side power supply voltage exceed a protection voltage greater than the preset voltage, the first signal delay setting circuit delays the first secondary-side signal generated by the first isolated integrated circuit according to the first input signal and the second input signal according to the first delay time to control the duty cycle of the first output signal, and the second signal delay setting circuit delays the second secondary-side signal generated by the second isolated integrated circuit according to the first input signal and the second input signal according to the second delay time to control the duty cycle of the second output signal, so that the high-side switch and the low-side switch will not be turned on at the same time.

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