A novel high-isolation and low-insertion-loss switch matrix chip

Abstract

The present invention discloses a novel high-isolation, low-insertion-loss switch matrix chip, comprising a switch matrix circuit disposed on a gallium arsenide (GaAs) pHEMT (Phe) semiconductor circuit layer. The switch matrix circuit comprises m input terminals, m switch structures, a vertical transition structure, n power dividers, and n output terminals. The vertical transition structure is configured as a coplanar waveguide. The input terminals are electrically connected to the signal input terminals of the switch structures, the signal output terminals of the switch structures are electrically connected to the vertical transition structure and the signal input terminals of the power dividers, the signal output terminals of the vertical transition structure are electrically connected to the signal input terminals of the power dividers, and the signal output terminals of the power dividers are electrically connected to the output terminals. A highly integrated switch matrix chip is achieved using a GaAs pHEMT process. The switch matrix chip integrates multiple switches and power dividers, along with a high-isolation vertical transition structure, achieving high isolation and low loss.

Description

Technical Field

[0001] The present invention relates to the field of microwave radio frequency technology, and in particular to a novel high-isolation and low-insertion-loss switch matrix chip. Background Art

[0002] Currently, RF signals are switched on and off by controlling the opening and closing of switching tubes. More complex switch matrices can achieve complex routing through a combination of single-pole single-throw, single-pole double-throw, and power divider circuits. In various systems such as communications, electronic warfare, and radar, switch matrices are used to connect different RF functional units. By opening and closing them, the flow of RF signals is controlled and changed, allowing the same RF front-end to meet different application requirements, reducing system development costs, shortening development time, and simplifying the development process. The advantage of existing technologies is that the required routing functions can be achieved through the combination of chips such as switches and power dividers, without the need for additional chip development. The disadvantages are low integration, high cost, and unfavorable miniaturization and low cost. Summary of the Invention

[0003] In order to solve the problems faced by the above-mentioned switch matrix, the present invention proposes a new type of high-isolation and low-insertion-loss switch matrix chip, which adopts gallium arsenide pHEMT process to realize a highly integrated switch matrix chip. The switch matrix chip integrates multiple switches and power dividers, and integrates a high-isolation vertical transition structure to achieve high isolation and low loss functions.

[0004] The technical solution adopted in the present invention is as follows:

[0005] A novel high-isolation, low-insertion-loss switch matrix chip includes a switch matrix circuit arranged on a gallium arsenide PHEMT semiconductor circuit layer. The switch matrix circuit includes m input terminals, m switch structures, a vertical transition structure, n power dividers, and n output terminals. The vertical transition structure is arranged in the form of a coplanar waveguide structure. The input terminal is electrically connected to the signal input terminal of the switch structure, the signal output terminal of the switch structure is electrically connected to the vertical transition structure and the signal input terminal of the power divider, the signal output terminal of the vertical transition structure is electrically connected to the signal input terminal of the power divider, and the signal output terminal of the power divider is electrically connected to the output terminal.

[0006] Furthermore, the gallium arsenide PHEMT semiconductor circuit layer includes a gallium arsenide layer, a first metal layer, a thin film resistor layer, a silicon nitride dielectric layer, a polyimide dielectric layer and a second metal layer. The gallium arsenide layer is arranged at the bottom, and the silicon nitride dielectric layer and the polyimide dielectric layer are sequentially arranged on the gallium arsenide layer as capacitor dielectrics. The first metal layer is arranged between the gallium arsenide layer and the silicon nitride dielectric layer as a capacitor lower electrode. The second metal layer is arranged on the polyimide dielectric layer as a capacitor upper electrode and extends downward through a second via layer to be directly connected to the polyimide dielectric layer. The first metal layer, the silicon nitride dielectric layer, the second via layer and the second metal layer together constitute a MIM capacitor; the thin film resistor layer is arranged between the gallium arsenide layer and the silicon nitride dielectric layer to make a gate isolation resistor for the pHEMT tube.

[0007] Furthermore, the first metal layer, the silicon nitride dielectric layer, the polyimide dielectric layer and the second metal layer can be used to manufacture a microstrip transmission line and cross wiring thereof.

[0008] Furthermore, the first metal layer, the silicon nitride dielectric layer, the polyimide dielectric layer and the second metal layer can be used to manufacture a coplanar waveguide.

[0009] Furthermore, the first metal layer is connected to the second metal layer through a first via layer and a second via layer in sequence.

[0010] Furthermore, the first metal layer is grounded through a third via layer.

[0011] Furthermore, the GaAs PHEMT semiconductor circuit layer further includes a passivation layer, and the passivation layer is disposed on the polyimide dielectric layer.

[0012] Furthermore, the passivation layer is made of silicon dioxide.

[0013] Furthermore, the switch structure includes a single-pole single-throw switch and a single-pole double-throw switch.

[0014] Furthermore, the insertion loss and phase of the single-pole single-throw switch and the single-pole double-throw switch are the same.

[0015] The beneficial effects of the present invention are:

[0016] (1) A novel high-isolation, low-insertion-loss switch matrix chip of the present invention can realize the functions of multiple single-function chips, greatly improving the integration level;

[0017] (2) A new vertical transition structure is used to improve the isolation between channels, and the simulated isolation reaches 50dB;

[0018] (3) Reducing the chip area helps reduce the cost of the entire solution and improve product consistency. The cost and consistency advantages are obvious in large-scale use. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of a GaAs PHEMT semiconductor circuit layer according to an embodiment of the present invention.

[0020] Figure 2 Schematic diagram of the vertical transition structure of an embodiment of the present invention.

[0021] Figure 3 It is a principle block diagram of a switch matrix circuit according to an embodiment of the present invention.

[0022] Figure 4 This is a diagram showing the effect of the switch matrix circuit of an embodiment of the present invention (including insertion loss IL and isolation ISO, where RFin1, RFin2, RFin3, and RFin4 are input ends, and RFout1 is the output end). The simulation results are for the output end RFout1, and the effect of the output end RFout2 is the same.

[0023] Figure 5 Schematic diagram of the external structure of the switch matrix circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific embodiments of the present invention are now described. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. That is, the embodiments described are only part of the embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0025] This embodiment provides a novel high-isolation, low-insertion-loss switch matrix chip, comprising a switch matrix circuit disposed on a gallium arsenide (GaAs) PHEMT semiconductor circuit layer. The switch matrix circuit includes m input terminals, m switch structures, a vertical transition structure, n power dividers, and n output terminals. The vertical transition structure is configured as a coplanar waveguide structure. The input terminal is electrically connected to the signal input terminal of the switch structure, the signal output terminal of the switch structure is electrically connected to the signal input terminal of the vertical transition structure and the power divider, the signal output terminal of the vertical transition structure is electrically connected to the signal input terminal of the power divider, and the signal output terminal of the power divider is electrically connected to the output terminal. Preferably, the switch structure includes a single-pole single-throw (SPST) switch and a single-pole double-throw (SPDT) switch, and the insertion loss and phase of the SPST and SPDT switches should be identical.

[0026] like Figure 1As shown, the gallium arsenide PHEMT semiconductor circuit layer includes a gallium arsenide layer GaAs, a first metal layer M1, a thin film resistor layer RT, a silicon nitride dielectric layer SiN, a polyimide dielectric layer Polymide, and a second metal layer M2. The gallium arsenide layer GaAs is disposed at the bottom, and the silicon nitride dielectric layer SiN and the polyimide dielectric layer Polymide are sequentially disposed on the gallium arsenide layer GaAs as capacitor dielectrics. The silicon nitride dielectric layer SiN is relatively thin (e.g., 0.1 μm), and the polyimide dielectric layer Polymide is etched away at the capacitor location through the second via layer P1 to achieve metallization. The first metal layer M1 is disposed between the gallium arsenide layer GaAs and the silicon nitride dielectric layer SiN as the capacitor bottom electrode, and the second metal layer M2 is disposed on the polyimide dielectric layer Polymide as the capacitor top electrode. The first metal layer M1, the silicon nitride dielectric layer SiN, the second via layer P1, and the second metal layer M2 together constitute a MIM capacitor (metal-insulator-metal capacitor) to increase capacitance density.

[0027] Among them, PHEMT is an improved structure of the high electron mobility transistor (HEMT). Its basic device structure is n+-AlxGa1-xAs / i-InGaAs / i–GaAs type, and an undoped i–InGaAs layer is used as the channel layer.

[0028] Retaining the polyimide dielectric layer in the location where no capacitor is prepared, and directly using the first metal layer M1 and the second metal layer M2 at different heights can also achieve cross wiring between transmission lines, but the isolation of direct cross wiring can only reach 35dB, making it difficult to achieve high isolation indicators. Therefore, the cross microstrip line is converted to a CPW (coplanar waveguide) structure. The coupling capacitance between the cross lines of the CPW structure is reduced to 1 / 25 of the microstrip line structure, and a large area of ground is connected on all sides. By optimizing the grounding shape and line width, the cross line isolation can be increased to 50dB. The specific structure is as follows: Figure 2 The first metal layer M1 is connected to the second metal layer M2 through the first via layer V1 and the second via layer P1 in sequence, and the first metal layer M1 is grounded through the third via layer.

[0029] The thin-film resistor layer RT, located between the gallium arsenide (GaAs) layer and the silicon nitride (SiN) dielectric layer, forms the pHEMT transistor's gate isolation resistor, improving isolation between channels. Considering switching speed, this isolation resistor is typically in the 1.5 kilo-ohm range, enabling switching speeds of 10 nanoseconds.

[0030] Preferably, the second metal layer M2 can be thickened to 4 μm to reduce RF trace loss. The insertion loss and phase consistency between different channels can be achieved by strictly controlling the electrical length of each channel switch transmission line and the size of the series and parallel tubes.

[0031] Preferably, the GaAs PHEMT semiconductor circuit layer further includes a passivation layer disposed on the polyimide dielectric layer to protect the upper surface of the entire chip, preventing burnout and long-term reliability caused by excess material. Specifically, the passivation layer can be made of silicon dioxide.

[0032] The above-mentioned GaAs PHEMT semiconductor circuit layer can realize basic components such as capacitors, resistors, transmission lines, grounding holes and pads, realize power division and vertical transition circuits, and realize switching circuits together with pHEMT tubes to form a switch matrix chip.

[0033] More specifically, if Figure 3 The figure shows the principle block diagram of a four-input, two-output switch matrix circuit operating at DC to 18GHz. It consists of two single-pole, single-throw switches fixed in the on state, two single-pole, double-throw switches, two two-way power dividers, and a high-isolation vertical transition structure. The switch matrix circuit is fabricated on the above-mentioned gallium arsenide PHEMT semiconductor circuit layer.

[0034] The SPST switch and SPDT switch maintain consistent insertion loss and phase, ensuring channel amplitude consistency and phase consistency. From DC to 18GHz, the in-band insertion loss is less than 1.5dB, and the isolation is greater than 50dB. The switch is connected to two power splitters, and the power splitter loss is 4.5dB. The overall insertion loss is shown in Figure 4 As shown in the figure, the isolation is the switch isolation plus the insertion loss of the power divider, reaching 54dBm.

[0035] like Figure 5 As shown, RFin1, RFin2, RFin3, and RFin4 are the four input terminals of the four-input and two-output module, RFout1 and RFout2 are the two output terminals, and the entire chip size is 4.2mm*3.6mm. The simulation results show a loss of 6dB and an isolation of 54dB.

[0036] It should be noted that the terms "center," "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are conventionally placed in the present invention when in use. They are intended solely to facilitate and simplify the description of the present invention, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third," etc., are used solely for distinction and description, and should not be construed as indicating or implying relative importance.

Claims

1. A new type of high isolation and low insertion loss switch matrix chip, characterized in that: The invention comprises a switch matrix circuit provided on a gallium arsenide PHEMT semiconductor circuit layer, the switch matrix circuit comprising m input terminals, m switch structures, a vertical transition structure, n power dividers, and n output terminals, wherein the vertical transition structure is provided in the form of a coplanar waveguide structure, the input terminal is electrically connected to the signal input terminal of the switch structure, the signal output terminal of the switch structure is electrically connected to the vertical transition structure and the signal input terminal of the power divider, the signal output terminal of the vertical transition structure is electrically connected to the signal input terminal of the power divider, and the signal output terminal of the power divider is electrically connected to the output terminal; The gallium arsenide PHEMT semiconductor circuit layer comprises a gallium arsenide layer (GaAs), a first metal layer (M1), a thin film resistor layer (RT), a silicon nitride dielectric layer (SiN), a polyimide dielectric layer (Polymide) and a second metal layer (M2), wherein the gallium arsenide layer (GaAs) is arranged at the bottom, the silicon nitride dielectric layer (SiN) and the polyimide dielectric layer (Polymide) are arranged in sequence on the gallium arsenide layer (GaAs), and the first metal layer (M1) is arranged as a capacitor bottom electrode between the gallium arsenide layer (GaAs) and the silicon nitride dielectric layer (SiN). The invention discloses a MIM capacitor comprising a first metal layer (M1), a second metal layer (M2), a silicon nitride dielectric layer (SiN), and a second metal layer (M2). The first metal layer (M1), the silicon nitride dielectric layer (SiN), the second via layer (P1), and the second metal layer (M2) are arranged between the gallium arsenide layer (GaAs) and the silicon nitride dielectric layer (SiN), the second metal layer (M2) is arranged as a capacitor upper electrode on the polyimide dielectric layer (Polymide), and is directly connected to the silicon nitride dielectric layer (SiN) by extending downward through the second via layer (P1). The first metal layer (M1), the silicon nitride dielectric layer (SiN), the second via layer (P1), and the second metal layer (M2) together constitute a MIM capacitor. The thin film resistor layer (RT) is arranged between the gallium arsenide layer (GaAs) and the silicon nitride dielectric layer (SiN) and is used to manufacture the gate isolation resistor of the pHEMT tube.

2. A novel high isolation and low insertion loss switch matrix chip according to claim 1, characterized in that: The first metal layer (M1), the silicon nitride dielectric layer (SiN), the polyimide dielectric layer (Polymide) and the second metal layer (M2) can be used to manufacture a microstrip transmission line and cross wiring thereof.

3. The novel high isolation and low insertion loss switch matrix chip according to claim 1, characterized in that: The first metal layer (M1), the silicon nitride dielectric layer (SiN), the polyimide dielectric layer (Polymide) and the second metal layer (M2) can be used to manufacture a coplanar waveguide.

4. The novel high isolation and low insertion loss switch matrix chip according to claim 1, characterized in that: The first metal layer (M1) is connected to the second metal layer (M2) through a first via layer (V1) and a second via layer (P1) in sequence.

5. The novel high isolation and low insertion loss switch matrix chip according to claim 1, characterized in that: The first metal layer (M1) is grounded through a third via layer.

6. The novel high isolation and low insertion loss switch matrix chip according to claim 1, characterized in that: The GaAs PHEMT semiconductor circuit layer further includes a passivation layer, which is disposed on the polyimide dielectric layer.

7. The novel high isolation and low insertion loss switch matrix chip according to claim 6, characterized in that: The passivation layer is made of silicon dioxide.

8. A novel high isolation and low insertion loss switch matrix chip according to any one of claims 1 to 7, characterized in that: The switch structure includes a single-pole single-throw switch and a single-pole double-throw switch.

9. The novel high isolation and low insertion loss switch matrix chip according to claim 8, characterized in that: The insertion loss and phase of the single-pole single-throw switch and the single-pole double-throw switch are the same.

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