Signal delay setting circuit, isolated integrated circuit and power conversion circuit system

Abstract

The invention provides a signal delay setting circuit, an isolated integrated circuit and a power conversion circuit system. The isolated integrated circuit receives a first power supply voltage, receives a first input signal and a second input signal through two signal input ends, and outputs an output signal generated according to the first input signal and the second input signal. When the first power supply voltage is within a preset voltage range, the signal delay setting circuit generates a voltage difference between the two signal input ends and calculates delay time according to the voltage difference. When the first power supply voltage is larger than the upper limit value of the preset voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time so as to control the duty ratio of the output signal. The duty ratio of the output signal of the isolated integrated circuit is controlled through the signal delay setting circuit, the power conversion circuit system effectively generates dead time to protect the high-side switch and the low-side switch, and the power conversion circuit system has the advantages of being low in deviation, high in reliability, small in circuit area requirement and the like.

Description

Technical Field

[0001] The present application relates to a signal delay setting circuit, and more particularly to a signal delay setting circuit applied to an isolated integrated circuit. Background Art

[0002] In a circuit structure composed of a high-side switch and a low-side switch, it is usually necessary to turn on the high-side switch and the low-side switch alternately to complete the operation. However, due to some non-ideal factors, the high-side switch and the low-side switch may be turned on at the same time, which may cause the high-side switch and the low-side switch to be damaged due to the large current flowing through them.

[0003] Some related technologies use a resistor-capacitor circuit (RC circuit) to set or use a trimming method to generate a dead zone or dead time to ensure that the high-side switch and the low-side switch are not turned on at the same time, but these related technologies each have their own problems. For example, the dead time generated by the related technology using a resistor-capacitor circuit may have a higher deviation due to the physical properties of the resistor and / or capacitor. For another example, the related technology using the trimming method may increase the complexity of the entire system. Therefore, it is necessary to propose a new method to solve the above problems. Summary of the invention

[0004] One aspect of the present application is a signal delay setting circuit suitable for an isolated integrated circuit. The isolated integrated circuit includes a first signal input terminal, a second signal input terminal and a signal output terminal, wherein the first signal input terminal is used to receive a first input signal, the second signal input terminal is used to receive a second input signal, and the signal output terminal is used to output an output signal generated according to the first input signal and the second input signal. The signal delay setting circuit includes a voltage drop generating circuit, a delay time control circuit and a signal delay circuit. The voltage drop generating circuit is used to generate a voltage difference between the first signal input terminal and the second signal input terminal. The delay time control circuit is coupled to the voltage drop generating circuit, and is used to enable the voltage drop generating circuit to generate a voltage difference when the first power supply voltage is within a preset voltage range, and is used to calculate the delay time according to the voltage difference, wherein the isolated integrated circuit also includes a first power supply terminal, and the first power supply terminal is used to receive the first power supply voltage. The signal delay circuit is coupled to the delay time control circuit, and is used to delay one of the first input signal and the second input signal according to the delay time when the first power supply voltage is greater than the upper limit value of the preset voltage range, so as to control the duty cycle of the output signal.

[0005] In some embodiments, the voltage drop generating circuit includes a current generating circuit, a resistor element, and a switch circuit. The current generating circuit is coupled to the first power supply terminal and is used to output a detection current. The resistor element is coupled between the first signal input terminal and the second signal input terminal. The switch circuit is coupled to the current generating circuit, the resistor element, and the first ground voltage, and is used to be turned on when the delay time control circuit enables the voltage drop generating circuit, so that the detection current flows through the resistor element, thereby generating the voltage difference at both ends of the resistor element.

[0006] In some embodiments, the resistor element is disposed outside the isolated integrated circuit, and the current generating circuit and the switch circuit are disposed inside the isolated integrated circuit.

[0007] In some embodiments, the switch circuit includes a first switch and a second switch. The first switch is coupled between the current generating circuit and the first signal input terminal. The second switch is coupled between the second signal input terminal and a first ground terminal of the isolated integrated circuit, wherein the first ground terminal is used to receive the first ground voltage.

[0008] In some embodiments, the delay time control circuit includes a voltage sensing circuit, a delay time calculation circuit, a switch driving circuit and a central control circuit. The voltage sensing circuit is used to sense the voltage difference between the first signal input terminal and the second signal input terminal to output a sensing voltage value corresponding to the voltage difference. The delay time calculation circuit is used to calculate the delay time according to the sensing voltage value to output the delay time to the signal delay circuit. The switch driving circuit is used to control the switch circuit in the voltage drop generating circuit to be turned on or off. The central control circuit is coupled to the voltage sensing circuit, the delay time calculation circuit and the switch driving circuit, and is used to control the voltage sensing circuit, the delay time calculation circuit and the switch driving circuit.

[0009] In some embodiments, the delay time control circuit further includes a storage circuit coupled to the voltage sensing circuit, the delay time calculation circuit and the central control circuit, and used to store the sensing voltage value to provide the sensing voltage value to the delay time calculation circuit.

[0010] In some embodiments, the signal delay circuit is coupled to the second signal input terminal and is used to delay a plurality of falling edges of the second input signal or a plurality of rising edges of the inverted second input signal by the delay time.

[0011] In some embodiments, the predetermined voltage range is between a power-on reset voltage and an under-voltage lockout voltage.

[0012] One aspect of the present application is an isolated integrated circuit. The isolated integrated circuit includes a primary side circuit, an isolation circuit, a secondary side circuit and a signal delay setting circuit. The primary side circuit is used to receive a first power supply voltage through a first power supply terminal, to receive a first input signal through a first signal input terminal, to receive a second input signal through a second signal input terminal, and to generate an intermediate signal according to the first input signal and the second input signal. The isolation circuit is coupled to the primary side circuit and is used to transmit the intermediate signal. The secondary side circuit is coupled to the isolation circuit, to receive the intermediate signal through the isolation circuit, and to output an output signal generated according to the intermediate signal through a signal output terminal. The signal delay setting circuit is coupled to the primary side circuit, and is used to calculate the delay time according to the voltage difference between the first signal input terminal and the second signal input terminal when the first power supply voltage is within a preset voltage range, and is used to delay one of the first input signal and the second input signal according to the delay time when the first power supply voltage is greater than the upper limit of the preset voltage range, so as to control the duty cycle of the output signal.

[0013] One aspect of the present application is a power conversion circuit system. The power conversion circuit system includes a high-side switch, a low-side switch, a controller circuit, a first isolated integrated circuit and a second isolated integrated circuit. The controller circuit is used to output a first input signal and a second input signal. The first isolated integrated circuit is coupled to the controller circuit and the high-side switch, and includes a first signal delay setting circuit for receiving a first input signal through a first signal input terminal, for receiving a second input signal through a second signal input terminal, and for generating a first output signal for driving the high-side switch according to the first input signal and the second input signal. The second isolated integrated circuit is coupled to the controller circuit and the low-side switch, and includes a second signal delay setting circuit for receiving a second input signal through a third signal input terminal, for receiving a first input signal through a fourth signal input terminal, and for generating a second output signal for driving the low-side switch according to the first input signal and the second input signal. When the first power supply voltage is within a preset voltage range, the first signal delay setting circuit calculates a first delay time according to a first voltage difference between the first signal input terminal and the second signal input terminal, and the second signal delay setting circuit calculates a second delay time according to a second voltage difference between the third signal input terminal and the fourth signal input terminal. When the first power supply voltage is greater than the upper limit value of the preset voltage range, the first signal delay setting circuit delays the second input signal according to the first delay time to control the duty cycle of the first output signal, and the second signal delay setting circuit delays the first input signal according to the second delay time to control the duty cycle of the second output signal, so that the high-side switch and the low-side switch will not be turned on at the same time.

[0014] In summary, by controlling the duty cycle of the output signal generated by the isolated integrated circuit through the signal delay setting circuit, the power conversion circuit system of the present application can effectively generate dead time to protect the high-side switch and the low-side switch. In addition, compared with some related technologies that generate dead time by using resistor and capacitor circuit settings or using trimming methods, the isolated integrated circuit and power conversion circuit system of the present application have the advantages of low deviation, high reliability, and small circuit area requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The invention is a circuit block diagram of a power conversion circuit system according to some embodiments of the present application.

[0016] Figure 2 The invention is a circuit diagram of an isolated integrated circuit according to some embodiments of the present application.

[0017] Figure 3 The invention is a circuit block diagram of a delay time control circuit according to some embodiments of the present application.

[0018] Figure 4 The figure is a signal timing diagram of an isolated integrated circuit according to some embodiments of the present application.

[0019] Figure 5 The figure is a signal timing diagram of an isolated integrated circuit according to some embodiments of the present application.

[0020] Figure 6 FIG. 1 is a timing diagram of output signals of two isolated integrated circuits according to some embodiments of the present application. DETAILED DESCRIPTION

[0021] The following embodiments are described in detail with reference to the accompanying drawings, but the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operation is not used to limit the order of its execution. Any structure recombined by the elements to produce a device with equal functions is within the scope of the present invention.

[0022] The terms used throughout the specification and claims generally have the ordinary meanings of each term used in the art, in the context of this disclosure, and in the specific context, unless otherwise noted.

[0023] As used herein, “coupled” or “connected” may refer to two or more elements being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other, or may refer to two or more elements operating or moving with each other.

[0024] See also Figure 1 , Figure 1FIG. 1 is a circuit block diagram of a power conversion circuit system 100 according to some embodiments of the present application. In some embodiments, the power conversion circuit system 100 includes a controller circuit 11, an isolated integrated circuit 13, an isolated integrated circuit 15, a high-side switch 17, and a low-side switch 19. Specifically, the power conversion circuit system 100 may be, for example but not limited to, a buck converter.

[0025] In some embodiments, Figure 1 As shown, the controller circuit 11 is electrically coupled to the isolated integrated circuit 13 and the isolated integrated circuit 15. The isolated integrated circuit 13 is electrically coupled to the high-side switch 17, and the second isolated integrated circuit 15 is electrically coupled to the low-side switch 19. In addition, the high-side switch 17 is connected in series with the low-side switch 19. It should be understood that in some embodiments, the connection node between the high-side switch 17 and the low-side switch 19 can be electrically coupled to a load circuit (not shown).

[0026] According to the circuit architecture of the power conversion circuit system 100, in some embodiments, the controller circuit 11 is used to output the first input signal IN+ and the second input signal IN- to the isolated integrated circuit 13 and the isolated integrated circuit 15, wherein the first input signal IN+ and the second input signal IN- can be inverted with each other. The isolated integrated circuit 13 is used to generate the output signal OUT1 to the high-side switch 17 according to the first input signal IN+ and the second input signal IN-. The isolated integrated circuit 15 is used to generate the output signal OUT2 to the low-side switch 19 according to the first input signal IN+ and the second input signal IN-. By driving the output signal OUT1 and the output signal OUT2, the high-side switch 17 and the low-side switch 19 will be turned on alternately to generate an output current (not shown) flowing through the aforementioned load circuit. In some embodiments, the first input signal IN+, the second input signal IN-, the output signal OUT1 and the output signal OUT2 are all periodic signals. In addition, the output signal OUT1 and the output signal OUT2 are also substantially inverted with each other, so that the high-side switch 17 and the low-side switch 19 can be driven to be turned on alternately.

[0027] In some embodiments, the isolated integrated circuit 13 includes a first power supply terminal P31, a first signal input terminal P32, a second signal input terminal P33, a first ground terminal P34, a second power supply terminal P35, a signal output terminal P36, an output / clamp terminal P37, and a second ground terminal P38. Figure 1As shown, the isolated integrated circuit 13 receives the first power supply voltage VCC1 through the first power supply terminal P31, receives the first input signal IN+ through the first signal input terminal P32, receives the second input signal IN- through the second signal input terminal P33, receives the first ground voltage GND1 through the first ground terminal P34, receives the second power supply voltage VDD1 through the second power supply terminal P35, outputs the aforementioned output signal OUT1 through the signal output terminal P36, and receives the second ground voltage VEE1 through the second ground terminal P38.

[0028] In some further embodiments, the output / clamp terminal P37 may be electrically coupled to the high-side switch 17, and the isolated integrated circuit 13 outputs a first level output signal (not shown) to the high-side switch 17 through the signal output terminal P36, or outputs a second level output signal (not shown) to the high-side switch 17 through the output / clamp terminal P37 as the output signal OUT1, that is, the signal output terminal P36 and the output / clamp terminal P37 are used together to control the high-side switch 17, wherein the first level output signal may have a low logic level, and the second level output signal may have a high logic level. In some other further embodiments, the isolated integrated circuit 13 outputs the above-mentioned first level output signal or second level output signal to the high-side switch 17 through the signal output terminal P36 to control the conduction state of the high-side switch 17, and the output / clamp terminal P37 is electrically coupled to an external element (not shown) to implement a clamping operation when the high-side switch 17 is turned off.

[0029] In some embodiments, the isolated integrated circuit 15 includes a first power terminal P51, a first signal input terminal P52, a second signal input terminal P53, a first ground terminal P54, a second power terminal P55, a signal output terminal P56, an output / clamp terminal P57, and a second ground terminal P58. Figure 1 As shown, the isolated integrated circuit 15 receives the first power supply voltage VCC2 through the first power supply terminal P51, receives the second input signal IN- through the first signal input terminal P52, receives the first input signal IN+ through the second signal input terminal P53, receives the first ground voltage GND2 through the first ground terminal P54, receives the second power supply voltage VDD2 through the second power supply terminal P55, outputs the aforementioned output signal OUT2 through the signal output terminal P56, and receives the second ground voltage VEE2 through the second ground terminal P58.

[0030] In some further embodiments, the output / clamp terminal P57 may be electrically coupled to the low-side switch 19, and the isolated integrated circuit 15 outputs a first level output signal (not shown) to the low-side switch 19 through the signal output terminal P56, or outputs a second level output signal (not shown) to the low-side switch 19 through the output / clamp terminal P57 as the output signal OUT2, that is, the signal output terminal P56 and the output / clamp terminal P57 are used together to control the low-side switch 19, wherein the first level output signal may have a low logic level, and the second level output signal may have a high logic level. In some other further embodiments, the isolated integrated circuit 15 outputs the above-mentioned first level output signal or second level output signal to the low-side switch 19 from the signal output terminal P56 to control the conduction state of the low-side switch 19, and the output / clamp terminal P57 is electrically coupled to an external element (not shown) to implement a clamping operation when the low-side switch 19 is turned off.

[0031] In the above embodiment, if Figure 1 As shown, the high-side switch 17 is coupled to the third power supply voltage HVDC, and the low-side switch 19 is coupled to the second ground voltage VEE2. That is, the high-side switch 17 and the low-side switch 19 are connected in series between the third power supply voltage HVDC and the second ground voltage VEE2. In the above embodiment, the first power supply voltage VCC1, the first power supply voltage VCC2, the second power supply voltage VDD1, the second power supply voltage VDD2 and the third power supply voltage HVDC are different from each other, and the first ground voltage GND1, the first ground voltage GND2, the second ground voltage VEE1 and the second ground voltage VEE2 are different from each other, but the present invention is not limited thereto.

[0032] Generally speaking, the high-side switch 17 and the low-side switch 19 can be implemented by transistors (e.g., metal oxide semiconductor (MOS) transistors). Therefore, if the high-side switch 17 and the low-side switch 19 are turned on at the same time due to some non-ideal factors, a large current may flow through the high-side switch 17 and the low-side switch 19, which further causes the high-side switch 17 and the low-side switch 19 themselves or the transistors inside them to burn out.

[0033] In view of this, in some embodiments, the isolated integrated circuit 13 is configured with a signal delay setting circuit 131, and the isolated integrated circuit 15 is configured with a signal delay setting circuit 151. It is worth noting that the signal delay setting circuit 131 and the signal delay setting circuit 151 are respectively used to control the duty ratio of the output signal OUT1 and the duty ratio of the output signal OUT2, thereby ensuring that the high-side switch 17 and the low-side switch 19 are not turned on at the same time.

[0034] Then match Figure 2 Describe the isolated integrated circuit 13 in detail, Figure 2 FIG. 1 is a circuit diagram of an isolated integrated circuit 13 according to some embodiments of the present application. In some embodiments, the isolated integrated circuit 13 includes the aforementioned signal delay setting circuit 131, a primary side circuit 133, an isolation circuit 135, and a secondary side circuit 137. Specifically, the isolated integrated circuit 13 can be, for example but not limited to, a gate driver. That is, in some embodiments, the output signal OUT1 is output to the gate of the transistor of the high-side switch 17.

[0035] In some embodiments, the signal delay setting circuit 131 includes a voltage drop generating circuit 311, a delay time control circuit 313, and a signal delay circuit 315. In some further embodiments, the voltage drop generating circuit 311 includes a current generating circuit ICS, a resistor element RDT, and a switch circuit SW, wherein the switch circuit SW includes a first switch SW1 and a second switch SW2. Specifically, the current generating circuit ICS can be implemented by a current source (e.g., a current mirror circuit), the resistor element RDT can be implemented by a resistor, and the first switch SW1 and the second switch SW2 can be implemented by transistors. It should be understood that in some embodiments, the resistor element RDT can also be replaced by other suitable passive elements (e.g., capacitors, inductors, etc.).

[0036] In some embodiments, the primary side circuit 133 includes a logic control circuit 331, a logic circuit 333, a logic circuit 335, and a logic circuit 337. Specifically, the logic control circuit 331 may be implemented by an oscillator, a modulator, a transmitter, or a combination thereof, the logic circuit 333 may be implemented by an AND gate, the logic circuit 335 may be implemented by a buffer gate, and the logic circuit 337 may be implemented by a NOT gate.

[0037] In some embodiments, the logic circuit 335 is coupled between the first signal input terminal P32 and the first data input terminal of the logic circuit 333. The signal delay circuit 315 is coupled between the second signal input terminal P33 and the data input terminal of the logic circuit 337, and the logic circuit 337 is coupled between the signal delay circuit 315 and the second data input terminal of the logic circuit 333. Furthermore, the data output terminal of the logic circuit 333 is coupled to the data input terminal of the logic control circuit 331.

[0038] In some embodiments, the current generating circuit ICS is coupled between the first power supply terminal P31 and the first switch SW1. The first switch SW1 is coupled between the current generating circuit ICS and the first signal input terminal P32. The resistor element RDT is coupled between the first signal input terminal P32 and the second signal input terminal P33. The second switch SW2 is coupled between the second signal input terminal P33 and the first ground terminal P34.

[0039] In some embodiments, the delay time control circuit 313 is coupled to the first power terminal P31, the logic control circuit 331, the signal delay circuit 315, the first signal input terminal P32, the second signal input terminal P33, the first switch SW1 and the second switch SW2.

[0040] From the above description of the signal delay setting circuit 131 and the primary side circuit 133, it can be known that the signal delay setting circuit 131 is coupled to the primary side circuit 133. In addition, in some further embodiments, Figure 2 As shown, the resistor RDT in the signal delay setting circuit 131 is disposed outside the isolated integrated circuit 13, while the current generating circuit ICS, the first switch SW1, and the second switch SW2 in the signal delay setting circuit 131 are disposed inside the isolated integrated circuit 13. However, the present invention is not limited thereto, and any circuit that can generate a voltage difference VDT between the first signal input terminal P32 and the second signal input terminal P33 within a specific period can be used to implement the signal delay setting circuit 131.

[0041] In some embodiments, one end of the isolation circuit 135 is coupled to the output end of the primary circuit 133 (i.e., the data output end of the logic control circuit 331), and the other end of the isolation circuit 135 is coupled to the input end of the secondary circuit 137, so as to provide electrical insulation between the primary circuit 133 and the secondary circuit 137 in the isolated integrated circuit 13 in response to system requirements. Accordingly, the operating voltage of the primary circuit 133 (i.e., the first power supply voltage VCC1 and the first ground voltage GND1) is different from the operating voltage of the secondary circuit 137 (i.e., the second power supply voltage VDD1 and the second ground voltage VEE1). Specifically, the isolation circuit 135 can be implemented by a passive element (e.g., a capacitor 351) or an insulating element (e.g., a transformer).

[0042] In some embodiments, while ensuring voltage isolation (i.e., the aforementioned electrical insulation) between the primary circuit 133 and the secondary circuit 137, the isolation circuit 135 is also used as a communication interface between the primary circuit 133 and the secondary circuit 137, so that data, signals, and / or information can be transmitted from the primary circuit 133 (e.g., through voltage coupling) to the secondary circuit 137. In addition, in some embodiments, the secondary circuit 137 can be implemented by a demodulator, a receiver, an amplifier, or a combination thereof.

[0043] In some embodiments, the first power supply voltage VCC1 starts to rise from 0 volts. After the first power supply voltage VCC1 rises to a power-on reset voltage POR (e.g., 1.2-1.8 volts), the isolated integrated circuit 13 will be initialized to a known state to facilitate logic operations in the isolated integrated circuit 13. Then, after the first power supply voltage VCC1 continues to rise to an undervoltage lockout voltage UVLO (e.g., 3, 5, 8 volts), the isolated integrated circuit 13 then operates according to the first input signal IN+ and the second input signal IN-.

[0044] In some embodiments, the delay time control circuit 313 is used to detect the first power supply voltage VCC1. When it is detected that the first power supply voltage VCC1 is greater than the power-on reset voltage POR and less than the under-voltage lockout voltage UVLO, the delay time control circuit 313 controls the first switch SW1 and the second switch SW2 to be turned on. Accordingly, a current path is formed between the first power supply voltage VCC1 and the first ground voltage GND1. Specifically, the current path includes the first power supply terminal P31, the current generating circuit ICS, the first switch SW1, the resistor RDT, the second switch SW2 and the first ground terminal P34.

[0045] In some embodiments, the current generating circuit ICS is used to generate a detection current Id according to the first power supply voltage VCC1, wherein the detection current Id may be a fixed current. Through the current path, the detection current Id generated by the current generating circuit ICS will sequentially flow through the first power supply terminal P31, the current generating circuit ICS, the first switch SW1, the resistor element RDT and the second switch SW2, and flow to the first ground terminal P34. According to Ohm's law, when the detection current Id flows through the resistor element RDT, a voltage difference VDT will be generated at both ends of the resistor element RDT (i.e., the first signal input terminal P32 and the second signal input terminal P33). In some embodiments, the delay time control circuit 313 is used to calculate the delay time DT according to the voltage difference VDT, which will be described in conjunction with the following paragraphs. Figure 3 Detailed description.

[0046] See also Figure 3 , Figure 3 FIG. 3 is a circuit block diagram of a delay time control circuit 313 according to some embodiments of the present application. In some embodiments, the delay time control circuit 313 includes a central control circuit 3131, a voltage sensing circuit 3133, a storage circuit 3135, a delay time calculation circuit 3137, and a switch driving circuit 3139. Figure 3 As shown, the voltage sensing circuit 3133 is coupled to the first signal input terminal P32 and the second signal input terminal P33. The storage circuit 3135 is coupled to the voltage sensing circuit 3133, and the delay time calculation circuit 3137 is coupled to the storage circuit 3135. The central control circuit 3131 is coupled to the voltage sensing circuit 3133, the storage circuit 3135, the delay time calculation circuit 3137 and the switch driving circuit 3139.

[0047] In some embodiments, the central control circuit 3131 is used to detect the first power voltage VCC1 and to control the operations of the voltage sensing circuit 3133 , the storage circuit 3135 , the delay time calculation circuit 3137 and the switch driving circuit 3139 .

[0048] In some embodiments, the voltage sensing circuit 3133 senses the voltage difference VDT between the first signal input terminal P32 and the second signal input terminal P33 to output a sensing voltage value VSEN corresponding to the voltage difference VDT. In some embodiments, the sensing voltage value VSEN is the current value of the detection current Id (e.g., 0.1 to 100 microamperes (μA)) multiplied by the resistance value of the resistor RDT (e.g., 1 to 500 kiloohms (kΩ)).

[0049] In some embodiments, the storage circuit 3135 is used to store the sensing voltage value VSEN to provide the sensing voltage value VSEN to the delay time calculation circuit 3137. Specifically, the storage circuit 3135 can be implemented by one or more memories.

[0050] In some embodiments, the delay time calculation circuit 3137 is used to calculate the delay time DT based on the sensing voltage value VSEN. In some further embodiments, the storage circuit 3135 pre-stores a lookup table (not shown), wherein the lookup table records multiple voltage values ​​and corresponding multiple durations. Therefore, the delay time calculation circuit 3137 can find the same voltage value as the sensing voltage value VSEN among the multiple voltage values ​​by comparing the multiple voltage values ​​in the lookup table with the sensing voltage value VSEN, and use the duration corresponding to the voltage value as the delay time DT. It should be understood that in the case where the voltage value that is the same as the sensing voltage value VSEN is not found from the multiple voltage values, the delay time calculation circuit 3137 can further calculate the delay time DT by (for example but not limited to) interpolation.

[0051] The method for calculating the delay time DT is not limited to the above. For example, in some embodiments, the delay time calculation circuit 3137 calculates the delay time DT by substituting the sensing voltage value VSEN into the following formula (1), where a and b can each be any pre-set value. It should be understood that the delay time calculation circuit 3137 is not limited to using formula (1) to calculate the delay time DT, and any formula that can describe the relationship between the sensing voltage value VSEN and the delay time DT can be used by the delay time calculation circuit 3137 to calculate the delay time DT.

[0052] DT=a×VSEN+b…(1)

[0053] Following the above embodiment in which the delay time control circuit 313 controls the first switch SW1 and the second switch SW2 to be turned on, the delay time control circuit 313 can Figure 3 The switch driving circuit 3139 controls the first switch SW1 and the second switch SW2 to be turned on or off. For example, when the central control circuit 3131 detects that the first power supply voltage VCC1 is greater than the power-on reset voltage POR and less than the under-voltage lockout voltage UVLO, the central control circuit 3131 controls the switch driving circuit 3139 to output an enable signal SEN to the first switch SW1 and the second switch SW2 to control the first switch SW1 and the second switch SW2 to be turned on.

[0054] In some embodiments, when the first power supply voltage VCC1 is detected to be not greater than the power-on reset voltage POR or not less than the under-voltage lockout voltage UVLO, the delay time control circuit 313 controls the first switch SW1 and the second switch SW2 to be turned off through the switch driving circuit 3139. Accordingly, the detection current Id does not flow through the resistor RDT.

[0055] Depend on Figure 2 and Figure 3 As can be seen from the description, the delay time control circuit 313 is used to enable the voltage drop generating circuit 311 (i.e., turn on the first switch SW1 and the second switch SW2) to generate a voltage difference VDT at the first signal input terminal P32 and the second signal input terminal P33 when the first power supply voltage VCC1 is within a preset voltage range (i.e., between the power-on reset voltage POR and the under-voltage lockout voltage UVLO). In addition, the delay time control circuit 313 can calculate the delay time DT according to the voltage difference VDT by looking up a table or calculating by a formula.

[0056] In some embodiments, after the delay time calculation circuit 3137 calculates the delay time DT, the delay time control circuit 313 Figure 2 As shown, the delay time DT is provided to the signal delay circuit 315 .

[0057] In some embodiments, as described above, when it is detected that the first power voltage VCC1 continues to rise and exceeds the under-voltage lockout voltage UVLO, the delay time control circuit 313 disables the voltage drop generating circuit 311 (i.e., turns off the first switch SW1 and the second switch SW2). Accordingly, the isolated integrated circuit 13 can operate according to the first input signal IN+ and the second input signal IN-, and the signal delay circuit 315 can delay the received signal according to the delay time DT.

[0058] Then match Figure 2 and Figure 4 The operation of the isolated integrated circuit 13 according to the first input signal IN+ and the second input signal IN- is described. Figure 4 FIG. 1 is a timing diagram of some signals related to the isolated integrated circuit 13 according to some embodiments of the present application.

[0059] In some embodiments, Figure 2 As shown, the primary side circuit 133 receives the first input signal IN+ from the first signal input terminal P32 through the logic circuit 335 .

[0060] In some embodiments, Figure 2 As shown, the signal delay circuit 315 receives the second input signal IN- from the second signal input terminal P33, and delays the second input signal IN- according to the delay time DT to output the delayed input signal DIN- to the logic circuit 337. In some further embodiments, as Figure 4 As shown, the signal delay circuit 315 delays the falling edge RE- of the second input signal IN- according to the delay time DT to generate the delayed input signal DIN-. Figure 4 In the embodiment, the falling edge DRE- of the delayed input signal DIN- will lag behind the falling edge RE- of the second input signal IN- by about the delay time DT. In this embodiment, the signal delay circuit 315 can be a digital circuit, which is convenient for delaying only the falling edge RE- of the second input signal IN-, but the present invention is not limited thereto. In addition, although the signal delay circuit 315 is arranged on the transmission path of the second input signal IN- in this embodiment, in some variations of the present invention, the signal delay circuit 315 can be arranged on the transmission path of the first input signal IN+ instead, so as to achieve the same effect.

[0061] exist Figure 2In the embodiment of the present invention, the logic circuit 335 buffers the first input signal IN+ and transmits it to the logic circuit 333, and the logic circuit 337 inverts the delayed input signal DIN- and transmits it to the logic circuit 333. Thereafter, the logic circuit 333 generates an intermediate signal MID1 to the logic control circuit 331 according to the first input signal IN+ and the delayed input signal DIN-, and the logic control circuit 331 can appropriately process the intermediate signal MID1 (e.g., signal buffering, signal amplification, etc.) and couple it to the isolation circuit 135.

[0062] In some embodiments, Figure 2 As shown, the isolation circuit 135 is used to couple the intermediate signal MID1 from the primary circuit 133 to the secondary circuit 137, so that the secondary circuit 137 generates the output signal OUT1 according to the intermediate signal MID1. In some further embodiments, the secondary circuit 137 receives and appropriately processes (e.g., signal buffering, signal amplification, etc.) a signal substantially the same as the intermediate signal MID1 to generate the output signal OUT1. Therefore, in some embodiments, as Figure 4 As shown, the waveform of the output signal OUT1 and the waveform of the intermediate signal MID1 have substantially the same frequency and / or period.

[0063] Then match it with Figure 4 Further explanation of the output signal OUT1. Figure 2 In the case of the circuit structure, each cycle of the output signal OUT1 has an enable period DTEN1 (corresponding to the output signal OUT1 at the enable level) and a disable period DTDE1 (corresponding to the output signal OUT1 at the disable level).

[0064] again, Figure 4 The thick dashed line in FIG. 1 also indicates the rising edge of the output signal OUT1 when the isolated integrated circuit 13 does not delay the second input signal IN- in the primary circuit 133. In this case, each cycle of the signal output by the isolated integrated circuit 13 has an enable period TEN1 and a disable period TDE1. Figure 4 It can be seen that compared with the output signal OUT1 generated without delaying the second input signal IN- in the primary side circuit 133, the output signal OUT1 generated by using Figure 2 The output signal OUT1 generated by the circuit architecture has a lower duty cycle (i.e., the proportion of the enable period DTEN1 in a cycle of the output signal OUT1). The aforementioned “lower duty cycle” can prevent the high-side switch 17 and the low-side switch 19 from being turned on at the same time. This effect will be discussed in the following paragraphs. Figure 6 Detailed description.

[0065] See also Figure 5 , Figure 51 is a timing diagram of some signals related to the isolated integrated circuit 15 according to some embodiments of the present application. It should be understood that Figure 1 The isolated integrated circuit 15 in the embodiment can be used with Figure 2 The isolated integrated circuit 13 in the embodiment has the same or similar circuit structure, so the detailed description of the isolated integrated circuit 15 is omitted here.

[0066] like Figure 5 As shown, the difference between the isolated integrated circuit 15 and the isolated integrated circuit 13 is that the isolated integrated circuit 15 receives the second input signal IN- through the first signal input terminal P52, and receives the first input signal IN+ through the second signal input terminal P53. In other words, in some embodiments, the signal delay setting circuit 151 in the isolated integrated circuit 15 delays the falling edge RE+ of the first input signal IN+, so that the isolated integrated circuit 15 generates the output signal OUT2. Similar to the output signal OUT1, each cycle of the output signal OUT2 has an enable period DTEN2 (corresponding to the output signal OUT2 at the enable level) and a disable period DTDE2 (corresponding to the output signal OUT2 at the disable level).

[0067] also, Figure 5 The thick dashed line in FIG. 1 also indicates the rising edge of the output signal OUT2 when the isolated integrated circuit 15 does not delay the first input signal IN+ in the primary side circuit. In this case, each cycle of the signal output by the isolated integrated circuit 15 has an enable period TEN2 and a disable period TDE2. Figure 5 It can be seen that, compared with the output signal OUT2 generated by not delaying the first input signal IN+ in the primary side circuit of the isolated integrated circuit 15, the output signal OUT2 generated by delaying the first input signal IN+ in the primary side circuit of the isolated integrated circuit 15 has a lower duty cycle (i.e., the proportion of the enable period DTEN2 in a cycle of the output signal OUT2). The aforementioned "lower duty cycle" can prevent the high-side switch 17 and the low-side switch 19 from being turned on at the same time, and this effect will be explained in the following paragraphs. Figure 6 Detailed description.

[0068] In the above embodiment, Figure 1 The high-side switch 17 is based on the output signal OUT1 (corresponding to the enable level) Figure 4 During the enable period DTEN1) is turned on, and according to the output signal OUT1 (corresponding to the disable level) Figure 4 During the disable period, DTDE1 is turned off. Figure 1 The low-side switch 19 is based on the output signal OUT2 (corresponding to the enable level) Figure 5 The enable period DTEN2) is turned on, and the output signal OUT2 (corresponding to the disable level) Figure 5 DTDE2) is turned off during the disable period.

[0069] Then match Figure 6 To further explain the relationship between the output signal OUT1 and the output signal OUT2, Figure 6 1 is a timing diagram of the output signal OUT1 and the output signal OUT2 according to some embodiments of the present application. As can be seen from the above description, the signal delay setting circuit 131 controls the isolated integrated circuit 13 to generate the output signal OUT1 with a lower duty cycle, and the signal delay setting circuit 151 controls the isolated integrated circuit 15 to generate the output signal OUT2 with a lower duty cycle. Figure 6 As shown, the high-side switch 17 is turned on during the period QON1 (corresponding to the enable period DTEN1 of the output signal OUT1), and the low-side switch 19 is turned on during the period QON2 (corresponding to the enable period DTEN2 of the output signal OUT2). The period QON1 and the period QON2 do not overlap, which means that the high-side switch 17 and the low-side switch 19 are not turned on at the same time. The period DZ between the period QON1 and the period QON2 is usually called a dead zone or dead time.

[0070] In the above embodiment, Figure 2 As shown, the logic circuit 337 is coupled between the signal delay circuit 315 and the logic circuit 333, but the present invention is not limited thereto. For example, in some embodiments, the logic circuit 337 is coupled between the second signal input terminal P33 and the signal delay circuit 315. In this configuration, the logic circuit 337 inverts the second input signal IN- and transmits it to the signal delay circuit 315. The signal delay circuit 315 then delays multiple rising edges of the inverted second input signal IN- according to the delay time DT, so that the following can also be generated: Figure 4 The output signal OUT1 is shown.

[0071] In the above embodiment, if Figure 2 As shown, the signal delay circuit 315 is used to delay the second input signal IN- from the second signal input terminal P33, but the present invention is not limited thereto. For example, in some embodiments, the signal delay circuit 315 can be connected in series before or after the logic circuit 335, and delay multiple rising edges of the first input signal IN+ from the first signal input terminal P32 according to the delay time DT, and the second input signal IN- from the second signal input terminal P33 is directly transmitted to the logic circuit 337, so as to generate the following Figure 4 The output signal OUT1 is shown.

[0072] As can be seen from the above description, the signal delay circuit 315 of the present application can delay one of the first input signal IN+ and the second input signal IN- according to the delay time DT to control the duty cycle of the output signal OUT1 when the first power supply voltage VCC1 is greater than the upper limit of the preset voltage range (i.e., exceeds the under-voltage lockout voltage UVLO). It should be understood that the above description is also applicable to the signal delay setting circuit 151 in the isolated integrated circuit 15, that is, the signal delay setting circuit 151 can delay one of the first input signal IN+ and the second input signal IN- according to the delay time DT to control the duty cycle of the output signal OUT2. Since the signal delay setting circuit 151 can be configured with reference to the signal delay setting circuit 131, the remaining detailed descriptions of the signal delay setting circuit 151 are omitted here.

[0073] In the above embodiment, if Figure 2 As shown, the logic control circuit 331 processes the intermediate signal MID1 appropriately (e.g., signal buffering, signal amplification, etc.) and then couples it to the isolation circuit 135. In some further embodiments, the logic control circuit 331 modulates the intermediate signal MID1 according to the baseband signal provided by the oscillator through a modulator to generate a modulated signal. The isolation circuit 135 couples the modulated signal to the secondary circuit 137. The secondary circuit 137 demodulates the modulated signal through a demodulator to generate a signal substantially the same as the intermediate signal MID1.

[0074] In addition, the delay time control circuit 313 of the present application is not limited to Figure 3 For example, in some embodiments, the central control circuit 3131 can receive and store the sensing voltage value VSEN through its internal storage circuit (not shown) to provide the sensing voltage value VSEN to the delay time calculation circuit 3137. In these embodiments, the storage circuit 3135 can be Figure 3 Omitted in .

[0075] As can be seen from the above embodiments of the present application, the duty cycle of the output signal OUT1 generated by the isolated integrated circuit 13 and the duty cycle of the output signal OUT2 generated by the isolated integrated circuit 15 are controlled by the signal delay setting circuit 131 and the signal delay setting circuit 151, respectively. The power conversion circuit system 100 of the present application can effectively generate dead time to prevent the high-side switch 17 and the low-side switch 19 from being turned on at the same time, so as to achieve the effect of protecting the high-side switch 17 and the low-side switch 19. In addition, compared with some related technologies that generate dead time by using resistor-capacitor circuit settings or using trimming methods, the isolated integrated circuit 13, the isolated integrated circuit 15 and the power conversion circuit system 100 of the present application have the advantages of low deviation, high reliability, and small circuit area requirements.

[0076] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the attached claims.

[0077]

Explanation of symbols

[0078] 11: Controller circuit

[0079] 13,15:Isolated integrated circuits

[0080] 17: High-side switch

[0081] 19: Low-side switch

[0082] 100: Power conversion circuit system

[0083] 131,151:Signal delay setting circuit

[0084] 133: Primary circuit

[0085] 135: Isolation circuit

[0086] 137: Secondary circuit

[0087] 311: Voltage drop generating circuit

[0088] 313: Delay time control circuit

[0089] 315:Signal delay circuit

[0090] 331:Logic control circuit

[0091] 333,335,337: Logic Circuits

[0092] 351:Capacitor

[0093] 3131: Central control circuit

[0094] 3133: Voltage sensing circuit

[0095] 3135: Storage circuit

[0096] 3137: Delay time calculation circuit

[0097] 3139:Switch drive circuit

[0098] DIN-: Delayed input signal

[0099] DT: Delay time

[0100] GND1, GND2: First ground voltage

[0101] HVDC: Third supply voltage

[0102] ICS: Current generating circuit

[0103] Id: Detection current

[0104] IN+: First input signal

[0105] IN-: Second input signal

[0106] MID1: Middle signal

[0107] OUT1, OUT2: output signal

[0108] P31, P51: First power supply terminal

[0109] P32, P52: First signal input terminal

[0110] P33, P53: Second signal input terminal

[0111] P34, P54: First ground terminal

[0112] P35, P55: Second power supply terminal

[0113] P36, P56: signal output terminal

[0114] P37, P57: Output / Clamp terminal

[0115] P38, P58: Second ground terminal

[0116] POR: Power-on reset voltage

[0117] QON1,QON2,DZ: Period

[0118] RDT: Resistor

[0119] RE-, DRE-, RE+: Falling edge

[0120] SEN: Enable signal

[0121] SW: Switching circuit

[0122] SW1: First switch

[0123] SW2: Second switch

[0124] TDE1, TDE2, DTDE1, DTDE2: Disable period

[0125] TEN1, TEN2, DTEN1, DTEN2: Enable period

[0126] UVLO: Under Voltage Lockout Voltage

[0127] VCC1, VCC2: First power supply voltage

[0128] VDD1, VDD2: Second power supply voltage

[0129] VDT: Voltage difference

[0130] VEE1, VEE2: Second ground voltage

[0131] VSEN: Sense voltage value.

Claims

1. A signal delay setting circuit, suitable for an isolated integrated circuit, characterized in that: The isolated integrated circuit comprises a first signal input terminal, a second signal input terminal and a signal output terminal, wherein the first signal input terminal is used to receive a first input signal, the second signal input terminal is used to receive a second input signal, and the signal output terminal is used to output an output signal generated according to the first input signal and the second input signal, and the signal delay setting circuit comprises: A voltage drop generating circuit, used for generating a voltage difference between the first signal input terminal and the second signal input terminal; A delay time control circuit is coupled to the voltage drop generating circuit and is used to enable the voltage drop generating circuit to generate the voltage difference when the first power supply voltage is within a preset voltage range, and is used to obtain the delay time according to the voltage difference, wherein the isolated integrated circuit further includes a first power supply terminal, and the first power supply terminal is used to receive the first power supply voltage; as well as The signal delay circuit is coupled to the delay time control circuit and is used to delay one of the first input signal and the second input signal according to the delay time when the first power supply voltage is greater than the upper limit of the preset voltage range to control the duty cycle of the output signal.

2. The signal delay setting circuit according to claim 1, characterized in that: The voltage drop generating circuit comprises: A current generating circuit is coupled to the first power supply terminal and is used to output a detection current; A resistor element coupled between the first signal input terminal and the second signal input terminal; as well as The switch circuit is coupled to the current generating circuit, the resistor element and the first ground voltage, and is used to be turned on when the delay time control circuit enables the voltage drop generating circuit to allow the detection current to flow through the resistor element, thereby generating the voltage difference across the resistor element.

3. The signal delay setting circuit according to claim 2, characterized in that: The resistor element is arranged outside the isolated integrated circuit, and the current generating circuit and the switch circuit are arranged inside the isolated integrated circuit.

4. The signal delay setting circuit according to claim 2, characterized in that: The switching circuit comprises: A first switch coupled between the current generating circuit and the first signal input terminal; and The second switch is coupled between the second signal input terminal and a first ground terminal of the isolation integrated circuit, wherein the first ground terminal is used for receiving the first ground voltage.

5. The signal delay setting circuit according to claim 1, characterized in that: The delay time control circuit comprises: A voltage sensing circuit, used for sensing the voltage difference between the first signal input terminal and the second signal input terminal, so as to output a sensing voltage value corresponding to the voltage difference; A delay time calculation circuit, used for calculating the delay time according to the sensed voltage value, so as to output the delay time to the signal delay circuit; A switch driving circuit, used for controlling the switch circuit in the voltage drop generating circuit to be turned on or off; as well as The central control circuit is coupled to the voltage sensing circuit, the delay time calculation circuit and the switch driving circuit, and is used to control the voltage sensing circuit, the delay time calculation circuit and the switch driving circuit.

6. The signal delay setting circuit according to claim 5, characterized in that: The delay time control circuit also includes: The storage circuit is coupled to the voltage sensing circuit, the delay time calculation circuit and the central control circuit, and is used to store the sensing voltage value to provide the sensing voltage value to the delay time calculation circuit.

7. The signal delay setting circuit according to claim 1, characterized in that: The signal delay circuit is coupled to the second signal input terminal and is used for delaying a plurality of falling edges of the second input signal or a plurality of rising edges of the inverted second input signal by the delay time.

8. The signal delay setting circuit according to claim 1, characterized in that: The preset voltage range is between a power-on reset voltage and an under-voltage lockout voltage.

9. An isolated integrated circuit, characterized in that: It has a first power supply terminal, a first signal input terminal, a second signal input terminal and a signal output terminal, and includes: a primary side circuit, for receiving a first power supply voltage through the first power supply terminal, for receiving a first input signal through the first signal input terminal, for receiving a second input signal through the second signal input terminal, and for generating an intermediate signal according to the first input signal and the second input signal; An isolation circuit, coupled to the primary side circuit and used for transmitting the intermediate signal; A secondary side circuit coupled to the isolation circuit and configured to receive the intermediate signal through the isolation circuit and to output an output signal generated according to the intermediate signal through the signal output terminal; as well as The signal delay setting circuit is coupled to the primary side circuit and is used to calculate the delay time according to the voltage difference between the first signal input terminal and the second signal input terminal when the first power supply voltage is within the preset voltage range, and is used to delay one of the first input signal and the second input signal according to the delay time when the first power supply voltage is greater than the upper limit of the preset voltage range to control the duty cycle of the output signal.

10. A power conversion circuit system, characterized in that: Include: High-side switch; Low-side switch; A controller circuit, configured to output a first input signal and a second input signal; A first isolated integrated circuit is coupled between the controller circuit and the high-side switch, has a first signal input terminal and a second signal input terminal, and includes a first signal delay setting circuit, wherein the first isolated integrated circuit is used to receive the first input signal through the first signal input terminal, receive the second input signal through the second signal input terminal, and generate a first output signal for driving the high-side switch according to the first input signal and the second input signal; as well as A second isolated integrated circuit is coupled between the controller circuit and the low-side switch, has a third signal input terminal and a fourth signal input terminal, and includes a second signal delay setting circuit, wherein the second isolated integrated circuit is used to receive the second input signal through the third signal input terminal, receive the first input signal through the fourth signal input terminal, and generate a second output signal for driving the low-side switch according to the first input signal and the second input signal; Wherein, when the first power supply voltage is within a preset voltage range, the first signal delay setting circuit calculates a first delay time according to a first voltage difference between the first signal input terminal and the second signal input terminal, and the second signal delay setting circuit calculates a second delay time according to a second voltage difference between the third signal input terminal and the fourth signal input terminal; When the first power supply voltage is greater than the upper limit value of the preset voltage range, the first signal delay setting circuit delays the second input signal according to the first delay time to control the duty cycle of the first output signal, and the second signal delay setting circuit delays the first input signal according to the second delay time to control the duty cycle of the second output signal, so that the high-side switch and the low-side switch will not be turned on at the same time.

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