Level shift circuit

Abstract

The invention relates to the technical field of microelectronics, semiconductors and communication technologies, and discloses a level shifting circuit which comprises a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a resistor R1 and a resistor R2. According to the level shift circuit, circuit optimization and improvement are carried out in the direction of level overturning, due to the fact that the phase inverter in the level shift circuit is composed of four transistors, high impedance of the output end is more stable, the influence of cascading is small, the consistency of circuit simulation and actual measurement is improved, and therefore the one-time success rate of design is improved.

Description

Technical Field

[0001] The present invention relates to the technical fields of microelectronics, semiconductors and communication technologies, and in particular to a level shift circuit. Background Art

[0002] In recent years, with the rapid development of RF chip design technology, the design and use of control chips such as RF switches, attenuators, and phase shifters have become more mature, and single-function devices are gradually unable to meet market demand. Multi-CNC circuits were born, and the addition of control circuits made the design of switches, attenuators, phase shifters and other devices more complex and diverse, but also realized rich control logic, thereby providing users with more advanced and broad application scenarios.

[0003] Logic control circuits often use digital circuits such as NOT gates, OR gates, NAND gates, and NOR gates. Among them, the most frequently used combinational logic circuits are 2-4 decoders, which integrate NOT gates and NOR gate circuits. In digital circuits, this circuit is widely used and mature, but in GaAs processes, due to process reasons, its digital circuit modeling is difficult and the model establishment is inaccurate. The logic tubes used in circuit simulation have threshold voltage fluctuations, which leads to the phenomenon of false flipping or non-flipping of the digital circuit level. This results in the circuit that can be realized by the process itself, but cannot be realized when the model is simulated under specific process conditions. This phenomenon weakens the accuracy of circuit model simulation and also undermines the confidence of designers. Summary of the invention

[0004] Based on this, it is necessary to address the technical problem that the GaAs process level shift circuit in the prior art has a poor effect, and propose a level shift circuit, the circuit comprising:

[0005] Diode D1, diode D2, diode D3, diode D4, diode D5, diode D6, transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, transistor M7, transistor M8, resistor R1, resistor R2;

[0006] The anode of the diode D1 is connected to the AC signal source, the cathode of the diode D1 is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the anode of the diode D3, the cathode of the diode D3 is connected to the anode of the diode D4, the cathode of the diode D4 is connected to the anode of the diode D5, the cathode of the diode D5 is connected to the anode of the diode D6, the cathode of the diode D6 is respectively connected to one end of the resistor R1 and the drain of the transistor M9, and the source and gate of the transistor M9 are connected to VSS;

[0007] The other end of the resistor R1 is connected to the gate of the transistor M1, the drain of the transistor M1 is connected to VSS, the source of the transistor M1 is respectively connected to the gate and drain of the transistor M2, the source of the transistor M2 is grounded, the gate of the transistor M2 is connected to the gate of the transistor M4, the source of the transistor M4 is grounded, the drain of the transistor M4 is respectively connected to the source of the transistor M3 and one end of the resistor R2, the gate and drain of the transistor M3 are connected to VSS, the other end of the resistor R2 is connected to the gate of the transistor M5, the drain of the transistor M5 is connected to VSS, the source of the transistor M5 is respectively connected to the drain and gate of the transistor M6, the source of the transistor M6 is grounded, the gate of the transistor M6 is connected to the gate of the transistor M8, the source of the transistor M8 is grounded, the drain of the transistor M8 is respectively connected to the output port and the source of the transistor M7, and the gate and drain of the transistor M7 are connected to VSS.

[0008] The level shift circuit proposed by the present invention comprises a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a resistor R1, and a resistor R2. The anode of the diode D1 is connected to an AC signal source, the cathode of the diode D1 is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the anode of the diode D3, the cathode of the diode D3 is connected to the anode of the diode D4, the cathode of the diode D4 is connected to the anode of the diode D5, the cathode of the diode D5 is connected to the anode of the diode D6, and the cathode of the diode D6 is respectively connected to one end of the resistor R1 and the drain of the transistor M9. The source and the gate of the transistor M9 are connected to VSS. The other end of the resistor R1 is connected to the drain of the transistor M9. The first end is connected to the gate of transistor M1, the drain of transistor M1 is connected to VSS, the source of transistor M1 is respectively connected to the gate and drain of transistor M2, the source of transistor M2 is grounded, the gate of transistor M2 is connected to the gate of transistor M4, the source of transistor M4 is grounded, the drain of transistor M4 is respectively connected to the source of transistor M3 and one end of resistor R2, the gate and drain of transistor M3 are connected to VSS, the other end of resistor R2 is connected to the gate of transistor M5, the drain of transistor M5 is connected to VSS, the source of transistor M5 is respectively connected to the drain and gate of transistor M6, the source of transistor M6 is grounded, the gate of transistor M6 is connected to the gate of transistor M8, the source of transistor M8 is grounded, the drain of transistor M8 is respectively connected to the output port and the source of transistor M7, and the gate and drain of transistor M7 are connected to VSS. The present invention optimizes and improves the circuit around the direction of level flipping. Since the inverter in the level shift circuit is composed of 4 transistors, the high impedance of the output end is more stable and is less affected by the cascade connection, thereby improving the consistency of circuit simulation and actual measurement, thereby improving the one-time success rate of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] in:

[0011] Figure 1 is a schematic diagram of the circuit structure of a level shift circuit in one embodiment;

[0012] Figure 2 A level conversion diagram of a common level shift circuit in one embodiment;

[0013] Figure 3 FIG. 4 is a level conversion diagram of a level shift circuit of the present invention in one embodiment. DETAILED DESCRIPTION

[0014] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0015] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] See also Figure 1 As shown, Figure 1A circuit diagram of a level shift circuit provided by an embodiment of the present invention includes: a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a resistor R1, and a resistor R2;

[0018] The anode of the diode D1 is connected to the AC signal source, the cathode of the diode D1 is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the anode of the diode D3, the cathode of the diode D3 is connected to the anode of the diode D4, the cathode of the diode D4 is connected to the anode of the diode D5, the cathode of the diode D5 is connected to the anode of the diode D6, the cathode of the diode D6 is respectively connected to one end of the resistor R1 and the drain of the transistor M9, and the source and gate of the transistor M9 are connected to VSS;

[0019] The other end of the resistor R1 is connected to the gate of the transistor M1, the drain of the transistor M1 is connected to VSS, the source of the transistor M1 is respectively connected to the gate and drain of the transistor M2, the source of the transistor M2 is grounded, the gate of the transistor M2 is connected to the gate of the transistor M4, the source of the transistor M4 is grounded, the drain of the transistor M4 is respectively connected to the source of the transistor M3 and one end of the resistor R2, the gate and drain of the transistor M3 are connected to VSS, the other end of the resistor R2 is connected to the gate of the transistor M5, the drain of the transistor M5 is connected to VSS, the source of the transistor M5 is respectively connected to the drain and gate of the transistor M6, the source of the transistor M6 is grounded, the gate of the transistor M6 is connected to the gate of the transistor M8, the source of the transistor M8 is grounded, the drain of the transistor M8 is respectively connected to the output port and the source of the transistor M7, and the gate and drain of the transistor M7 are connected to VSS.

[0020] The working principle of the level shift circuit is as follows: Compared with the general level shift circuit, the output level of the first-stage inverter in the level shift circuit of the present invention is less affected by the second-stage inverter after the inverters are cascaded, and conforms to the normal level flip value. This is because the inverter in the level shift circuit is composed of 4 transistors, which can be subdivided into a depletion load inverter circuit and a resistive load inverter circuit. The high impedance of the output end is more stable, so it is less affected by the cascade.

[0021] The present invention proposes a level shift circuit suitable for GaAs technology. In terms of the level shift of the decoder, if a general level shift circuit is used, there is a risk of incorrect level flipping, which will destroy the accuracy of the level shift circuit simulation and cause the designer to make a wrong judgment. Therefore, the level shift circuit structure of the present invention can accurately display the logic circuit simulation level and meet the required requirements.

[0022] refer to Figure 2, Figure 2 It is a common level shift circuit level conversion diagram. From this figure, the results show that the level conversion of the classic level shift circuit is affected by the inverter cascade, and the flip level changes. Figure 3 , Figure 3 This is a level conversion diagram of the level shift circuit described in the present invention. The results from this diagram show that when the inverter of the level shift circuit is used, no level flip error occurs during the cascade process, which effectively compensates for the shortcomings of GaAs process modeling and improves the accuracy of circuit simulation.

[0023] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A level shift circuit, characterized in that: The level shift circuit includes: a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a resistor R1, and a resistor R2; The anode of the diode D1 is connected to the AC signal source, the cathode of the diode D1 is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the anode of the diode D3, the cathode of the diode D3 is connected to the anode of the diode D4, the cathode of the diode D4 is connected to the anode of the diode D5, the cathode of the diode D5 is connected to the anode of the diode D6, the cathode of the diode D6 is respectively connected to one end of the resistor R1 and the drain of the transistor M9, and the source and gate of the transistor M9 are connected to VSS; The other end of the resistor R1 is connected to the gate of the transistor M1, the drain of the transistor M1 is connected to VSS, the source of the transistor M1 is respectively connected to the gate and drain of the transistor M2, the source of the transistor M2 is grounded, the gate of the transistor M2 is connected to the gate of the transistor M4, the source of the transistor M4 is grounded, the drain of the transistor M4 is respectively connected to the source of the transistor M3 and one end of the resistor R2, the gate and drain of the transistor M3 are connected to VSS, the other end of the resistor R2 is connected to the gate of the transistor M5, the drain of the transistor M5 is connected to VSS, the source of the transistor M5 is respectively connected to the drain and gate of the transistor M6, the source of the transistor M6 is grounded, the gate of the transistor M6 is connected to the gate of the transistor M8, the source of the transistor M8 is grounded, the drain of the transistor M8 is respectively connected to the output port and the source of the transistor M7, and the gate and drain of the transistor M7 are connected to VSS.

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