A memristor-based Boolean logic circuit, control method, and Boolean logic operation device

Abstract

The present invention discloses a memristor-based Boolean logic circuit, a control method and a Boolean logic operation device, belonging to the technical field of microelectronic devices; the Boolean logic circuit includes a memristor M1, a memristor M2, a first NMOS transistor, a second NMOS transistor, a resistor and a voltage comparator; by applying voltages V r at the control terminal T1 and the control terminal T2 respectively, applying the gate voltage corresponding to the logic value a to the gate of the first transistor, applying the gate voltage corresponding to the logic value c to the gate of the second transistor, and grounding the control terminal T3, the corresponding Boolean logic operation result can be obtained at the output terminal of the voltage comparator. The present invention makes full use of the resistance state characteristics of the memristor and the switching characteristics of the transistor, and can realize any Boolean logic operation with fewer operation steps by setting the values of the logic values a, b, c, and d, and supports the realization of complete Boolean logic operations. At the same time, the present invention is easy to cascade and has the advantage of parallel computing.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic devices, and more specifically, relates to a memristor-based Boolean logic circuit, a control method, and a Boolean logic operation device. Background Art

[0002] Traditional computers adopt the von Neumann architecture, where the computing and storage functions are respectively completed by a processing unit and a storage unit. These two units are physically separated and communicate through a bus. In the context of the era of artificial intelligence and big data, the explosively growing data poses higher requirements for the information processing capabilities of computers, and the computing bottleneck under the traditional structure becomes increasingly prominent. On the one hand, the computing frequency of the processor is much faster than the access speed of the memory, resulting in a speed mismatch, namely the "memory wall" problem; on the other hand, the processing of data requires frequent transmission and read / write processes, which brings a great burden to the bus, and at the same time, the transfer of data consumes a large proportion of power consumption and time. The technology of in-memory computing is considered to be one of the key ideas to solve the above problems. By integrating the data computing unit and the storage unit, in-situ logical computing and storage can be realized, thereby avoiding frequent data transfer and greatly improving the computing parallelism.

[0003] A memristor is a storage device that can cause a high-low resistance transition of a resistive switching layer material by applying an electric field. Due to its natural non-volatile characteristics, as well as advantages such as small device size, fast read / write speed, low power consumption, and compatibility with CMOS processes, it can provide a hardware basis for in-memory computing research. In terms of digital logic, by mapping logical values to physical quantities such as resistance and voltage, and configuring the port voltage according to the computing needs, the memristor can perform corresponding resistance state switching under specific conditions, thereby completing logical operations. However, when the existing memristor-based logic circuits implement complete Boolean logic operations, for relatively complex logical operations among them, multiple permutations and combinations of basic Boolean logics are often required to be implemented. For example, for a NAND logic operation, it is necessary to first implement an AND logic operation through an AND control operation, and then invert the result of the AND logic operation through a NOT control operation. This method requires more operation steps and is more complex in operation. Summary of the Invention

[0004] Aiming at the above-mentioned defects or improvement requirements of the prior art, the present invention provides a memristor-based Boolean logic circuit, a control method, and a Boolean logic operation device, which are used to solve the technical problem that the operation is relatively complex when the prior art implements complete Boolean logic operations.

[0005] To achieve the above object, in a first aspect, the present invention provides a memristor-based Boolean logic circuit, including: a memristor M1, a memristor M2, a first NMOS transistor, a second NMOS transistor, a resistor, and a voltage comparator;

[0006] The positive electrode of the memristor M1 serves as the control terminal of T1, and the negative electrode is connected to the source electrode of the first NMOS transistor; the positive electrode of the memristor M2 serves as the control terminal of T2, and the negative electrode is connected to the source electrode of the second NMOS transistor; the drain electrodes of the first NMOS transistor and the second NMOS transistor are both connected to one end of the resistor, and the other end of the resistor serves as the control terminal of T3; the positive terminal of the voltage comparator is connected to the common node of the memristor M1, the memristor M2, and the resistor; the first transistor and the second transistor are the same; the memristor M1 and the memristor M2 are the same; the resistance value of the resistor is the low-resistance state resistance value of the memristor;

[0007] When performing a Boolean logic operation, the memristor M1 is used to store the logical value b; the negative terminal of the voltage comparator is used to connect to the reference voltage V ref ; the memristor M2 is used to store the logical value d; the control terminals of T1 and T2 are respectively used to connect to the voltage V r ; the gate of the first transistor is used to connect to the gate voltage corresponding to the logical value a; the gate of the second transistor is used to connect to the gate voltage corresponding to the logical value c; the control terminal of T3 is used to connect to the ground; the output terminal of the voltage comparator is used to output the corresponding Boolean logic operation result;

[0008] Among them, V ref and V r satisfy: (R H +R L )V r / (2R H +R L )<V ref <2V r / 3; R H and R L are respectively the high-resistance state resistance value and the low-resistance state resistance value of the memristor; the gate voltage corresponding to the logical value 0 is the voltage V G less than the transistor turn-on voltage, and the gate voltage corresponding to the logical value 1 is the voltage V DD greater than or equal to the transistor turn-on voltage.

[0009] Further preferably, when the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, d is 0 or 1;

[0010] When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, d is 0 or 1;

[0011] When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, d is 0 or 1;

[0012] When the Boolean logic operation is a q logic operation, a is 0, c is q, b is 0 or 1, d is 1;

[0013] When the Boolean logic operation is the NOT p logic operation, a is the logical value NOT p, c is 0, b is 1, and d is 0 or 1;

[0014] When the Boolean logic operation is the NOT q logic operation, a is 0, c is the logical value NOT q, b is 0 or 1, and d is 1;

[0015] When the Boolean logic operation is the AND logic operation of logical values p and q, a is p, c is 0, b is q, and d is 0 or 1;

[0016] When the Boolean logic operation is the NAND logic operation of logical values p and q, a is the logical value NOT p, c is the logical value NOT q, b is 1, and d is 1;

[0017] When the Boolean logic operation is the OR logic operation of logical values p and q, a is p, c is q, b is 1, and d is 1;

[0018] When the Boolean logic operation is the NOR logic operation of logical values p and q, a is the logical value NOT p, c is 0, b is the logical value NOT q, and d is 0 or 1;

[0019] When the Boolean logic operation is the material implication logic operation of logical values p and q, a is the logical value NOT p, c is q, b is 1, and d is 1;

[0020] When the Boolean logic operation is the negative material implication logic operation of logical values p and q, a is p, c is 0, b is the logical value NOT q, and d is 0 or 1;

[0021] When the Boolean logic operation is the inverse material implication logic operation of logical values p and q, a is p, c is the logical value NOT q, b is 1, and d is 1;

[0022] When the Boolean logic operation is the inverse negative material implication logic operation of logical values p and q, a is the logical value NOT p, c is 0, b is q, and d is 0 or 1;

[0023] When the Boolean logic operation is the exclusive OR logic operation of logical values p and q, a is the logical value NOT p, c is p, b is q, and d is the logical value NOT q;

[0024] When the Boolean logic operation is the equivalence logic operation of logical values p and q, a is p, c is the logical value NOT p, b is q, and d is the logical value NOT q.

[0025] In a second aspect, the present invention provides a control method for the above-mentioned Boolean logic circuit, including a Boolean logic operation: applying voltages V r to the T1 control terminal and the T2 control terminal respectively, applying the gate voltage corresponding to the logical value a to the gate of the first transistor, applying the gate voltage corresponding to the logical value c to the gate of the second transistor, grounding the T3 control terminal, and reading the corresponding Boolean logic operation result at the output terminal of the voltage comparator;

[0026] Among them, the memristor M1 stores the logical value b, and the memristor M2 stores the logical value d; the negative terminal of the voltage comparator is connected to a reference voltage V ref ; V ref and V r Satisfy: (R H +R L )V r / (2R H +R L ) < V ref < 2V r / 3; R H and R L are respectively the high-resistance state resistance value and the low-resistance state resistance value of the memristor; the gate voltage corresponding to the logical value 0 is a voltage V G less than the transistor turn-on voltage, and the gate voltage corresponding to the logical value 1 is a voltage V DD greater than or equal to the transistor turn-on voltage.

[0027] Further preferably, the above control method further includes: an operation of initializing the memristor performed before the Boolean logic operation;

[0028] The operation of initializing the memristor includes: writing the logical value b in the memristor M1 and writing the logical value d in the memristor M2;

[0029] Among them, the corresponding logical value is written by setting the high and low resistance states of the memristor; the high-resistance state of the memristor corresponds to the logical value 0, and the low-resistance state corresponds to the logical value 1.

[0030] Further preferably, writing the logical value b in the memristor M1 includes:

[0031] When b is 0, the control terminal of T1 is grounded, the control terminal of T2 is set to the floating state, a fixed voltage V q is connected to the control terminal of T3, and V DD is applied to the gates of the first transistor and the second transistor, so as to write the logical value b in the memristor M1;

[0032] When b is 1, a fixed voltage V p is connected to the control terminal of T1, the control terminal of T2 is set to the floating state, the control terminal of T3 is grounded, and V DD is applied to the gates of the first transistor and the second transistor, so as to write the logical value b in the memristor M1;

[0033] Among them, V q > 2|V reset |; V p > (R H +R L )V set / RH ; V reset is the threshold for the memristor to change from the low-resistance state to the high-resistance state; V set is the threshold for the memristor to change from the high-resistance state to the low-resistance state; R H is the high-resistance state resistance value of the memristor; R L is the low-resistance state resistance value of the memristor.

[0034] Further preferably, writing the logical value d in the memristor M2 includes:

[0035] When d is 0, set the control terminal of T1 to the floating state, ground the control terminal of T2, connect a fixed voltage V q to the control terminal of T3, apply V DD to the gates of the first transistor and the second transistor, and write the logical value d in the memristor M2;

[0036] When d is 1, set the control terminal of T1 to the floating state, connect a fixed voltage V p to the control terminal of T2, ground the control terminal of T3, apply V DD to the gates of the first transistor and the second transistor, and write the logical value d in the memristor M2;

[0037] wherein, V q > 2|V reset |; V p > (R H + R L )V set / R H ; V reset is the threshold for the memristor to change from the low-resistance state to the high-resistance state; V set is the threshold for the memristor to change from the high-resistance state to the low-resistance state; R H is the high-resistance state resistance value of the memristor; R L is the low-resistance state resistance value of the memristor.

[0038] Further preferably, when the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, and d is 0 or 1;

[0039] When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, and d is 0 or 1;

[0040] When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, and d is 0 or 1;

[0041] When the Boolean logic operation is a q logic operation, a is 0, c is q, b is 0 or 1, and d is 1;

[0042] When the Boolean logic operation is a non-p logic operation, a is the logical value non-p, c is 0, b is 1, and d is 0 or 1;

[0043] When the Boolean logic operation is a NOT-q logic operation, a is 0, c is the logical value NOT-q, b is 0 or 1, and d is 1;

[0044] When the Boolean logic operation is an AND logic operation of logical values p and q, a is p, c is 0, b is q, and d is 0 or 1;

[0045] When the Boolean logic operation is a NAND logic operation of logical values p and q, a is the logical value NOT-p, c is the logical value NOT-q, b is 1, and d is 1;

[0046] When the Boolean logic operation is an OR logic operation of logical values p and q, a is p, c is q, b is 1, and d is 1;

[0047] When the Boolean logic operation is a NOR logic operation of logical values p and q, a is the logical value NOT-p, c is 0, b is the logical value NOT-q, and d is 0 or 1;

[0048] When the Boolean logic operation is a material implication logic operation of logical values p and q, a is the logical value NOT-p, c is q, b is 1, and d is 1;

[0049] When the Boolean logic operation is a negative material implication logic operation of logical values p and q, a is p, c is 0, b is the logical value NOT-q, and d is 0 or 1;

[0050] When the Boolean logic operation is a reverse material implication logic operation of logical values p and q, a is p, c is the logical value NOT-q, b is 1, and d is 1;

[0051] When the Boolean logic operation is a reverse negative material implication logic operation of logical values p and q, a is the logical value NOT-p, c is 0, b is q, and d is 0 or 1;

[0052] When the Boolean logic operation is an exclusive OR logic operation of logical values p and q, a is the logical value NOT-p, c is p, b is q, and d is the logical value NOT-q;

[0053] When the Boolean logic operation is an equivalence logic operation of logical values p and q, a is p, c is the logical value NOT-p, b is q, and d is the logical value NOT-q.

[0054] In a third aspect, the present invention provides a Boolean logic operation device, including: a controller and the Boolean logic circuit provided in the first aspect of the present invention;

[0055] The controller is configured to execute the control method provided in the second aspect of the present invention.

[0056] Fourthly, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it executes the control method provided in the second aspect of the present invention.

[0057] Fifthly, the present invention further provides a computer-readable storage medium, which includes a stored computer program. When the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method provided in the second aspect of the present invention.

[0058] Sixthly, the present invention also provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, they implement the control method provided in the second aspect of the present invention.

[0059] Generally speaking, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0060] 1. The present invention provides a Boolean logic circuit based on memristors, including a memristor M1, a memristor M2, a first NMOS transistor, a second NMOS transistor, a resistor, and a voltage comparator. By applying voltages V r to the control terminals T1 and T2 respectively, applying the gate voltage corresponding to the logic value a to the gate of the first transistor, applying the gate voltage corresponding to the logic value c to the gate of the second transistor, and grounding the control terminal T3, the corresponding Boolean logic operation result can be obtained at the output terminal of the voltage comparator. Among them, V ref and V r satisfy: (R H +R L )V r / (2R H +R L )<V ref <2V r / 3, which ensures the correct execution of logical operations and the accuracy of the read results. The present invention makes full use of the resistance state characteristics of memristors and the switching characteristics of transistors. By setting the values of the logical values a, b, c, and d, any Boolean logic operation can be realized with fewer operation steps, the operation is relatively simple, and the implementation of complete Boolean logic operations is supported.

[0061] 2. In the operation process of logical calculation of the Boolean logic circuit provided by the present invention, the resistance states of the memristor M1 and the memristor M2 do not change, and the whole operation process is non-destructive, which is beneficial to protecting the integrity of the input information.

[0062] 3. The Boolean logic circuit provided by the present invention requires fewer operation steps, has a faster operation speed, lower operation power consumption, and has a simplified peripheral circuit configuration. It is suitable for applications in memory computing and the design of digital logic units. At the same time, it is easy to cascade, has significant parallel computing advantages, and supports large-scale parallel computing. Description of the Drawings

[0063] Figure 1 It is a schematic diagram of the result of a memristor-based Boolean logic circuit provided by an embodiment of the present invention. Detailed Embodiments

[0064] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0065] To achieve the above objective, in a first aspect, the present invention provides a memristor-based Boolean logic circuit, as Figure 1 shown, including: a memristor M1, a memristor M2, a first NMOS transistor N1, a second NMOS transistor N2, a resistor R, and a voltage comparator SA;

[0066] The positive electrode of the memristor M1 serves as the T1 control terminal, and the negative electrode is connected to the source electrode of the first NMOS transistor; the positive electrode of the memristor M2 serves as the T2 control terminal, and the negative electrode is connected to the source electrode of the second NMOS transistor; the gate electrode of the first NMOS transistor is connected to the word line WL1; the gate electrode of the second NMOS transistor is connected to the word line WL2; the drain electrodes of the first NMOS transistor and the second NMOS transistor are both connected to one end of the resistor, and the other end of the resistor serves as the T3 control terminal; the positive terminal of the voltage comparator is connected to the common node of the memristor M1, the memristor M2, and the resistor, and the negative terminal is connected to the reference voltage V ref ; the first transistor and the second transistor are the same; the memristor M1 and the memristor M2 are the same; the resistance value of the resistor is the low-resistance state resistance value of the memristor;

[0067] When performing a Boolean logic operation, the memristor M1 is used to store the logic value b; the negative terminal of the voltage comparator is used to connect to the reference voltage V ref ; the memristor M2 is used to store the logic value d; the T1 control terminal and the T2 control terminal are respectively used to connect to the voltage V r ; the gate electrode of the first transistor is used to connect to the gate voltage corresponding to the logic value a; the gate electrode of the second transistor is used to connect to the gate voltage corresponding to the logic value c; the T3 control terminal is used to connect to the ground; the output terminal of the voltage comparator is used to output the corresponding Boolean logic operation result.

[0068] Among them, the memristor includes two resistance states, namely the high resistance state and the low resistance state, and the corresponding resistance values are R H and R L respectively; among them, the high resistance state of the memristor corresponds to the logical value 0, and the low resistance state of the memristor corresponds to the logical value 1. When the positive voltage value applied across the memristor is greater than V set , the memristor can be changed from the high resistance state to the low resistance state (i.e., the Set process of the memristor); conversely, when a reverse voltage with an absolute value greater than |V reset | is applied across the memristor, the memristor can be changed from the high resistance state to the low resistance state (i.e., the Reset process of the memristor). Specifically, in an optional implementation manner, the average values of V set and V reset of the memristor are 0.6V and -1.2V respectively, the high resistance state resistance value R H = 100 kΩ, the low resistance state resistance value R L = 1 kΩ, and the resistance value R = 1 kΩ.

[0069] The Boolean logic circuit provided by the present invention can be regarded as composed of two 1T1R units. By defining the input of this structure, all Boolean logics can be represented, which is a complete and reconfigurable logic set. In an optional implementation manner, the input and output definitions of the Boolean logic circuit are shown in Table 1:

[0070]

[0071] It should be noted that the gate voltage corresponding to the logical value 0 is the voltage V G less than the transistor turn-on voltage, and the gate voltage corresponding to the logical value 1 is the voltage V DD greater than or equal to the transistor turn-on voltage. When a voltage V G is applied to the gate of the transistor, the transistor is not conducting; when a voltage V DD is applied to the gate of the transistor, the transistor is conducting. Usually, V G is 0V, corresponding to the operation of grounding the transistor gate. For the input logic variables p or q, in positive logic (i.e., the Boolean logic operation does not involve taking the inverse of p or q), when the gate voltage (WL1 or WL2) of the NMOS transistor (N1 or N2) is grounded, it represents the logical value "0"; when the gate voltage (WL1 or WL2) of the NMOS transistor (N1 or N2) is connected to a fixed voltage V DDWhen the time represents the logical value "1"; when the resistance state of the memristor (M1 or M2) is the high-resistance state, it represents the logical value "0"; when the resistance state of the memristor (M1 or M2) is the low-resistance state, it represents the logical value "1". For the input logical variables p or q, when performing the inverse logic (involving taking the inverse of p or q), when the gate voltage (WL1 or WL2) of the NMOS transistor (N1 or N2) is grounded, it represents the logical value "1"; when the gate voltage (WL1 or WL2) of the NMOS transistor (N1 or N2) is connected to the fixed voltage V DD When it represents the logical value "0"; when the resistance state of the memristor (M1 or M2) is the high-resistance state, it represents the logical value "1"; when the resistance state of the memristor (M1 or M2) is the low-resistance state, it represents the logical value "0". For the output variable V o , V o When it is at a low level, it represents the output logical value "0"; when V o When it is at a high level, it represents the output logical value "1".

[0072] The positive terminal of the voltage comparator is connected to the voltage V at the common node of the memristor M1, the memristor M2, and the resistor. V cond will change according to the change of the resistance values of the memristor M1 and the memristor M2. To ensure the correct execution of the logical operation and correctly read the result, V ref and V r Satisfy the following relationship: (R H +R L )V r / (2R H +R L )<V ref <2V r / 3. Preferably, in an alternative embodiment, the switching ratio of the memristor is greater than or equal to 100. It should be noted that the switching ratio of the memristor directly affects the resistance state change window of the memristor in the output column. The larger the switching ratio, the larger the resistance state change window of the memristor in the output column. When the switching ratio is greater than or equal to 100, the memristor in the output column can more accurately achieve the resistance state change, thereby further improving the calculation accuracy. At this time, the above relationship can be further simplified to: 101V r / 201<V ref <2V r / 3.

[0073] The Boolean logic circuit provided by the present invention is a four-input logic circuit, and the output result is the result of the AND-OR combination of the four inputs. The expression is: o = ab + cd. By setting the values of the logical values a, b, c, and d, the four variables can be dimensionally reduced to achieve a complete Boolean logic operation.

[0074] Specifically, in an alternative embodiment, when the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, and d is 0 or 1;

[0075] When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, and d is 0 or 1;

[0076] When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, and d is 0 or 1;

[0077] When the Boolean logic operation is a q logic operation, a is 0, c is q, b is 0 or 1, and d is 1;

[0078] When the Boolean logic operation is a non-p logic operation, a is the logical value non-p, c is 0, b is 1, and d is 0 or 1;

[0079] When the Boolean logic operation is a non-q logic operation, a is 0, c is the logical value non-q, b is 0 or 1, and d is 1;

[0080] When the Boolean logic operation is a logical AND operation of logical values p and q, a is p, c is 0, b is q, and d is 0 or 1;

[0081] When the Boolean logic operation is a logical NAND operation of logical values p and q, a is the logical value non-p, c is the logical value non-q, b is 1, and d is 1;

[0082] When the Boolean logic operation is a logical OR operation of logical values p and q, a is p, c is q, b is 1, and d is 1;

[0083] When the Boolean logic operation is a logical NOR operation of logical values p and q, a is the logical value non-p, c is 0, b is the logical value non-q, and d is 0 or 1;

[0084] When the Boolean logic operation is a material implication logical operation of logical values p and q, a is the logical value non-p, c is q, b is 1, and d is 1;

[0085] When the Boolean logic operation is a negative material implication logical operation of logical values p and q, a is p, c is 0, b is the logical value non-q, and d is 0 or 1;

[0086] When the Boolean logic operation is a converse non-implication logical operation of logical values p and q, a is p, c is the logical value non-q, b is 1, and d is 1;

[0087] When the Boolean logic operation is a negative converse non-implication logical operation of logical values p and q, a is the logical value non-p, c is 0, b is q, and d is 0 or 1;

[0088] When the Boolean logic operation is an exclusive OR logical operation of logical values p and q, a is the logical value non-p, c is p, b is q, and d is the logical value non-q;

[0089] When the Boolean logic operation is the exclusive-NOR logic operation of logical values p and q, a is p, c is the logical value NOT p, b is q, and d is the logical value NOT q.

[0090] In a second aspect, the present invention provides a control method for the above-mentioned Boolean logic circuit, including:

[0091] An initialization memristor operation performed before the actual Boolean logic operation:

[0092] Write the logical value b into the memristor M1 so that the logical value b is stored in the memristor M1; write the logical value d into the memristor M2 so that the logical value d is stored in the memristor M2. In an alternative embodiment, the corresponding logical value is written by setting the high and low resistance states of the memristor; wherein, the high resistance state of the memristor corresponds to the logical value 0, and the low resistance state corresponds to the logical value 1.

[0093] Specifically, in an alternative embodiment, the above-mentioned writing the logical value b into the memristor M1 includes:

[0094] When b is 0, ground the control terminal of T1, set the control terminal of T2 to the floating state, connect a fixed voltage V q to the control terminal of T3, and apply a fixed voltage V DD for transistor gating to the gates of the first transistor and the second transistor. At this time, the memristor M1 realizes the Reset process and becomes the high resistance state, thereby writing the logical value 0 into the memristor M1.

[0095] When b is 1, connect a fixed voltage V p to the control terminal of T1, set the control terminal of T2 to the floating state, ground the control terminal of T3, and apply a fixed voltage V DD for transistor gating to the gates of the first transistor and the second transistor. At this time, the memristor M1 realizes the set process and becomes the low resistance state, thereby writing the logical value 1 into the memristor M1.

[0096] In an alternative embodiment, writing the logical value d into the memristor M2 includes:

[0097] When d is 0, set the control terminal of T1 to the floating state, ground the control terminal of T2, connect a fixed voltage V q to the control terminal of T3, and apply a fixed voltage V DD for transistor gating to the gates of the first transistor and the second transistor. At this time, the memristor M2 realizes the Reset process and becomes the high resistance state, writing the logical value 0 into the memristor M2.

[0098] When d is 1, set the control terminal of T1 to the floating state, connect a fixed voltage V p, ground the T3 control terminal, and apply a fixed voltage V for gating the transistors to the gates of the first and second transistors DD , at this time, the memristor M2 implements the set process and becomes a low-resistance state, and a logic value 1 is written in the memristor M2.

[0099] It should be noted that in order to ensure that the input information on the memristors M1 and M2 can be written normally, it is necessary to satisfy: V q > 2|V reset |; V p > (R H + R L )V set / R H ; where V reset is the threshold value for the memristor to change from the low-resistance state to the high-resistance state; V set is the threshold value for the memristor to change from the high-resistance state to the low-resistance state; R H is the high-resistance state resistance value of the memristor; R L is the low-resistance state resistance value of the memristor.

[0100] Preferably, in an alternative embodiment, according to the limitation of the above operation voltage value range, combined with the relationship between V set and V reset of the actually used memristor, select V p = 1.2V set ; V q = 2.2|V reset |; V ref = 0.6V r ; V r = 0.4V.

[0101] Actual Boolean logic operation:

[0102] Apply voltages V r to the T1 control terminal and the T2 control terminal respectively, apply the gate voltage corresponding to the logic value a to the gate of the first transistor, apply the gate voltage corresponding to the logic value c to the gate of the second transistor, ground the T3 control terminal, and read the corresponding Boolean logic operation result at the output terminal of the voltage comparator.

[0103] Among them, the negative terminal of the voltage comparator is connected with a reference voltage V ref ; V ref and V r satisfy: (R H + R L )V r / (2R H + R L ) <V ref < 2V r / 3; R Hand R L are the high - resistance state resistance value and the low - resistance state resistance value of the memristor respectively; the gate voltage corresponding to the logical value 0 is the voltage V less than the transistor turn - on voltage G , and the gate voltage corresponding to the logical value 1 is the voltage V greater than or equal to the transistor turn - on voltage DD .

[0104] In the present invention, the expression of the Boolean logic operation result is: o = ab+cd. By setting the values of the logical values a, b, c, and d, a complete Boolean logic operation can be achieved. Specifically, a reference voltage V is applied to the negative terminal of the voltage comparator ref , voltages V are applied to the control terminals of T1 and T2 respectively r , the control terminal of T3 is grounded. When a = 0 and c = 0, the gates of the NMOS transistors N1 and N2 are both connected to the fixed voltage V G . When a = 1 and c = 0, the gate of the NMOS transistor N1 is connected to the fixed voltage V DD , and the gate of the NMOS transistor N2 is connected to the fixed voltage V G . When a = 0 and c = 1, the gate of the NMOS transistor N1 is connected to the fixed voltage V G , and the gate of the NMOS transistor N2 is connected to the fixed voltage V DD . When a = 1 and c = 1, the gates of the NMOS transistor N1 and the NMOS transistor N2 are both connected to the fixed voltage V DD . The corresponding Boolean logic operation result is obtained at the output terminal of the voltage comparator

[0105] The specific voltage configuration is shown in Table 2

[0106]

[0107] The related technical solutions are the same as the Boolean logic circuit provided in the first aspect of the present invention, and will not be elaborated here

[0108] In order to make the technical solutions and advantages of the present invention clearer and more understandable, in an alternative embodiment, an operation table for realizing 16 kinds of Boolean logics in one step based on the memristor - based four - input logic scheme as shown in Table 3 is provided. In this embodiment, V G is a voltage with an amplitude of 0, corresponding to the operation of grounding the transistor gate

[0109]

[0110] The specific operations are as follows

[0111] When the Boolean logic operation is a true logic operation, the logical expression is 1. At this time, a = 1, c = 0 or 1, b = 1, d = 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to the low resistance state, and the memristor M2 is pre-set to the high resistance state or the low resistance state, which is not limited here. When performing the Boolean logic operation, voltages V are respectively applied to the T1 control terminal and the T2 control terminal r , the T3 control terminal is grounded, a fixed voltage V is applied to the gate of the first transistor DD , a voltage with an amplitude of 0 or a fixed voltage V is applied to the gate of the second transistor DD , which is not limited here. At this time, the current flowing through the fixed-value resistor R is large, and V cond > V ref . The voltage output by the voltage comparator is at a high level, that is, the logic operation result is always 1, realizing the true logic.

[0112] When the Boolean logic operation is a false logic operation, the logical expression is 0. At this time, a is 0, c is 0, b is 0 or 1, d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to the high resistance state or the low resistance state, and the memristor M2 is pre-set to the high resistance state or the low resistance state, which is not limited here. When performing the Boolean logic operation, voltages V are respectively applied to the T1 control terminal and the T2 control terminal r , the T3 control terminal is grounded, and the gates of the first transistor and the second transistor are grounded. At this time, the current flowing through the fixed-value resistor R is small, and V cond <V ref . The voltage output by the voltage comparator is at a low level, that is, the logic operation result is always 0, realizing the false logic.

[0113] When the Boolean logic operation is a p logic operation, the logical expression is p. At this time, a is p, c is 0, b is 1, d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to the low resistance state, and the memristor M2 is pre-set to the high resistance state or the low resistance state, which is not limited here. When performing the Boolean logic operation, voltages V are respectively applied to the T1 control terminal and the T2 control terminal r , the T3 control terminal is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the first transistor DD , and the gate of the second transistor is grounded; at this time, the current flowing through the fixed-value resistor R changes according to the input logical value p, thereby affecting the relationship between V cond and V ref . When p is 0, V cond <V ref . The voltage output by the voltage comparator is at a low level, that is, the logic operation result is 0; when p is 1, V cond >Vref When this occurs, the voltage output by the voltage comparator is at a high level, that is, the result of the logical operation is 1. Thus, the p logical operation is achieved, and the result of the Boolean logical operation is p.

[0114] When the Boolean logical operation is a q logical operation, the logical expression is q. At this time, a is 0, c is q, b is 0 or 1, and d is 1. Specifically, before performing the Boolean logical operation, the memristor M1 is pre-set to a high resistance state or a low resistance state, which is not limited here; the memristor M2 is pre-set to a low resistance state. When performing the Boolean logical operation, voltages V are applied to the control terminals of T1 and T2 respectively r , the control terminal of T3 is grounded, the gate of the first transistor is grounded, and when q is 0, the gate of the second transistor is grounded, and when q is 1, a fixed voltage V is applied to the gate of the second transistor DD , at this time, the current flowing through the fixed-value resistor R changes according to the input logical value q, thereby affecting V cond and V ref , when q is 0, V cond < V ref , the voltage output by the voltage comparator is at a low level, that is, the result of the logical operation is 0; when q is 1, V cond > V ref , the voltage output by the voltage comparator is at a high level, that is, the result of the logical operation is 1; thus, the q logical operation is achieved, and the result of the Boolean logical operation is q.

[0115] When the Boolean logical operation is a non-p logical operation, the logical expression is , at this time, a is the logical value non-p, c is 0, b is 1, and d is 0 or 1. Specifically, before performing the Boolean logical operation, the memristor M1 is pre-set to a low resistance state, and the memristor M2 is pre-set to a high resistance state or a low resistance state, which is not limited here. When performing the Boolean logical operation, voltages V are applied to the control terminals of T1 and T2 respectively r , the control terminal of T3 is grounded, and when p is 0 (non-p is 1), a fixed voltage V DD is applied to the gate of the first transistor, when p is 1 (non-p is 0), the gate of the first transistor is grounded, and the gate of the second transistor is grounded; at this time, the current flowing through the fixed-value resistor R changes according to the input logical value p, thereby affecting V cond and V ref , when p is 1, V cond < V ref , the voltage output by the voltage comparator is at a low level, that is, the result of the logical operation is 0; when p is 0, V cond > V refWhen the voltage comparator outputs a high voltage level, that is, the logical operation result is 1. Thus, the NOT p logical operation is realized, and the Boolean logical operation result is .

[0116] When the Boolean logical operation is the NOT q logical operation, the logical expression is . At this time, a is 0, c is the logical value NOT q, b is 0 or 1, and d is 1. Specifically, before performing the Boolean logical operation, the memristor M1 is pre-set to a high resistance state or a low resistance state, which is not limited here; the memristor M2 is pre-set to a low resistance state. When performing the Boolean logical operation, voltages V r are respectively applied to the control terminals of T1 and T2, the control terminal of T3 is grounded, the gate of the first transistor is grounded, and when q is 0 (NOT q is 1), a fixed voltage V DD is applied to the gate of the second transistor. When p is 1 (NOT p is 0), the gate of the second transistor is grounded. At this time, the current flowing through the fixed value resistor R changes according to the change of the input logical value q, thereby affecting the magnitude relationship between V cond and V ref . When q is 1, V cond < V ref , and the voltage output by the voltage comparator is a low voltage level, that is, the logical operation result is 0; when q is 0, V cond > V ref when the voltage output by the voltage comparator is a high voltage level, that is, the logical operation result is 1. Thus, the NOT q logical operation is realized, and the Boolean logical operation result is .

[0117] When the Boolean logical operation is the AND logical operation of logical values p and q, the logical expression is pq. At this time, a is p, c is 0, b is q, and d is 0 or 1. Specifically, before performing the Boolean logical operation, the memristor M1 is pre-set to a resistance state corresponding to the logical value q. When q is 0, the memristor M1 is pre-set to a high resistance state. When q is 1, the memristor M1 is pre-set to a low resistance state; the memristor M2 is pre-set to a high resistance state or a low resistance state, which is not limited here. When performing the Boolean logical operation, voltages V r are respectively applied to the control terminals of T1 and T2, the control terminal of T3 is grounded, and when p is 0, the gate of the first transistor is grounded. When p is 1, a fixed voltage V DD is applied to the gate of the first transistor, and the gate of the second transistor is grounded; at this time, the current flowing through the fixed value resistor R changes according to the change of the input logical value pq, thereby affecting the magnitude relationship between V cond and V ref . When pq is 0, V cond < V ref, the voltage output by the voltage comparator is at a low level, that is, the logical operation result is 0; when pq is 1, V cond > V ref , the voltage output by the voltage comparator is at a high level, that is, the logical operation result is 1. Thus, the AND logical operation is realized, and the Boolean logical operation result is pq.

[0118] When the Boolean logical operation is the NAND logical operation of logical values p and q, the logical expression is , at this time, a is the logical value not p, c is the logical value not q, b is 1, and d is 1. Specifically, before performing the Boolean logical operation, both the memristor M1 and the memristor M2 are pre-set to the low-resistance state. When performing the Boolean logical operation, voltages V r are respectively applied to the T1 control terminal and the T2 control terminal, the T3 control terminal is grounded, and when p is 1 (not p is 0), the gate of the first transistor is grounded, and when p is 0 (not p is 1), a fixed voltage V DD is applied to the gate of the first transistor. When q is 1 (not q is 0), the gate of the second transistor is grounded, and when q is 0 (not q is 1), a fixed voltage V DD is applied to the gate of the second transistor; at this time, the current flowing through the fixed-value resistor R changes according to the input logical value , thereby affecting the magnitude relationship between V cond and V ref . When is 0, V cond < V ref , the voltage output by the voltage comparator is at a low level, that is, the logical operation result is 0; when is 1, V cond > V ref , the voltage output by the voltage comparator is at a high level, that is, the logical operation result is 1. Thus, the NAND logical operation is realized, and the Boolean logical operation result is .

[0119] When the Boolean logical operation is the OR logical operation of logical values p and q, the logical expression is p + q. At this time, a is p, c is q, b is 1, and d is 1. Specifically, before performing the Boolean logical operation, both the memristor M1 and the memristor M2 are pre-set to the low-resistance state. When performing the Boolean logical operation, voltages V r are respectively applied to the T1 control terminal and the T2 control terminal, the T3 control terminal is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V DD is applied to the gate of the first transistor. When q is 0, the gate of the second transistor is grounded, and when q is 1, a fixed voltage V DD; At this time, the current flowing through the fixed-value resistor R changes according to the change of the input logic value p + q, thereby affecting V cond and V ref The magnitude relationship of, when p + q is 0, V cond <V ref , the voltage output by the voltage comparator is low level, that is, the logical operation result is 0; when a + b is 1, V cond >V ref , the voltage output by the voltage comparator is high level, that is, the logical operation result is 1. Thus, the OR logical operation is realized, and the Boolean logical operation result is p + q.

[0120] When the Boolean logical operation is the NOR logical operation of logical values p and q, the logical expression is , at this time, a is the logical value NOT p, c is 0, b is the logical value NOT q, and d is 0 or 1. Specifically, before the Boolean logical operation is performed, the memristor M1 is pre-set to the resistance state corresponding to the logical value NOT q. When q is 1 (NOT q is 0), the memristor M1 is pre-set to the high-resistance state. When q is 0 (NOT q is 1), the memristor M1 is pre-set to the low-resistance state; the memristor M2 is pre-set to the high-resistance state or the low-resistance state, which is not limited here. When performing the Boolean logical operation, voltages V r are applied to the T1 control terminal and the T2 control terminal respectively, the T3 control terminal is grounded, and when p is 1 (NOT p is 0), the gate of the first transistor is grounded. When p is 0 (NOT p is 1), a fixed voltage V DD is applied to the gate of the first transistor, and the gate of the second transistor is grounded; at this time, the current flowing through the fixed-value resistor R changes according to the input logical value changes, thereby affecting V cond and V ref The magnitude relationship of, when is 0, V cond <V ref , the voltage output by the voltage comparator is low level, that is, the logical operation result is 0; when is 1, V cond >V ref , the voltage output by the voltage comparator is high level, that is, the logical operation result is 1. Thus, the NOR logical operation is realized, and the Boolean logical operation result is .

[0121] When the Boolean logical operation is the material implication logical operation of logical values p and q, the logical expression is , at this time, a is the logical value NOT p, c is q, b is 1, and d is 1. Specifically, before the Boolean logical operation is performed, both the memristor M1 and the memristor M2 are pre-set to the low-resistance state. When performing the Boolean logical operation, voltages V are applied to the T1 control terminal and the T2 control terminal respectivelyr Ground the control terminal of T3, and when p = 1 (¬p = 0), ground the gate of the first transistor; when p = 0 (¬p = 1), apply a fixed voltage V to the gate of the first transistor. DD When q = 0, ground the gate of the second transistor; when q = 1, apply a fixed voltage V to the gate of the second transistor. DD At this time, the current flowing through the fixed-value resistor R changes according to the input logic value , thereby affecting the magnitude relationship between V cond and V ref . When = 0, V cond < V ref , and the voltage output by the voltage comparator is at a low level, that is, the logical operation result is 0; when = 1, V cond > V ref , the voltage output by the voltage comparator is at a high level, that is, the logical operation result is 1. Thus, the material implication logical operation is realized, and the Boolean logical operation result is .

[0122] When the Boolean logical operation is the negative material implication logical operation of logical values p and q, the logical expression is . At this time, a is p, c is 0, b is the logical value ¬q, and d is 0 or 1. Specifically, before performing the Boolean logical operation, the memristor M1 is pre-set to a resistance state corresponding to the logical value ¬q. When q = 1 (¬q = 0), the memristor M1 is pre-set to a high resistance state; when q = 0 (¬q = 1), the memristor M1 is pre-set to a low resistance state. The memristor M2 is pre-set to a high resistance state or a low resistance state, which is not limited here. When performing the Boolean logical operation, apply voltage V r to the control terminals of T1 and T2 respectively, ground the control terminal of T3, and when p = 0, ground the gate of the first transistor; when p = 1, apply a fixed voltage V DD to the gate of the first transistor, and ground the gate of the second transistor. At this time, the current flowing through the fixed-value resistor R changes according to the input logic value , thereby affecting the magnitude relationship between V cond and V ref . When = 0, V cond < V ref , the voltage output by the voltage comparator is at a low level, that is, the logical operation result is 0; when = 1, V cond > V ref , the voltage output by the voltage comparator is at a high level, that is, the logical operation result is 1. Thus, the negative material implication logical operation is realized, and the Boolean logical operation result is .

[0123] When the Boolean logic operation is the anti-material implication logic operation of logical values p and q, the logical expression is , at this time, a is p, c is the logical value not q, b is 1, and d is 1. Specifically, before performing the Boolean logic operation, both the memristor M1 and the memristor M2 are pre-set to the low-resistance state. When performing the Boolean logic operation, voltages V are respectively applied to the T1 control terminal and the T2 control terminal r , the T3 control terminal is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the first transistor DD , when q is 1 (not q is 0), the gate of the second transistor is grounded, and when q is 0 (not q is 1), a fixed voltage V is applied to the gate of the second transistor DD ; at this time, the current flowing through the fixed-value resistor R changes according to the input logical value , thereby affecting the magnitude relationship between V cond and V ref . When is 0, V cond < V ref , the voltage output by the voltage comparator is at a low level, that is, the logical operation result is 0; when is 1, V cond > V ref , the voltage output by the voltage comparator is at a high level, that is, the logical operation result is 1. Thus, the anti-material implication logic operation is realized, and the Boolean logic operation result is .

[0124] When the Boolean logic operation is the anti-negative material implication logic operation of logical values p and q, the logical expression is , at this time, a is the logical value not p, c is 0, b is q, and d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to the resistance state corresponding to the logical value q. When q is 0, the memristor M1 is pre-set to the high-resistance state, and when q is 1, the memristor M1 is pre-set to the low-resistance state; the memristor M2 is pre-set to the high-resistance state or the low-resistance state, which is not limited here. When performing the Boolean logic operation, voltages V are respectively applied to the T1 control terminal and the T2 control terminal r , the T3 control terminal is grounded, and when p is 1 (not p is 0), the gate of the first transistor is grounded, and when p is 0 (not p is 1), a fixed voltage V is applied to the gate of the first transistor DD , the gate of the second transistor is grounded; at this time, the current flowing through the fixed-value resistor R changes according to the input logical value , thereby affecting the magnitude relationship between V cond and V ref . When When it is 0, V cond <V ref , the voltage output by the voltage comparator is at a low level, that is, the result of the logical operation is 0; when is 1, V cond >V ref , the voltage output by the voltage comparator is at a high level, that is, the result of the logical operation is 1. Thus, the anti-negative material implication logical operation is realized, and the Boolean logical operation result is .

[0125] When the Boolean logical operation is the exclusive OR logical operation of logical values p and q, the logical expression is , at this time, a is the logical value not p, c is p, b is q, and d is the logical value not q. Specifically, before performing the Boolean logical operation, the memristor M1 is pre-set to a resistance state corresponding to the logical value q. When q is 0, the memristor M1 is pre-set to a high resistance state, and when q is 1, the memristor M1 is pre-set to a low resistance state; the memristor M2 is pre-set to a resistance state corresponding to the logical value not q. When q is 1 (not q is 0), the memristor M2 is pre-set to a high resistance state, and when q is 0 (not q is 1), the memristor M2 is pre-set to a low resistance state. When performing the Boolean logical operation, voltages V r are applied to the T1 control terminal and the T2 control terminal respectively, the T3 control terminal is grounded, and when p is 1 (not p is 0), the gate of the first transistor is grounded, and when p is 0 (not p is 1), a fixed voltage V DD is applied to the gate of the first transistor. When p is 0, the gate of the second transistor is grounded, and when p is 1, a fixed voltage V DD is applied to the gate of the second transistor; at this time, the current flowing through the fixed-value resistor R changes according to the input logical value , thereby affecting the magnitude relationship between V cond and V ref . When is 0, V cond <V ref , the voltage output by the voltage comparator is at a low level, that is, the result of the logical operation is 0; when is 1, V cond >V ref , the voltage output by the voltage comparator is at a high level, that is, the result of the logical operation is 1. Thus, the exclusive OR logical operation is realized, and the Boolean logical operation result is .

[0126] When the Boolean logical operation is the equivalence logical operation of logical values p and q, the logical expression is , at this time, a is p, c is the logical value NOT p, b is q, and d is the logical value NOT q. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to a resistance state corresponding to the logical value q. When q is 0, the memristor M1 is pre-set to a high resistance state, and when q is 1, the memristor M1 is pre-set to a low resistance state; the memristor M2 is pre-set to a resistance state corresponding to the logical value NOT q. When q is 1 (NOT q is 0), the memristor M2 is pre-set to a high resistance state, and when q is 0 (NOT q is 1), the memristor M2 is pre-set to a low resistance state. When performing the Boolean logic operation, voltages V are respectively applied to the T1 control terminal and the T2 control terminal r , the T3 control terminal is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the first transistor DD , and when p is 1 (NOT p is 0), the gate of the second transistor is grounded, and when p is 0 (NOT p is 1), a fixed voltage V is applied to the gate of the second transistor DD ; at this time, the current flowing through the fixed-value resistor R changes according to the input logical value , thereby affecting the magnitude relationship between V cond and V ref . When is 0, V cond < V ref , and the voltage output by the voltage comparator is a low level, that is, the logic operation result is 0; when is 1, V cond > V ref , and the voltage output by the voltage comparator is a high level, that is, the logic operation result is 1. Thus, the exclusive-NOR logic operation is realized, and the Boolean logic operation result is .

[0127] It uses fewer device numbers and operation steps, has a simple circuit structure, and can flexibly select the input variables to be retained for logic cascading in more complex application scenarios, which can lay a foundation for complex logic operations.

[0128] In a third aspect, the present invention provides a Boolean logic operation device, including: a controller and the Boolean logic circuit provided in the first aspect of the present invention;

[0129] The controller is used to execute the control method provided in the second aspect of the present invention.

[0130] The related technical solutions are the same as the Boolean logic circuit provided in the first aspect of the present invention and the control method provided in the second aspect of the present invention, and will not be elaborated here.

[0131] Fourthly, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it executes the control method provided in the second aspect of the present invention.

[0132] The related technical solutions are the same as the control method provided in the second aspect of the present invention, and will not be elaborated here.

[0133] Fifthly, the present invention further provides a computer-readable storage medium, which includes a stored computer program. When the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method provided in the second aspect of the present invention.

[0134] The related technical solutions are the same as the control method provided in the second aspect of the present invention, and will not be elaborated here.

[0135] Sixthly, the invention further provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, they implement the control method provided in the second aspect of the present invention.

[0136] The related technical solutions are the same as the control method provided in the second aspect of the present invention, and will not be elaborated here.

[0137] In summary, the present invention provides a method for realizing four-input reconfigurable logic based on memristors. Any one of the 16 complete Boolean logics can be completed within two steps under one operation scheme, and it is easy to cascade. At the same time, this method can implement large-scale parallel computing in a 1T1R array, and has great advantages in the process of implementing digital logic components such as full adders.

[0138] It is easy for those skilled in the art to understand that the above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A Boolean logic circuit based on a memristor, characterized in that: include: Memristor M1, memristor M2, a first transistor, a second transistor, a resistor and a voltage comparator; the memristor M1 is the same as the memristor M2; the first transistor and the second transistor are the same and are both NMOS transistors; the resistance value of the resistor is the low resistance value of the memristor; The positive electrode of the memristor M1 serves as the control terminal of T1, and the negative electrode is connected to the source of the first transistor; the positive electrode of the memristor M2 serves as the control terminal of T2, and the negative electrode is connected to the source of the second transistor; the drains of the first transistor and the second transistor are both connected to one end of the resistor, and the other end of the resistor serves as the control terminal of T3; the positive end of the voltage comparator is connected to the common node of the memristor M1, the memristor M2 and the resistor; When performing Boolean logic operations, the memristor M1 is used to store the logic value b; the negative terminal of the voltage comparator is used to access the reference voltage V ref ; Memristor M2 is used to store logic value d; T1 control terminal and T2 control terminal are respectively used to access voltage V r ; The gate of the first transistor is used to access the gate voltage corresponding to the logic value a; the gate of the second transistor is used to access the gate voltage corresponding to the logic value c; the T3 control terminal is used to be grounded; the output terminal of the voltage comparator is used to output the corresponding Boolean logic operation result; Among them, V ref and V r Satisfy: (R H +R L )V r / (2R H +R L ) < V ref <2V r / 3; R H and R L are the high resistance and low resistance of the memristor respectively; the gate voltage corresponding to the logic value 0 is the voltage V less than the transistor turn-on voltage G , the gate voltage corresponding to the logic value 1 is greater than or equal to the transistor turn-on voltage V DD .

2. The Boolean logic circuit according to claim 1, characterized in that: When the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, and d is 0 or 1; When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, and d is 0 or 1; When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is q logic operation, a is 0, c is q, b is 0 or 1, and d is 1; When the Boolean logic operation is a non-p logic operation, a is a logical value non-p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is a non-q logic operation, a is 0, c is a logical value non-q, b is 0 or 1, and d is 1; When the Boolean logic operation is the AND operation of logical values ​​p and q, a is p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the AND-NOT logic operation of logical values ​​p and q, a is the logical value not p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the OR operation of logical values ​​p and q, a is p, c is q, b is 1, and d is 1; When the Boolean logic operation is a logical value p, q or a not logical operation, a is a logical value not p, c is 0, b is a logical value not q, and d is 0 or 1; When the Boolean logic operation is a substantial implied logic operation of logical values ​​p and q, a is the logical value not p, c is q, b is 1, and d is 1; When the Boolean logic operation is a negative substantial implication logic operation of logical values ​​p and q, a is p, c is 0, b is logical value not q, and d is 0 or 1; When the Boolean logic operation is the inverse substantial implication logic operation of the logical values ​​p and q, a is p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the negative substantive implied logic operation of the logical values ​​p and q, a is the logical value not p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is the logical value not p, c is p, b is q, and d is the logical value not q; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is p, c is the logical value not p, b is q, and d is the logical value not q.

3. A control method for a Boolean logic circuit, characterized in that: The Boolean logic circuit is the Boolean logic circuit according to claim 1; the control method comprises a Boolean logic operation: applying a voltage V to the T1 control terminal and the T2 control terminal of the Boolean logic circuit respectively r , applying a gate voltage corresponding to a logic value a to the gate of the first transistor in the Boolean logic circuit, applying a gate voltage corresponding to a logic value c to the gate of the second transistor in the Boolean logic circuit, grounding the T3 control terminal of the Boolean logic circuit, and reading the corresponding Boolean logic operation result at the output terminal of the voltage comparator in the Boolean logic circuit; The memristor M1 in the Boolean logic circuit stores a logic value b, and the memristor M2 in the Boolean logic circuit stores a logic value d; the negative terminal of the voltage comparator in the Boolean logic circuit is connected to a reference voltage V ref ; V ref and V r Satisfy: (R H +R L )V r / (2R H +R L ) < V ref <2V r / 3; R H and R L are the high resistance and low resistance of the memristor respectively; the gate voltage corresponding to the logic value 0 is the voltage V less than the transistor turn-on voltage G , the gate voltage corresponding to the logic value 1 is greater than or equal to the transistor turn-on voltage V DD .

4. The control method according to claim 3, characterized in that: Also includes: an initialization memristor operation performed before the Boolean logic operation; The memristor initialization operation includes: writing a logic value b in the memristor M1; writing a logic value d in the memristor M2; The corresponding logic value is written by setting the high and low resistance states of the memristor; the high resistance state of the memristor corresponds to a logic value of 0, and the low resistance state corresponds to a logic value of 1.

5. The control method according to claim 4, characterized in that: Writing the logic value b into the memristor M1 comprises: When b is 0, the T1 control terminal is grounded, the T2 control terminal is set to a suspended state, and a fixed voltage V is connected to the T3 control terminal. q , V is applied to the gates of the first transistor and the second transistor DD , thereby writing a logic value b into the memristor M1; When b is 1, a fixed voltage V is connected to the control terminal of T1. p , set the T2 control terminal to a floating state, ground the T3 control terminal, and apply V to the gates of the first transistor and the second transistor. DD , thereby writing a logic value b into the memristor M1; Among them, V q >2|V reset |;V p >(R H +R L )V set / R H ; V reset V is the threshold value of the memristor changing from a low resistance state to a high resistance state; set is the threshold value of the memristor changing from a high resistance state to a low resistance state; R H is the high-resistance resistance value of the memristor; R L is the low-resistance state resistance value of the memristor.

6. The control method according to claim 4, characterized in that: Writing the logic value d into the memristor M2 comprises: When d is 0, the T1 control terminal is set to a suspended state, the T2 control terminal is grounded, and a fixed voltage V is connected to the T3 control terminal. q , V is applied to the gates of the first transistor and the second transistor DD , write a logic value d into the memristor M2; When d is 1, the T1 control terminal is set to a suspended state, and a fixed voltage V is connected to the T2 control terminal. p , ground the control terminal of T3, and apply V to the gates of the first transistor and the second transistor. DD , write a logic value d into the memristor M2; Among them, V q >2|V reset |;V p >(R H +R L )V set / R H ; V reset V is the threshold value of the memristor changing from a low resistance state to a high resistance state; set is the threshold value of the memristor changing from a high resistance state to a low resistance state; R H is the high-resistance resistance value of the memristor; R L is the low-resistance state resistance value of the memristor.

7. The control method according to any one of claims 3 to 6, characterized in that: When the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, and d is 0 or 1; When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, and d is 0 or 1; When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is q logic operation, a is 0, c is q, b is 0 or 1, and d is 1; When the Boolean logic operation is a non-p logic operation, a is a logical value non-p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is a non-q logic operation, a is 0, c is a logical value non-q, b is 0 or 1, and d is 1; When the Boolean logic operation is the AND operation of logical values ​​p and q, a is p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the AND-NOT logic operation of logical values ​​p and q, a is the logical value not p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the OR operation of logical values ​​p and q, a is p, c is q, b is 1, and d is 1; When the Boolean logic operation is a logical value p, q or a not logical operation, a is a logical value not p, c is 0, b is a logical value not q, and d is 0 or 1; When the Boolean logic operation is a substantial implied logic operation of logical values ​​p and q, a is the logical value not p, c is q, b is 1, and d is 1; When the Boolean logic operation is a negative substantial implication logic operation of logical values ​​p and q, a is p, c is 0, b is logical value not q, and d is 0 or 1; When the Boolean logic operation is the inverse substantial implication logic operation of the logical values ​​p and q, a is p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the negative substantive implied logic operation of the logical values ​​p and q, a is the logical value not p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is the logical value not p, c is p, b is q, and d is the logical value not q; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is p, c is the logical value not p, b is q, and d is the logical value not q.

8. A Boolean logic operation device, characterized in that: include: A controller and a Boolean logic circuit as claimed in claim 1; The controller is used to execute the control method described in any one of claims 3-7.

9. A control system, characterized in that: include: A memory and a processor, wherein the memory stores a computer program, and the processor executes the control method according to any one of claims 3 to 7 when executing the computer program.

10. A computer program product, characterized in that The method comprises a computer program / instruction, which, when executed by a processor, implements the control method described in any one of claims 3 to 7.

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