Voltage controlled oscillator, phase locked loop, electronic device and vehicle

Abstract

The application discloses a voltage-controlled oscillator, a phase-locked loop, an electronic device and a vehicle. The voltage-controlled oscillator comprises a positive feedback gain unit, a capacitor array unit, a positive output port VCO_OP and a negative output port VCO_ON, and the two ends of the parallel connection of the positive feedback gain unit and the capacitor array unit are connected with the positive output port VCO_OP and the negative output port VCO_ON respectively. The positive feedback gain unit is used for ensuring the continuous oscillation of the voltage-controlled oscillator and allowing the oscillation frequency to be adjusted by an external voltage signal. The capacitor array unit is used for providing the voltage-controlled oscillator with a wide range of frequency tuning capability and compensating the frequency gain and the temperature coefficient of the voltage-controlled oscillator.

Description

Technical Field

[0001] This invention relates to the field of electronic and electrical technology, and in particular to a voltage-controlled oscillator, a phase-locked loop, electronic equipment, and a vehicle. Background Technology

[0002] A phase-locked loop (PLL) mainly consists of a phase detector (PFD), a charge pump (CP), a loop filter (LPF), and a voltage-controlled oscillator (VCO). It is a negative feedback control system that uses a voltage generated by phase synchronization to tune a VCO to produce a target frequency. Due to its unique frequency synthesis, synchronization, and phase detection functions, PLLs are widely used in many fields. With the continuous development of communication technology, the bandwidth requirements for PLLs are becoming increasingly stringent. The main factors affecting bandwidth are the frequency gain (Kvco) and temperature coefficient of the VCO. Therefore, how to ensure that the VCO has a constant frequency gain and temperature coefficient is a pressing issue.

[0003] In existing technologies, frequency gain and temperature coefficient are usually compensated to keep them constant. However, the compensation for frequency gain and temperature coefficient is carried out separately. This means that more components will be connected in the circuit. The more components connected, the worse the phase noise of the voltage-controlled oscillator will be, leading to a deterioration of the loop noise of the phase-locked loop. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a voltage-controlled oscillator, a phase-locked loop, an electronic device, and a vehicle that combine compensation for frequency gain and temperature coefficient, ensuring constant frequency gain and temperature coefficient while avoiding noise degradation caused by adding too many components.

[0005] To achieve the objectives of this invention, the following technical solution is adopted:

[0006] According to a first aspect of the present invention, a voltage-controlled oscillator is provided, comprising:

[0007] The system comprises a positive feedback gain unit, a capacitor array unit, a positive output port VCO_OP, and a negative output port VCO_ON. The two ends of the positive feedback gain unit and the capacitor array unit connected in parallel are respectively connected to the positive output port VCO_OP and the negative output port VCO_ON. The positive feedback gain unit is used to ensure the continuous oscillation of the voltage-controlled oscillator and allows the oscillation frequency to be adjusted by an external voltage signal. The capacitor array unit is used to provide the voltage-controlled oscillator with a wide range of frequency tuning capability and to compensate for the frequency gain and temperature coefficient of the voltage-controlled oscillator.

[0008] According to some embodiments of the present invention, the positive feedback gain unit includes a first P-type field-effect transistor MP1, a second P-type field-effect transistor MP2, a first N-type field-effect transistor MN1, and a second N-type field-effect transistor MN2;

[0009] The gate G of the first P-type field-effect transistor MP1 and the drain D of the second P-type field-effect transistor MP2 are connected to the negative output port VCO_ON, and the drain D of the first P-type field-effect transistor MP1 and the gate G of the second P-type field-effect transistor MP2 are connected to the positive output port VCO_OP. The source S of the first P-type field-effect transistor MP1 and the second P-type field-effect transistor MP2 are connected to the first power supply voltage VDD1. The gate G of the first N-type field-effect transistor MN1 and the drain D of the second N-type field-effect transistor MN2 are connected to the negative output port VCO_ON, and the drain D of the first N-type field-effect transistor MN1 and the gate G of the second N-type field-effect transistor MN2 are connected to the positive output port VCO_OP. The source S of the first N-type field-effect transistor MN1 and the second N-type field-effect transistor MN2 is grounded through the first variable resistor R_turn1.

[0010] According to some embodiments of the present invention, the capacitor array unit includes a variable capacitor array module, a fixed capacitor array module, and a bias voltage module. The variable capacitor array module and the fixed capacitor array module are connected in parallel, and their two ends are respectively connected to the positive terminal plus and the negative terminal minus of the capacitor array unit. The bias voltage module is connected to the variable capacitor array module to provide a bias voltage. The variable capacitor array module, the fixed capacitor array module, and the bias voltage module cooperate to provide a wide range of frequency coordination capability for the voltage-controlled oscillator, and to compensate for the frequency gain and temperature coefficient of the voltage-controlled oscillator.

[0011] According to some embodiments of the present invention, the variable capacitor array module has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal, and the fixed capacitor array module has a first terminal, a second terminal, and a third terminal; the node formed by connecting the second terminal of the variable capacitor array module and the second terminal of the fixed capacitor array module is the positive terminal plus, and the node formed by connecting the fifth terminal of the variable capacitor array module and the third terminal of the fixed capacitor array module is the negative terminal minus; the first terminal of the variable capacitor array module is connected to a selector MUX to receive a first control voltage Vctr1<7:0>; the third and fourth terminals of the variable capacitor array module are connected to the bias voltage module; and the first terminal of the fixed capacitor array module receives a second control word signal Band_sel<7:0>.

[0012] According to some embodiments of the present invention, the variable capacitor array module includes multiple variable capacitor branches, the multiple variable capacitor branches are connected in parallel, and each variable capacitor branch is controlled by the corresponding bit in the first control voltage Vctr1<7:0>, and the voltage connected to each variable capacitor branch is determined according to the value of the corresponding bit.

[0013] According to some embodiments of the present invention, the variable capacitor branch includes a first sub-branch, a second sub-branch, a third sub-branch, and a fourth sub-branch; node a, where the first sub-branch and the fourth sub-branch are connected, serves as the third terminal of the variable capacitor array module; node b, where the first sub-branch and the fourth sub-branch are connected, and node c, where the second sub-branch and the third sub-branch are connected, serve as the first terminal of the variable capacitor array module; node d, where the second sub-branch and the third sub-branch are connected, serves as the fourth terminal of the variable capacitor array module; node e, where the first sub-branch and the second sub-branch are connected, serves as the second terminal of the variable capacitor array module; and node f, where the third sub-branch and the fourth sub-branch are connected, serves as the fifth terminal of the variable capacitor array module.

[0014] According to some embodiments of the present invention, the fixed capacitor array module includes multiple fixed capacitor branches connected in parallel; each fixed capacitor branch includes a fifth DC blocking capacitor C5, a switch k, and a sixth DC blocking capacitor C6 connected in series, wherein the floating end of the fifth DC blocking capacitor C5 serves as the second end of the fixed capacitor array module, and the floating end of the sixth DC blocking capacitor C6 serves as the third end of the fixed capacitor array module.

[0015] According to some embodiments of the present invention, the bias voltage module includes a third P-type field-effect transistor MP3, a fourth P-type field-effect transistor MP4, an amplifier AMP1, a second variable resistor R_turn2, and a transistor Q1;

[0016] The sources S of the third P-type field-effect transistor MP3 and the fourth P-type field-effect transistor MP4 are connected to the second supply voltage VDD2. The gates G of the third P-type field-effect transistor MP3 and the fourth P-type field-effect transistor MP4 are connected to the output pin of amplifier AMP1. The drain D of the third P-type field-effect transistor MP3 is connected to the positive input pin of amplifier AMP1 and then grounded through the fifth resistor R5. The inverting input pin of amplifier AMP1 is connected to the reference voltage source Vbg. The drain D of the fourth P-type field-effect transistor MP4 serves as one output terminal of the bias voltage module 23, outputting the second bias voltage Vref2. The drain D of the fourth P-type field-effect transistor MP4 is connected to the emitter E of transistor Q1 through the second variable resistor R_turn2. The emitter E of transistor Q1 serves as the other output terminal of the bias voltage module 23, outputting the first bias voltage Vref1. The base B and collector C of transistor Q1 are grounded.

[0017] A second aspect of the present invention provides a phase-locked loop comprising the voltage-controlled oscillator described in any one of the first aspects.

[0018] A third aspect of the present invention provides an electronic device comprising a voltage-controlled oscillator as described in any one of the first aspects or a phase-locked loop as described in the second aspect.

[0019] A fourth aspect of the invention provides a vehicle including the electronic equipment described in the third aspect.

[0020] According to the technical solution provided by the present invention, at least the following beneficial effects are achieved: the voltage-controlled oscillator ensures continuous oscillation through a positive feedback gain unit; and the frequency gain and temperature coefficient compensation are combined through a capacitor array unit, which can effectively ensure the constant frequency gain and temperature coefficient without increasing the number of components and causing noise degradation.

[0021] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0023] Figure 1 This is a structural diagram of the voltage-controlled oscillator according to an embodiment of the present invention;

[0024] Figure 2 This is a circuit diagram of a voltage-controlled oscillator according to an embodiment of the present invention;

[0025] Figure 3 The CV characteristic curve of the variable capacitor branch in an embodiment of the present invention;

[0026] Figure 4 The circuit diagram and temperature characteristic curve of the bias voltage module are shown in the embodiment of the present invention.

[0027] Figure label:

[0028] Positive feedback gain unit 1, capacitor array unit 2, variable capacitor array module 21, fixed capacitor array module 22, variable capacitor branch 211, fixed capacitor branch 221, bias voltage module 23 Detailed Implementation

[0029] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0030] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0031] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "setting," "arrangement," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0032] The following is for reference. Figures 1 to 4 A voltage-controlled oscillator according to a first aspect of the present invention is described.

[0033] like Figure 1As shown, the voltage-controlled oscillator (VCO) according to an embodiment of the present invention includes a positive feedback gain unit 1, a capacitor array unit 2, a positive output port VCO_OP, and a negative output port VCO_ON. The two ends of the positive feedback gain unit 1 and the capacitor array unit 2 connected in parallel are respectively connected to the positive output port VCO_OP and the negative output port VCO_ON. An inductor L is also connected to the positive output port VCO_OP and the negative output port VCO_ON. The positive feedback gain unit 1 is used to ensure the continuous oscillation of the VCO and allows the oscillation frequency to be adjusted by an external voltage signal. The capacitor array unit 2 is used to provide a wide range of frequency tuning capability for the VCO and to compensate for the frequency gain and temperature coefficient of the VCO, thereby achieving more stable and precise frequency control.

[0034] like Figure 2 As shown, in some specific embodiments of the present invention, the positive feedback gain unit 1 includes a first P-type field-effect transistor MP1, a second P-type field-effect transistor MP2, a first N-type field-effect transistor MN1, and a second N-type field-effect transistor MN2. The gate (G) of the first P-type field-effect transistor MP1 and the drain (D) of the second P-type field-effect transistor MP2 are connected to the negative output port VCO_ON of the voltage-controlled oscillator (VCO). The drain (D) of the first P-type field-effect transistor MP1 and the gate (G) of the second P-type field-effect transistor MP2 are connected to the positive output port VCO_OP of the VCO. The source (S) of the first P-type field-effect transistor MP1 and the second P-type field-effect transistor MP2 are connected to the first power supply voltage VDD1. The gate (G) of the first N-type field-effect transistor MN1 and the drain (D) of the second N-type field-effect transistor MN2 are connected to the negative output port VCO_ON. The drain (D) of the first N-type field-effect transistor MN1 and the gate (G) of the second N-type field-effect transistor MN2 are connected to the positive output port VCO_OP. The source (S) of the first N-type field-effect transistor MN1 and the second N-type field-effect transistor MN2 are connected to one end of the first variable resistor R_turn1, and the other end of the first variable resistor R_turn1 is grounded.

[0035] like Figure 1 , Figure 2 and Figure 4As shown, in some specific embodiments of the present invention, the capacitor array unit 2 includes a variable capacitor array module 21, a fixed capacitor array module 22, and a bias voltage module 23. The variable capacitor array module 21 and the fixed capacitor array module 22 are connected in parallel, and their two ends are respectively connected to the positive terminal plus and the negative terminal minus of the capacitor array unit 2 (the positive terminal plus of the capacitor array unit 2 corresponds to the positive output port VCO_OP of the voltage-controlled oscillator, and the negative terminal minus of the capacitor array unit 2 corresponds to the negative output port VCO_ON of the voltage-controlled oscillator). The bias voltage module 23 is connected to the variable capacitor array module 21 to provide a bias voltage. In this embodiment, the variable capacitor array module 21, the fixed capacitor array module 22, and the bias voltage module 23 cooperate to provide the voltage-controlled oscillator with a wide range of frequency coordination capabilities, and to compensate for the frequency gain and temperature coefficient of the voltage-controlled oscillator.

[0036] Specifically, the variable capacitor array module 21 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal, and the fixed capacitor array module 22 has a first terminal, a second terminal, and a third terminal. The node formed by connecting the second terminal of the variable capacitor array module 21 and the second terminal of the fixed capacitor array module 22 serves as the positive terminal plus of the capacitor array unit 2, and the node formed by connecting the fifth terminal of the variable capacitor array module 21 and the third terminal of the fixed capacitor array module 22 serves as the negative terminal minus of the capacitor array unit 2. The first terminal of the variable capacitor array module 21 is connected to a selector MUX to receive a first control voltage Vctr1<7:0>. The selector MUX can select either a fixed voltage Vfix or a control voltage Lpf_Vc as the first control voltage Vctr1<7:0> based on the first control word signal VAR_SEL<7:0>. The third and fourth terminals of the variable capacitor array module 21 are connected to a bias voltage module 23 to receive a bias voltage. The first terminal of the fixed capacitor array module 22 receives a second control word signal Band_sel<7:0>.

[0037] It should be noted that the fixed voltage Vfix is ​​a fixed value, while the control voltage Lpf_Vc is a variable value, ranging from 0 to VDD1. The control voltage Lpf_Vc is the output voltage of the loop filter in the phase-locked loop (PLL). When the PLL's output frequency is lower than the preset target value, loop feedback will increase the control voltage Lpf_Vc until the output frequency of the voltage-controlled oscillator (VCO) equals the PLL's preset target value. Conversely, when the PLL's output frequency is higher than the preset target value, loop feedback will decrease the control voltage Lpf_Vc until the VCO's output frequency equals the PLL's preset target value.

[0038] In some specific embodiments of the present invention, the variable capacitor array module 21 includes multiple variable capacitor branches 211, which are connected in parallel and share a positive terminal plus and a negative terminal minus. Each variable capacitor branch 211 corresponds one-to-one with a bit in the first control voltage Vctr1<7:0>, and the voltage connected to each variable capacitor branch 211 is determined as Lpf_Vc or Vfix based on the value of the corresponding bit in the first control voltage Vctr1<7:0>.

[0039] Specifically, each variable capacitor branch 211 includes a first sub-branch, a second sub-branch, a third sub-branch, and a fourth sub-branch. Node a, where the first and fourth sub-branch are connected, serves as the third terminal of the variable capacitor array module 21 (connected to the first bias voltage Vref1 output by the bias voltage module 23); node b, where the first and fourth sub-branch are connected, and node c, where the second and third sub-branch are connected, serve as the first terminal of the variable capacitor array module 21 (connected to the selector MUX to receive the first control voltage Vctr1 of the corresponding bit); node d, where the second and third sub-branch are connected, serves as the fourth terminal of the variable capacitor array module 21 (connected to the second bias voltage Vref2 output by the bias voltage module 23); node e, where the first and second sub-branch are connected, serves as the second terminal (positive terminal plus) of the variable capacitor array module 21; and node f, where the third and fourth sub-branch are connected, serves as the fifth terminal (negative terminal minus) of the variable capacitor array module 21.

[0040] Furthermore, the first sub-branch includes a first DC blocking capacitor C1, a first variable capacitor VAR1, and a first resistor R1. One end of the first DC blocking capacitor C1 serves as the second terminal (positive terminal plus) of the variable capacitor array module 21, and the other end of the first DC blocking capacitor C1 is connected to the positive terminal of the first variable capacitor VAR1. The negative terminal of the first variable capacitor VAR1 serves as the first terminal of the variable capacitor array module 21 (connected to the control selector MUX to receive the first control voltage Vctr1<7:0> for the corresponding bit). Simultaneously, the other end of the first DC blocking capacitor C1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 serves as the third terminal of the variable capacitor array module 21 (connected to the bias voltage module 23 to receive the first bias voltage Vref1).

[0041] The second sub-branch includes a second DC blocking capacitor C2, a second variable capacitor VAR2, and a second resistor R2. One end of the second DC blocking capacitor C2 is connected to one end of the first DC blocking capacitor C1, and the other end of the second DC blocking capacitor C2 is connected to the positive terminal of the second variable capacitor VAR2. The negative terminal of the second variable capacitor VAR2 is connected to the negative terminal of the first variable capacitor VAR1. Simultaneously, the other end of the second DC blocking capacitor C2 is connected to one end of the second resistor R2, and the other end of the second resistor R2 serves as the fourth terminal of the variable capacitor array module 21 (connected to the bias voltage module 23 to receive the second bias voltage Vref2).

[0042] The third sub-branch includes a third DC blocking capacitor C3, a third variable capacitor VAR3, and a third resistor R3. One end of the third DC blocking capacitor C3 serves as the fifth terminal (minus negative terminal) of the variable capacitor array module 21. The other end of the third DC blocking capacitor C3 is connected to the positive terminal of the third variable capacitor VAR3, and the negative terminal of the third variable capacitor VAR3 is connected to the negative terminal of the first variable capacitor VAR1. Simultaneously, the other end of the third DC blocking capacitor C3 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the other end of the second resistor R2.

[0043] The fourth sub-branch includes a fourth DC blocking capacitor C4, a fourth variable capacitor VAR4, and a fourth resistor R4. One end of the fourth DC blocking capacitor C4 is connected to one end of the third DC blocking capacitor C3, and the other end of the fourth DC blocking capacitor C4 is connected to the positive terminal of the fourth variable capacitor VAR4. The negative terminal of the fourth variable capacitor VAR4 is connected to the negative terminal of the first variable capacitor VAR1. Simultaneously, the other end of the fourth DC blocking capacitor C4 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the other end of the first resistor R1.

[0044] It should be noted that the variable capacitor branch 211 is configured in this way so that its capacitance value has a good linear trend under the action of the first control voltage Vctrl over a wide range. Figure 3 The figure shows the CV characteristic curve of the variable capacitor branch 211. It can be seen that the capacitance value of the variable capacitor branch 211 has a wider linear variation range, which can make the frequency gain Kvco not change with the change of the first control voltage Vctrl in a single sub-band, thereby achieving the effect of constant frequency gain Kvco in a single sub-band.

[0045] In this embodiment, to enable the voltage-controlled oscillator (VCO) to have a wider frequency tuning range, the variable capacitor array module 21 uses an 8-bit control word to control and adjust the frequency band of the VCO (i.e., the capacitance value connected to the resonant cavity). Each control word corresponds to a sub-band, and the 8-bit control word controls a total of 256 sub-bands. Therefore, the variable capacitor array module 21 includes 8 variable capacitor branches 211, which constitute 256 sub-bands. The capacitance value of each variable capacitor branch 211 corresponds to the following relationship: VAR7=2*VAR6=4*VAR5=8*VAR4=16*VAR3=32*VAR2=64*VAR1=128*VAR0 (VAR0...VAR7 represent the capacitance values ​​of the 0th to the 7th variable capacitor branches, respectively). The bits in the first control word signal VAR_SEL<7:0> correspond one-to-one with the bits in the first control voltage Vctrl<7:0>. When the first control word signal VAR_SEL<7:0>=00000000, Vctrl<7:0> selects Lpf_Vc; when VAR_SEL<7:0>=11111111, Vctrl<7:0> selects Vfix. When a bit in VAR_SEL<7:0> is 0, the voltage of the corresponding bit in Vctrl<7:0> is Lpf_Vc; when a bit in VAR_SEL<7:0> is 1, the voltage of the corresponding bit in Vctrl<7:0> is Vfix. Therefore, when VAR_SEL<7:0> increases, the variable capacitor branch 211 controlled by the controlled voltage Lpf_Vc decreases, and the frequency gain Kvco of the voltage-controlled oscillator decreases; when VAR_SEL<7:0> decreases, the variable capacitor branch 211 controlled by the controlled voltage Lpf_Vc increases, and the frequency gain Kvco of the voltage-controlled oscillator increases.

[0046] In some specific embodiments of the present invention, the fixed capacitor array module 22 includes multiple fixed capacitor branches 221, which are connected in parallel and share a positive terminal plus and a negative terminal minus.

[0047] Specifically, each fixed capacitor branch 221 includes a fifth DC blocking capacitor C5, a switch K, and a sixth DC blocking capacitor C6, which are connected in series. The floating end of the fifth DC blocking capacitor C5 serves as the second terminal (positive terminal plus) of the fixed capacitor array module 22, and the floating end of the sixth DC blocking capacitor C6 serves as the third terminal (negative terminal minus) of the fixed capacitor array module 22.

[0048] In this embodiment, to enable the voltage-controlled oscillator (VCO) to have a wider frequency tuning range, the fixed capacitor array module 22 uses an 8-bit control word to control and adjust the frequency band of the VCO (i.e., the capacitance value connected to the resonant cavity). Each control word corresponds to a sub-band, and the 8-bit control word controls a total of 256 sub-bands. Therefore, the fixed capacitor array module 22 includes 8 fixed capacitor branches 221, which constitute 256 sub-bands. The capacitance value of each fixed capacitor branch 221 corresponds to the following relationship: C7=2*C6=4*C5=8*C4=16*C3=32*C2=64*C1=128*C0 (C0……C7 represent the capacitance values ​​of the 0th to the 7th fixed capacitor branches, respectively). The second control word signal Band_sel<7:0> controls the opening and closing of the switches K of the 8 fixed capacitor branches 221, respectively. The bits corresponding to the second control word signal Band_sel<7:0> correspond one-to-one with the bits of the switches K in the 7th to 0th fixed capacitor branches 221. When a bit in Band_sel<7:0> is 0, the switch K in the corresponding fixed capacitor branch 221 is closed; when a bit in Band_sel<7:0> is 1, the switch K in the corresponding fixed capacitor branch 221 is open. When Band_sel<7:0>=00000000, all switches K in the 8 fixed capacitor branches 221 are closed, and the ideal capacitance value is 255*C0; when Band_sel<7:0>=11111111, all switches K in the 8 fixed capacitor branches 221 are open, and the ideal capacitance value is 0. Therefore, when Band_sel<7:0> decreases, the number of fixed capacitor branches 221 connected to the resonant cavity increases; when Band_sel<7:0> increases, the number of fixed capacitor branches 221 connected to the resonant cavity decreases.

[0049] It should be noted that the method of adjusting the variable capacitor array module 21 and the fixed capacitor array module 22 in conjunction ensures that the frequency gain Kvco of the voltage-controlled oscillator does not change with the frequency subband. When the second control word signal Band_sel<7:0> increases, VAR_SEL<7:0> also increases, thus reducing the number of fixed capacitor branches 221 connected to the resonant cavity. Simultaneously, the number of variable capacitor branches 211 controlled by the controlled voltage Lpf_Vc also decreases. Conversely, when the second control word signal Band_sel<7:0> decreases, VAR_SEL<7:0> also decreases, thus increasing the number of fixed capacitor branches 221 connected to the resonant cavity. Simultaneously, the number of variable capacitor branches 211 controlled by the controlled voltage Lpf_Vc also increases. By adjusting Band_sel<7:0> and VAR_SEL<7:0> in the same way, the ratio of the variable capacitor to the overall capacitance of the resonant cavity can be made to be very small in different frequency bands. This results in a small difference in the frequency gain Kvco corresponding to different frequency sub-bands, and thus achieves the effect of constant frequency gain Kvco between different frequency sub-bands.

[0050] like Figure 4 As shown, in some specific embodiments of the present invention, the bias voltage module 23 includes a third P-type field-effect transistor MP3, a fourth P-type field-effect transistor MP4, an amplifier AMP1, a second variable resistor R_turn2, and a transistor Q1, wherein the transistor Q1 is a PNP type.

[0051] Specifically, the sources (S) of the third P-type field-effect transistor (FET) MP3 and the fourth P-type field-effect transistor (FET) MP4 are connected to the second supply voltage VDD2. The gates (G) of the third P-type field-effect transistor (FET) MP3 and the fourth P-type field-effect transistor (FET) MP4 are connected to the output pin of amplifier AMP1. The drain (D) of the third P-type field-effect transistor (FET) MP3 is connected to the positive input pin of amplifier AMP1 and then grounded through the fifth resistor R5. The negative input pin of amplifier AMP1 is connected to the system bandgap reference voltage source Vbg. The drain (D) of the fourth P-type field-effect transistor (FET) MP4 serves as one output terminal of the bias voltage module 23, outputting the second bias voltage Vref2. The drain (D) of the fourth P-type field-effect transistor (FET) MP4 is connected to the emitter (E) of transistor Q1 through the second variable resistor R_turn2. The emitter (E) of transistor Q1 serves as the other output terminal of the bias voltage module 23, outputting the first bias voltage Vref1. The base (B) and collector (C) of transistor Q1 are grounded.

[0052] It should be noted that since the positive terminals of the first variable capacitor VAR1 and the fourth variable capacitor VAR4 are connected to the first bias voltage Vref1 through the first resistor R1 and the fourth resistor R4, respectively, and the positive terminals of the second variable capacitor VAR2 and the third variable capacitor VAR3 are connected to the second bias voltage Vref2 through the second resistor R2 and the third resistor R3, respectively, it can be seen that the capacitance value of the variable capacitor is directly proportional to the bias voltage. When the first bias voltage Vref1 increases, the capacitance values ​​of the first variable capacitor VAR1 and the fourth variable capacitor VAR4 increase; when the first bias voltage Vref1 decreases, the capacitance values ​​of the first variable capacitor VAR1 and the fourth variable capacitor VAR4 decrease. Similarly, the second bias voltage Vref2 is related to the second variable capacitor VAR2 and the third variable capacitor VAR3.

[0053] Since the first bias voltage Vref1 and the second bias voltage Vref2 have negative temperature coefficients, when the temperature rises, the voltage values ​​of the first bias voltage Vref1 and the second bias voltage Vref2 decrease, thereby reducing the capacitance values ​​of the first variable capacitor VAR1, the fourth variable capacitor VAR4, the second variable capacitor VAR2, and the third variable capacitor VAR3; when the temperature falls, the voltage values ​​of the first bias voltage Vref1 and the second bias voltage Vref2 rise, thereby increasing the capacitance values ​​of the first variable capacitor VAR1, the fourth variable capacitor VAR4, the second variable capacitor VAR2, and the third variable capacitor VAR3. This compensates for the frequency change of the voltage-controlled oscillator caused by the temperature change of the inductor L, thus achieving temperature compensation characteristics.

[0054] It should be noted that, based on the basic characteristics of a PNP transistor, the voltage Vbe between the base (B) and emitter (E) of the transistor has a negative temperature coefficient, with a typical value of -1.5mV / K. This makes the first bias voltage Vref1 also have a negative temperature coefficient.

[0055] The system's bandgap reference voltage source Vbg is also temperature insensitive. Thus, an amplifier AMP1 and a current mirror (composed of the third P-type MOSFET MP3 and the fourth P-type MOSFET MP4) generate a reference current Iref = Vbg / R5 flowing through the fifth resistor R5. Therefore, the second bias voltage Vref2 is the sum of the voltage drop across the mirror current on the second variable resistor R_turn2 and Vbe, i.e., Vref2 = Vbe + Irfe * R_turn2 = Vbe + Vbg * R_turn2 / R5. Since the reference voltage source Vbg, the fifth resistor R5, and the second variable resistor R_turn2 are all temperature-independent, the second bias voltage Vref2, like the first bias voltage Vref1, is only related to the voltage Vbe. The second bias voltage Vref2 also has a negative temperature coefficient. By adjusting the value of the second variable resistor R_turn2, the voltage values ​​of the first bias voltage Vref1 and the second bias voltage Vref2 can be made close. The temperature characteristic curves of the first bias voltage Vref1 and the second bias voltage Vref2 are shown below. Figure 4 As shown, the voltage values ​​of the first bias voltage Vref1 and the second bias voltage Vref2 decrease as the temperature increases.

[0056] Simulation and testing data show that when temperature compensation is used, the frequency of the voltage-controlled oscillator of this invention changes with temperature by 1 / 5 of the frequency change with temperature without temperature compensation. This demonstrates that the temperature compensation effect of the voltage-controlled oscillator of this invention is significant.

[0057] The voltage-controlled oscillator in the above technical solution generates a first bias voltage Vref1 and a second bias voltage Vref2 with negative temperature coefficients through the bias voltage module 23, which are used to bias the variable capacitor branch 211 and the variable capacitor array module 21, thereby achieving temperature compensation. By combining the variable capacitor array module 21, the fixed capacitor array module 22 and the bias voltage module 23, temperature compensation is achieved while ensuring the stability of the frequency gain Kvco. Furthermore, it saves one set of variable capacitor array module 21 for temperature compensation, effectively avoiding noise degradation caused by adding more components.

[0058] The phase-locked loop according to a second aspect of the present invention includes the voltage-controlled oscillator described in the first aspect of the present invention.

[0059] The phase-locked loop in the above technical solution has all the beneficial effects of the voltage-controlled oscillator described above, which will not be repeated here.

[0060] An electronic device according to a third aspect of the present invention includes a voltage-controlled oscillator as described in the first aspect of the present invention or a phase-locked loop as described in the second aspect of the present invention.

[0061] The electronic equipment using the above technical solution has all the beneficial effects of the voltage-controlled oscillator or phase-locked loop mentioned above, which will not be elaborated here.

[0062] A vehicle according to a fourth aspect embodiment of the present invention includes the electronic equipment described in the third aspect embodiment of the present invention.

[0063] The vehicle using the above technical solution has all the beneficial effects of the aforementioned electronic equipment, which will not be elaborated further here.

[0064] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0065] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A voltage-controlled oscillator, characterized in that, include: The system comprises a positive feedback gain unit (1), a capacitor array unit (2), a positive output port VCO_OP, and a negative output port VCO_ON. The two ends of the positive feedback gain unit (1) and the capacitor array unit (2) connected in parallel are respectively connected to the positive output port VCO_OP and the negative output port VCO_ON. The positive feedback gain unit (1) is used to ensure the continuous oscillation of the voltage-controlled oscillator and to allow the oscillation frequency to be adjusted by an external voltage signal. The capacitor array unit (2) is used to provide the voltage-controlled oscillator with a wide range of frequency tuning capability and to compensate for the frequency gain and temperature coefficient of the voltage-controlled oscillator. The capacitor array unit (2) includes a variable capacitor array module (21), a fixed capacitor array module (22), and a bias voltage module (23). The variable capacitor array module (21) and the fixed capacitor array module (22) are connected in parallel, and their two ends are respectively connected to the positive terminal plus and the negative terminal minus of the capacitor array unit (2). The bias voltage module (23) is connected to the variable capacitor array module (21) to provide a bias voltage. The variable capacitor array module (21), the fixed capacitor array module (22), and the bias voltage module (23) work together to provide a wide range of frequency coordination capability for the voltage-controlled oscillator, as well as to compensate for the frequency gain and temperature coefficient of the voltage-controlled oscillator. The variable capacitor array module (21) has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal; the fixed capacitor array module (22) has a first terminal, a second terminal, and a third terminal; the node formed by connecting the second terminal of the variable capacitor array module (21) and the second terminal of the fixed capacitor array module (22) is the positive terminal plus; the node formed by connecting the fifth terminal of the variable capacitor array module (21) and the third terminal of the fixed capacitor array module (22) is the negative terminal minus; the first terminal of the variable capacitor array module (21) is connected to the selector MUX to receive the first control voltage Vctr1<7:0>; the third and fourth terminals of the variable capacitor array module (21) are connected to the bias voltage module (23); the first terminal of the fixed capacitor array module (22) receives the second control word signal Band_sel<7:0>; The variable capacitor array module (21) includes multiple variable capacitor branches (211), which are connected in parallel. Each variable capacitor branch (211) is controlled by the corresponding bit in the first control voltage Vctr1<7:0>, and the voltage connected to each variable capacitor branch (211) is determined according to the value of the corresponding bit.

2. The voltage-controlled oscillator according to claim 1, characterized in that, The positive feedback gain unit (1) includes a first P-type field-effect transistor MP1, a second P-type field-effect transistor MP2, a first N-type field-effect transistor MN1, and a second N-type field-effect transistor MN2; The gate G of the first P-type field-effect transistor MP1 and the drain D of the second P-type field-effect transistor MP2 are connected to the negative output port VCO_ON, and the drain D of the first P-type field-effect transistor MP1 and the gate G of the second P-type field-effect transistor MP2 are connected to the positive output port VCO_OP. The source S of the first P-type field-effect transistor MP1 and the second P-type field-effect transistor MP2 are connected to the first power supply voltage VDD1. The gate G of the first N-type field-effect transistor MN1 and the drain D of the second N-type field-effect transistor MN2 are connected to the negative output port VCO_ON, and the drain D of the first N-type field-effect transistor MN1 and the gate G of the second N-type field-effect transistor MN2 are connected to the positive output port VCO_OP. The source S of the first N-type field-effect transistor MN1 and the second N-type field-effect transistor MN2 is grounded through the first variable resistor R_turn1.

3. The voltage-controlled oscillator according to claim 1, characterized in that, The variable capacitor branch (211) includes a first sub-branch, a second sub-branch, a third sub-branch, and a fourth sub-branch; node a, where the first sub-branch and the fourth sub-branch are connected, serves as the third end of the variable capacitor array module (21); node b, where the first sub-branch and the fourth sub-branch are connected, and node c, where the second sub-branch and the third sub-branch are connected, serve as the first end of the variable capacitor array module (21); node d, where the second sub-branch and the third sub-branch are connected, serves as the fourth end of the variable capacitor array module (21); node e, where the first sub-branch and the second sub-branch are connected, serves as the second end of the variable capacitor array module (21); and node f, where the third sub-branch and the fourth sub-branch are connected, serves as the fifth end of the variable capacitor array module (21).

4. The voltage-controlled oscillator according to claim 1, characterized in that, The fixed capacitor array module (22) includes multiple fixed capacitor branches (221), which are connected in parallel. Each fixed capacitor branch (221) includes a fifth DC blocking capacitor C5, a switch k, and a sixth DC blocking capacitor C6 connected in series. The floating end of the fifth DC blocking capacitor C5 serves as the second end of the fixed capacitor array module (22), and the floating end of the sixth DC blocking capacitor C6 serves as the third end of the fixed capacitor array module (22).

5. The voltage-controlled oscillator according to claim 1, characterized in that, The bias voltage module (23) includes a third P-type field-effect transistor MP3, a fourth P-type field-effect transistor MP4, an amplifier AMP1, a second variable resistor R_turn2, and a transistor Q1; The sources S of the third P-type field-effect transistor MP3 and the fourth P-type field-effect transistor MP4 are connected to the second supply voltage VDD2. The gates G of the third P-type field-effect transistor MP3 and the fourth P-type field-effect transistor MP4 are connected to the output pin of amplifier AMP1. The drain D of the third P-type field-effect transistor MP3 is connected to the positive input pin of amplifier AMP1 and then grounded through the fifth resistor R5. The inverting input pin of amplifier AMP1 is connected to the reference voltage source Vbg. The drain D of the fourth P-type field-effect transistor MP4 serves as one output terminal of the bias voltage module 23, outputting the second bias voltage Vref2. The drain D of the fourth P-type field-effect transistor MP4 is connected to the emitter E of transistor Q1 through the second variable resistor R_turn2. The emitter E of transistor Q1 serves as the other output terminal of the bias voltage module 23, outputting the first bias voltage Vref1. The base B and collector C of transistor Q1 are grounded.

6. A phase-locked loop, characterized in that, Includes the voltage-controlled oscillator as described in any one of claims 1 to 5.

7. An electronic device, characterized in that, Includes the voltage-controlled oscillator as described in any one of claims 1 to 5 or the phase-locked loop as described in claim 6.

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