Foreground calibration circuit of time domain analog-to-digital converter

Abstract

The invention provides a foreground calibration circuit of a time domain analog-to-digital converter. The foreground calibration circuit comprises a calibration clock generating circuit, an oscillation period detecting and processing circuit and a current adjusting circuit, the calibration clock generation circuit is connected with the oscillation period detection and processing circuit and is used for calibrating a circuit clock; the oscillation period detecting and processing circuit is connected with the counter and the current adjusting circuit and is used for detecting and adjusting the oscillation period; and the current adjusting circuit is connected with the input current and is used for adjusting the magnitude of the current. A detection circuit is introduced to a period counting result of the ring oscillator, under the condition of input full swing, whether the counting period reaches a preset value or not is detected, the result is fed back to a counter, and control code words are output to adjust discharge current in the voltage-time conversion circuit and adjust the output time range; and automatic matching of the conversion range of the voltage-time conversion circuit and the quantization range of the time-digital conversion circuit is realized.

Description

Technical Field

[0001] The invention relates to the technical field of analog integrated circuits, and in particular to a foreground calibration circuit of a time domain analog-to-digital converter. Background Art

[0002] The analog-to-digital converter is an important bridge between analog signals and digital signals. It is an essential component for computers to process analog signals and is widely used in modern communications, smart medical care, and other fields. With the development of integrated circuit manufacturing technology, the characteristic size of transistors continues to decrease, and the power supply voltage is gradually decreasing. For the analog-to-digital converter in the voltage domain, the input swing becomes smaller, resulting in a decrease in the achievable signal-to-noise ratio. The analog-to-digital converter in the time domain converts the input voltage into a time signal and quantizes the time signal. The quantization resolution increases as the delay time decreases, and as the characteristic size decreases, the delay time of a single inverter decreases, which has a significant speed advantage. Figure 1 It is a traditional time domain analog-to-digital converter circuit, and its working process is: first, the analog voltage V2 and V1 are collected to the capacitors at both ends through the switch, and then the voltage on the capacitor is discharged. The charge conversion relationship can be expressed as I*(t2-t1)=C*((V2-VTH)-(V1-VTH)), where I is the discharge current, t1 and t2 are the time when the voltage at both ends is reduced to the inverter flip threshold VTH, and C is the discharged capacitance value. When the discharge current and capacitance value remain unchanged, the voltage difference and the discharge time difference are in a linear relationship. The output clock rising edge signal is then converted into a pulse signal through a pulse generation circuit to enable a multi-stage differential ring oscillator structure based on an inverter. By collecting the oscillation cycle number and phase information of the output clock at the falling edge of the enable signal, a digital codeword is obtained through processing to complete the conversion of the analog signal to the digital signal.

[0003] However, the delay of the inverter is affected by the process angle, temperature, and power supply voltage, causing the time range of the time-to-digital conversion circuit to change. At the same time, the capacitance value in the voltage-to-time conversion circuit is affected by the change in the process angle, affecting the output time range, resulting in a mismatch between the output range of the voltage-to-time conversion circuit and the quantization range of the time-to-digital conversion circuit. Summary of the invention

[0004] The purpose of the present invention is to provide a foreground calibration circuit of a time domain analog-to-digital converter, which solves the problem that the output range of the voltage-to-time conversion circuit and the quantization range of the time-to-digital conversion circuit do not match under the changes of process angle, temperature and power supply voltage of the existing time domain analog-to-digital converter, and proposes a foreground calibration circuit of a time domain analog-to-digital converter. The present invention introduces a detection circuit at the cycle counting result of the ring oscillator, and in the case of full input swing, by detecting whether the counted cycle reaches a preset value, the result is fed back to the counter output control codeword to adjust the discharge current in the voltage-to-time conversion circuit, adjust the output time range, and realize automatic matching of the conversion range of the voltage-to-time conversion circuit and the quantization range of the time-to-digital conversion circuit.

[0005] A foreground calibration circuit of a time domain analog-to-digital converter comprises: a calibration clock generation circuit, an oscillation period detection and processing circuit, and a current adjustment circuit;

[0006] The calibration clock generation circuit is connected to the oscillation period detection and processing circuit and is used to calibrate the circuit clock;

[0007] The oscillation period detection and processing circuit is connected to the counter and the current adjustment circuit, and is used to detect the oscillation period and adjust the oscillation period;

[0008] The current adjustment circuit is connected to the input current and is used to adjust the magnitude of the current.

[0009] Preferably, the calibration clock generation circuit comprises: a D flip-flop (DFF0) with asynchronous low-level reset and a D flip-flop (DFF1) with asynchronous low-level reset;

[0010] The reset terminals RST of the asynchronous low-level reset D flip-flop (DFF0) and the asynchronous low-level reset D flip-flop (DFF1) are connected to the calibration enable signal EN_CAL, the input clock terminal Clk of the asynchronous low-level reset D flip-flop (DFF0) is connected to the data acquisition clock CLK of the ring oscillator, the data input terminal D is connected to the reverse output terminal Q, and is connected to the input clock terminal Clk of the asynchronous low-level reset D flip-flop (DFF1);

[0011] The data input terminal D and the reverse output terminal Q of the asynchronous low-level reset D flip-flop (DFF1) are connected, the reverse output terminal Q is connected to the sampling clock CLK_SIN, and the forward output terminal Q is connected to the codeword output clock CLK_DOUT.

[0012] Preferably, the oscillation period detection and processing circuit comprises: a D flip-flop (DFF2), a D flip-flop with asynchronous low-level reset (DFF3), a D flip-flop with asynchronous low-level reset (DFF4), a D flip-flop with asynchronous low-level reset (DFF5), a D flip-flop with asynchronous low-level reset (DFF6), a D flip-flop with asynchronous low-level set (DFF7), a half adder (A1), a full adder (A2), a full adder (A3), a full adder (A4), and a full adder (A5);

[0013] The input terminal D of the D flip-flop (DFF2) is connected to the cycle counting signal CNT, the input clock terminal Clk is connected to the sampling clock CLK_SIN, the positive output terminal Q is connected to the detection signal CNT_IN, and the reverse output terminal Q is connected to the detection signal CNT_INB;

[0014] The input terminal A of the half adder (A1) is connected to the signal IN <0> , the input terminal B is connected to the power supply voltage VDD, and the output terminal summation result S is connected to the signal OUT <0> , the carry result CO at the output is connected to the input CI of the next full adder (A2);

[0015] The input terminal A of the full adder (A2) is connected to the signal IN <1> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <1> , the carry result CO at the output is connected to the input CI of the next full adder (A3);

[0016] The input terminal A of the full adder (A3) is connected to the signal IN <2> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <2> , the carry result CO at the output is connected to the input CI of the next full adder (A3);

[0017] The input terminal A of the full adder (A4) is connected to the signal IN <3> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <3> , the carry result CO at the output is connected to the input terminal CI of the next stage full adder (A5);

[0018] The input terminal A of the full adder (A5) is connected to the signal IN <4> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <4> ;

[0019] The input terminal D of the asynchronous low-level reset D flip-flop (DFF3) is connected to the signal OUT <0> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <0> , the reverse output terminal Q is connected to the signal INB <0> ;

[0020] The input terminal D of the asynchronous low-level reset D flip-flop (DFF4) is connected to the signal OUT <1> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <1> , the reverse output terminal Q is connected to the signal INB <1> ;

[0021] The input terminal D of the asynchronous low-level reset D flip-flop (DFF5) is connected to the signal OUT <2> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <2> , the reverse output terminal Q is connected to the signal INB <2> ;

[0022] The input terminal D of the asynchronous low-level reset D flip-flop (DFF6) is connected to the signal OUT <3> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <3> , the reverse output terminal Q is connected to the signal INB <3> ;

[0023] The input terminal D of the asynchronous low-level set D flip-flop (DFF7) is connected to the signal OUT <4> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input set terminal SET is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <4> , the reverse output terminal Q is connected to the signal INB <4> .

[0024] Preferably, the current adjustment circuit comprises: a current source (I1), a PMOS tube (PM1), a PMOS tube (PM2), a PMOS tube (PM3), a PMOS tube (PM4), a PMOS tube (PM5), an NMOS tube (NM1), an NMOS tube (NM2), an NMOS tube (NM3), an NMOS tube (NM4), an NMOS tube (NM5), an NMOS tube (NM6), an NMOS tube (NM7), an NMOS tube (NM8), an NMOS tube (NM9), an NMOS tube (NM10), an NMOS tube (NM11), an NMOS tube (NM12), an NMOS tube (NM13), an NMOS tube (NM14), an NMOS tube (NM15), an NMOS tube (NM16), an NMOS tube (NM17), an NMOS tube (NM18), an NMOS tube (NM19), and a resistor (R1), and the size ratio of the five-way adjustable current mirror part is 16:8:4:2:1;

[0025] The input end of the current source (I1) is connected to the power supply VDD, the output end is connected to VB1, both ends of the resistor (R1) are connected to VB1 and VB2, the drain of the NMOS tube (NM6) is connected to VB2, the gate is connected to VB1, the source is connected to the drain of the NMOS tube (NM13), the gate of the NMOS tube (NM13) is connected to VB2, and the source is connected to VSS;

[0026] The drain terminal of the NMOS tube (NM7) is connected to the output terminal IBout, the gate is connected to VB1, the source is connected to the drain terminal of the NMOS tube (NM14), the gate terminal of the NMOS tube (NM14) is connected to VB2, and the source terminal is connected to VSS;

[0027] The drain of the NMOS tube (NM8) is connected to the output terminal IBout, and the gate is connected to D <0> , the source is connected to the drain of the NMOS tube (NM15), the gate of the NMOS tube (NM15) is connected to VB2, and the source is connected to VSS;

[0028] The drain of the NMOS tube (NM9) is connected to the output terminal IBout, and the gate is connected to D <1> , the source is connected to the drain of the NMOS tube (NM16), the gate of the NMOS tube (NM16) is connected to VB2, and the source is connected to VSS;

[0029] The drain of the MOS tube (NM10) is connected to the output terminal IBout, and the gate is connected to D <2> , the source is connected to the drain of the NMOS tube (NM17), the gate of the NMOS tube (NM17) is connected to VB2, and the source is connected to VSS;

[0030] The drain of the NMOS tube (NM11) is connected to the output terminal IBout, and the gate is connected to D <3> , the source is connected to the drain of the NMOS tube (NM18), the gate of the NMOS tube (NM18) is connected to VB2, and the source is connected to VSS;

[0031] The drain of the NMOS tube (NM12) is connected to the output terminal IBout, and the gate is connected to D <4> , the source is connected to the drain of the NMOS tube (NM19), the gate of the NMOS tube (NM19) is connected to VB2, and the source is connected to VS;

[0032] The drain of the PMOS tube (PM1) is connected to the bias voltage VB2, and the gate is connected to INB <0> , the source is connected to D <0> , NMOS tube NMOS tube (NM1) drain connected to VSS, gate connected to INB <0> , the source is connected to D <0> ;

[0033] The drain of the PMOS tube (PM2) is connected to the bias voltage VB2, and the gate is connected to INB <1> , the source is connected to D <1> , NMOS tube NMOS tube (NM2) drain connected to VSS, gate connected to INB <1> , the source is connected to D <1> ;

[0034] The drain of the PMOS tube (PM3) is connected to the bias voltage VB2, and the gate is connected to INB <2> , the source is connected to D <2> , NMOS tube NMOS tube (NM3) drain connected to VSS, gate connected to INB <2> , the source is connected to D <2> ;

[0035] The drain of the PMOS tube (PM4) is connected to the bias voltage VB2, and the gate is connected to INB <3> , the source is connected to D <3> , NMOS tube NMOS tube (NM1) drain connected to VSS, gate connected to INB <3> , the source is connected to D <3> ;

[0036] The drain of the PMOS tube (PM5) is connected to the bias voltage VB2, and the gate is connected to INB <4> , the source is connected to D <4> , NMOS tube NMOS tube (NM1) drain connected to VSS, gate connected to INB <4> , the source is connected to D <4> .

[0037] A method for controlling a foreground calibration circuit of a time domain analog-to-digital converter is applied to a foreground calibration circuit of a time domain analog-to-digital converter, comprising:

[0038] Reset the circuit;

[0039] Calibrate the circuit after reset.

[0040] Preferably, calibrating the reset circuit includes:

[0041] Sampling the signal;

[0042] The sampled signal is adjusted.

[0043] Preferably, resetting the circuit comprises:

[0044] The RST_CAL signal is at a low level, the EN_CAL signal is at a low level, the outputs of the D flip-flop (DFF3), the D flip-flop with asynchronous low-level reset (DFF4), the D flip-flop with asynchronous low-level reset (DFF5), the D flip-flop with asynchronous low-level reset (DFF6), and the D flip-flop with asynchronous low-level set (DFF7) are reset, and the corresponding inverted output signal INB<4:0>=01111 controls the PMOS tube (PM1), NMOS tube (NM2), NMOS tube (NM3), NMOS tube (NM4), and NMOS tube (NM5) to turn on, making the D <4> =VB2,D <0> ,D <1> ,D <2> , D <3> All are VSS, so that the NMOS tube (NM12) is turned on, and the input current is composed of two branches of the NMOS tube (NM7), the NMOS tube (NM14) and the NMOS tube (NM12), the NMOS tube (NM19).

[0045] Preferably, sampling the signal comprises:

[0046] When the rising edge of CLK_SIN arrives, the D flip-flop (DFF2) samples the cycle count result CNT. If CNT is 1, it is latched to obtain CNT_IN=1, CNT_INB=0, indicating that the oscillation period exceeds the preset value. CNT is 0, and it is latched to obtain CNT_IN=0, CNT_INB=1, indicating that the oscillation period is less than the preset value. Through the subsequent processing circuit composed of a half adder and a full adder, when CNT_IN=1, CNT_INB=0, the output code word OUT<4:0> is increased by 1 compared to IN<4:0>. When CNT_IN=0, CNT_INB=1, the input code word IN<4:0> is equivalent to adding 11111. Since the output is only 5 bits, it is equivalent to the output code word OUT<4:0> minus 1 compared to IN<4:0>, completing the code word conversion.

[0047] Preferably, adjusting the sampled signal includes:

[0048] When the rising edge of CLK_DOUT arrives, the output code word OUT<4:0> is triggered and latched as IN<4:0>. The reverse signal INB<4:0> sets the value of D<4:0> by selecting the PMOS and NMOS transmission level VB2 or VSS, and then adjusts the conductive part of the current mirror circuit to achieve current adjustment;

[0049] When the oscillation period exceeds the preset value, the input code word is increased by 1, the PMOS is turned on, so that the control end output is VB2, the current tube is turned on, and the current is increased to reduce the output time range of the voltage-to-time converter. When the oscillation period is less than the preset value, the input code word is reduced by 1, the NMOS is turned on, so that the control end output is VSS, the current tube is turned off, and the current is reduced to increase the output time range of the voltage-to-time converter.

[0050] Preferably, calibrating the reset circuit includes:

[0051] The RST_CAL signal is at a high level. With the rising edge of the data acquisition clock CLK of the ring oscillator, the asynchronous low-level reset D flip-flop (DFF0) and the asynchronous low-level reset D flip-flop (DFF1) flip the output level under the control of the clock CLK to achieve the function of four-division. The frequency of the output clocks CLK_SIN and CLK_DOUT is 1 / 4 of the original.

[0052] The beneficial effects of the present invention are as follows: 1. The present invention introduces a detection circuit at the cycle counting result of the ring oscillator. When the input is full swing, the detection circuit detects whether the counted cycle reaches the preset value, and the result is fed back to the counter to adjust the size of the current source in the voltage-to-time conversion circuit, adjust the output time range, and realize the automatic matching of the quantization range of the voltage-to-time conversion circuit and the time-to-digital conversion circuit. 2. The circuit design of the present invention also has good PVT (process, voltage, temperature) robustness. By enabling calibration, the circuit can maintain stable performance under different process angles, power supply voltages and ambient temperature conditions. The detection result is fed back to the counter, and the circuit can adapt to these changes and automatically adjust to maintain a suitable matching range, thereby improving the reliability and adaptability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0055] Figure 1 It is a schematic diagram of the structure of a foreground calibration circuit of a time domain analog-to-digital converter of the present invention;

[0056] Figure 2 A schematic diagram of the structure of a calibration clock generation circuit of the present invention;

[0057] Figure 3 It is a schematic diagram of the structure of the oscillation period detection and processing circuit of the present invention;

[0058] Figure 4 It is a schematic diagram of the structure of the current regulating circuit of the present invention;

[0059] Figure 5 This is a diagram showing the adjustment result when the VTC output time range of the present invention is too large;

[0060] Figure 6 This is a waveform diagram showing the adjustment of the VTC output time range of the present invention when it is smaller. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0063] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0064] The delay of the inverter is affected by the process angle, temperature, and power supply voltage, causing the time range of the time-to-digital conversion circuit to change. At the same time, the capacitance value in the voltage-to-time conversion circuit is affected by the change in the process angle, affecting the output time range, causing the output range of the voltage-to-time conversion circuit to not match the quantization range of the time-to-digital conversion circuit.

[0065] The present invention introduces a detection circuit at the cycle counting result of the ring oscillator. When the input is full swing, the result is fed back to the counter to adjust the size of the current source in the voltage-time conversion circuit and the output time range, thereby realizing automatic matching of the quantization range of the voltage-time conversion circuit and the time-to-digital conversion circuit. The circuit design of the present invention also has good PVT (process, voltage, temperature) robustness. By enabling calibration, the circuit can maintain stable performance under different process angles, power supply voltages and ambient temperature conditions. The detection result is fed back to the counter, and the circuit can adapt to these changes and automatically adjust to maintain a suitable matching range, thereby improving the reliability and adaptability of the circuit.

[0066] Example 1

[0067] A foreground calibration circuit for a time domain analog-to-digital converter, referring to Figure 1, including: a calibration clock generation circuit, an oscillation period detection and processing circuit, and a current adjustment circuit;

[0068] The calibration clock generating circuit is connected to the oscillation period detecting and processing circuit and is used for calibrating the circuit clock;

[0069] The oscillation period detection and processing circuit is connected with the counter and the current adjustment circuit, and is used for detecting the oscillation period and adjusting the oscillation period;

[0070] The current adjustment circuit is connected to the input current and is used to adjust the magnitude of the current.

[0071] Preferably, reference Figure 2 , the calibration clock generation circuit includes: a D flip-flop (DFF0) with asynchronous low-level reset and a D flip-flop (DFF1) with asynchronous low-level reset;

[0072] The reset terminal RST of the asynchronous low-level reset D flip-flop (DFF0) and the asynchronous low-level reset D flip-flop (DFF1) is connected to the calibration enable signal EN_CAL, the input clock terminal Clk of the asynchronous low-level reset D flip-flop (DFF0) is connected to the data acquisition clock CLK of the ring oscillator, and the data input terminal D and the reverse output terminal connected to the input clock terminal Clk of the D flip-flop (DFF1) with asynchronous low-level reset;

[0073] The data input terminal D and the inverting output terminal Q of the asynchronous low-level reset D flip-flop (DFF1) are connected. Connected to the sampling clock CLK_SIN, and the positive output terminal Q is connected to the code word output clock CLK_DOUT.

[0074] Preferably, reference Figure 3 , the oscillation period detection and processing circuit includes: a D flip-flop (DFF2), a D flip-flop with asynchronous low-level reset (DFF3), a D flip-flop with asynchronous low-level reset (DFF4), a D flip-flop with asynchronous low-level reset (DFF5), a D flip-flop with asynchronous low-level reset (DFF6), a D flip-flop with asynchronous low-level set (DFF7), a half adder (A1), a full adder (A2), a full adder (A3), a full adder (A4), and a full adder (A5);

[0075] The input terminal D of the D flip-flop (DFF2) is connected to the cycle count signal CNT, the input clock terminal Clk is connected to the sampling clock CLK_SIN, the positive output terminal Q is connected to the detection signal CNT_IN, and the negative output terminal Connected to the detection signal CNT_INB;

[0076] The input terminal A of the half adder (A1) is connected to the signal IN <0> , the input terminal B is connected to the power supply voltage VDD, and the output terminal summation result S is connected to the signal OUT <0> , the carry result CO at the output is connected to the input CI of the next full adder (A2);

[0077] The input terminal A of the full adder (A2) is connected to the signal IN <1> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <1> , the carry result CO at the output is connected to the input CI of the next full adder (A3);

[0078] The input terminal A of the full adder (A3) is connected to the signal IN <2> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <2> , the carry result CO at the output is connected to the input CI of the next full adder (A3);

[0079] The input terminal A of the full adder (A4) is connected to the signal IN <3> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <3> , the carry result CO at the output is connected to the input terminal CI of the next stage full adder (A5);

[0080] The input terminal A of the full adder (A5) is connected to the signal IN <4> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <4> ;

[0081] The input terminal D of the asynchronous low-level reset D flip-flop (DFF3) is connected to the signal OUT <0> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <0> , the reverse output terminal Q is connected to the signal INB <0> ;

[0082] The input terminal D of the asynchronous low-level reset D flip-flop (DFF4) is connected to the signal OUT <1> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <1> , reverse output terminal Receive signal INB <1> ;

[0083] The input terminal D of the asynchronous low-level reset D flip-flop (DFF5) is connected to the signal OUT <2> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <2> , reverse output terminal Receive signal INB <2> ;

[0084] The input terminal D of the asynchronous low-level reset D flip-flop (DFF6) is connected to the signal OUT <3> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <3> , the inverting output terminal is connected to the signal INB <3> ;

[0085] The input terminal D of the asynchronous low-level set D flip-flop (DFF7) is connected to the signal OUT <4> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input set terminal SET is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <4> , reverse output terminal Receive signal INB <4> .

[0086] Preferably, reference Figure 4 The current adjustment circuit includes: a current source (I1), a PMOS tube (PM1), a PMOS tube (PM2), a PMOS tube (PM3), a PMOS tube (PM4), a PMOS tube (PM5), an NMOS tube (NM1), an NMOS tube (NM2), an NMOS tube (NM3), an NMOS tube (NM4), an NMOS tube (NM5), an NMOS tube (NM6), an NMOS tube (NM7), an NMOS tube (NM8), an NMOS tube (NM9), an NMOS tube (NM10), an NMOS tube (NM11), an NMOS tube (NM12), an NMOS tube (NM13), an NMOS tube (NM14), an NMOS tube (NM15), an NMOS tube (NM16), an NMOS tube (NM17), an NMOS tube (NM18), an NMOS tube (NM19), and a resistor (R1), and the size ratio of the five-way adjustable current mirror part is 16:8:4:2:1;

[0087] The input end of the current source (I1) is connected to the power supply VDD, the output end is connected to VB1, both ends of the resistor (R1) are connected to VB1 and VB2, the drain of the NMOS tube (NM6) is connected to VB2, the gate is connected to VB1, the source is connected to the drain of the NMOS tube (NM13), the gate of the NMOS tube (NM13) is connected to VB2, and the source is connected to VSS;

[0088] The drain terminal of the NMOS tube (NM7) is connected to the output terminal IBout, the gate is connected to VB1, the source is connected to the drain terminal of the NMOS tube (NM14), the gate terminal of the NMOS tube (NM14) is connected to VB2, and the source terminal is connected to VSS;

[0089] The drain of the NMOS tube (NM8) is connected to the output terminal IBout, and the gate is connected to D <0> , the source is connected to the drain of the NMOS tube (NM15), the gate of the NMOS tube (NM15) is connected to VB2, and the source is connected to VSS;

[0090] The drain of the NMOS tube (NM9) is connected to the output terminal IBout, and the gate is connected to D <1> , the source is connected to the drain of the NMOS tube (NM16), the gate of the NMOS tube (NM16) is connected to VB2, and the source is connected to VSS;

[0091] The drain of the MOS tube (NM10) is connected to the output terminal IBout, and the gate is connected to D <2> , the source is connected to the drain of the NMOS tube (NM17), the gate of the NMOS tube (NM17) is connected to VB2, and the source is connected to VSS;

[0092] The drain of the NMOS tube (NM11) is connected to the output terminal IBout, and the gate is connected to D <3> , the source is connected to the drain of the NMOS tube (NM18), the gate of the NMOS tube (NM18) is connected to VB2, and the source is connected to VSS;

[0093] The drain of the NMOS tube (NM12) is connected to the output terminal IBout, and the gate is connected to D <4> , the source is connected to the drain of the NMOS tube (NM19), the gate of the NMOS tube (NM19) is connected to VB2, and the source is connected to VS;

[0094] The drain of the PMOS tube (PM1) is connected to the bias voltage VB2, and the gate is connected to INB <0> , the source is connected to D <0> , NMOS tube NMOS tube (NM1) drain connected to VSS, gate connected to INB <0> , the source is connected to D <0> ;

[0095] The drain of the PMOS tube (PM2) is connected to the bias voltage VB2, and the gate is connected to INB <1> , the source is connected to D <1> , NMOS tube NMOS tube (NM2) drain connected to VSS, gate connected to INB <1> , the source is connected to D <1> ;

[0096] The drain of the PMOS tube (PM3) is connected to the bias voltage VB2, and the gate is connected to INB <2> , the source is connected to D <2> , NMOS tube NMOS tube (NM3) drain connected to VSS, gate connected to INB <2> , the source is connected to D <2> ;

[0097] The drain of the PMOS tube (PM4) is connected to the bias voltage VB2, and the gate is connected to INB <3> , the source is connected to D <3> , NMOS tube NMOS tube (NM1) drain connected to VSS, gate connected to INB <3> , the source is connected to D <3> ;

[0098] The drain of the PMOS tube (PM5) is connected to the bias voltage VB2, and the gate is connected to INB <4> , the source is connected to D <4> , NMOS tube NMOS tube (NM1) drain connected to VSS, gate connected to INB <4> , the source is connected to D <4> .

[0099] Example 2

[0100] A method for controlling a foreground calibration circuit of a time domain analog-to-digital converter, referring to Figure 5 and Figure 6 , applied to a front-end calibration circuit of a time domain analog-to-digital converter, comprising:

[0101] S100, resetting the circuit;

[0102] S200, calibrating the reset circuit.

[0103] In order to further verify the technical effect of the present invention, the inventor conducted the following experiments. The 65nm CMOS process was used to simulate the time domain analog-to-digital converter after adding the calibration circuit. The full swing voltage was input to the circuit. When the quantization range of the voltage-to-time conversion circuit is large, the output quantization codeword is too large. When the cycle count value is detected to be 1, the current control codeword is adjusted to add 1, and the corresponding control current branch is opened, so that the current increases, the discharge speed becomes faster, and the conversion time range becomes smaller, until the detected cycle value is 0. The final output codeword jumps within the set value range. The simulation waveform is as follows Figure 5 As shown. Input full swing voltage to the circuit. When the quantization range of the voltage-time conversion circuit is small, the output quantization codeword is small. When the cycle count value is detected to be 0, the current control codeword is adjusted to be minus 1, and the corresponding control current branch is disconnected, so that the current decreases, the discharge speed slows down, and the conversion time range increases until the detected cycle value is 1. The final output codeword jumps within the set value range. The simulation waveform is as follows Figure 6 The simulations in these two cases show that the calibration technology proposed in the present invention can achieve the calibration function.

[0104] Preferably, calibrating the reset circuit includes:

[0105] Sampling the signal;

[0106] The sampled signal is adjusted.

[0107] Preferably, resetting the circuit comprises:

[0108] The RST_CAL signal is at a low level, the EN_CAL signal is at a low level, the outputs of the D flip-flop (DFF3), the D flip-flop with asynchronous low-level reset (DFF4), the D flip-flop with asynchronous low-level reset (DFF5), the D flip-flop with asynchronous low-level reset (DFF6), and the D flip-flop with asynchronous low-level set (DFF7) are reset, and the corresponding inverted output signal INB<4:0>=01111 controls the PMOS tube (PM1), NMOS tube (NM2), NMOS tube (NM3), NMOS tube (NM4), and NMOS tube (NM5) to turn on, making the D <4> =VB2,D <0> ,D <1> ,D <2> , D <3> All are VSS, so that the NMOS tube (NM12) is turned on, and the input current is composed of two branches of the NMOS tube (NM7), the NMOS tube (NM14) and the NMOS tube (NM12), the NMOS tube (NM19).

[0109] Preferably, sampling the signal comprises:

[0110] When the rising edge of CLK_SIN arrives, the D flip-flop (DFF2) samples the cycle count result CNT. If CNT is 1, it is latched to obtain CNT_IN=1, CNT_INB=0, indicating that the oscillation period exceeds the preset value. CNT is 0, and it is latched to obtain CNT_IN=0, CNT_INB=1, indicating that the oscillation period is less than the preset value. Through the subsequent processing circuit composed of a half adder and a full adder, when CNT_IN=1, CNT_INB=0, the output code word OUT<4:0> is increased by 1 compared to IN<4:0>. When CNT_IN=0, CNT_INB=1, the input code word IN<4:0> is equivalent to adding 11111. Since the output is only 5 bits, it is equivalent to the output code word OUT<4:0> minus 1 compared to IN<4:0>, completing the code word conversion.

[0111] Preferably, adjusting the sampled signal includes:

[0112] When the rising edge of CLK_DOUT arrives, the output code word OUT<4:0> is triggered and latched as IN<4:0>. The reverse signal INB<4:0> sets the value of D<4:0> by selecting the PMOS and NMOS transmission level VB2 or VSS, and then adjusts the conductive part of the current mirror circuit to achieve current adjustment;

[0113] When the oscillation period exceeds the preset value, the input code word is increased by 1, the PMOS is turned on, so that the control end output is VB2, the current tube is turned on, and the current is increased to reduce the output time range of the voltage-to-time converter. When the oscillation period is less than the preset value, the input code word is reduced by 1, the NMOS is turned on, so that the control end output is VSS, the current tube is turned off, and the current is reduced to increase the output time range of the voltage-to-time converter.

[0114] Preferably, calibrating the reset circuit includes:

[0115] The RST_CAL signal is at a high level. With the rising edge of the data acquisition clock CLK of the ring oscillator, the asynchronous low-level reset D flip-flop (DFF0) and the asynchronous low-level reset D flip-flop (DFF1) flip the output level under the control of the clock CLK to achieve the function of four-division. The frequency of the output clocks CLK_SIN and CLK_DOUT is 1 / 4 of the original.

[0116] The present invention introduces a detection circuit at the cycle counting result of the ring oscillator. When the input is full swing, the result is fed back to the counter to adjust the size of the current source in the voltage-time conversion circuit and the output time range, thereby realizing automatic matching of the quantization range of the voltage-time conversion circuit and the time-to-digital conversion circuit. The circuit design of the present invention also has good PVT (process, voltage, temperature) robustness. By enabling calibration, the circuit can maintain stable performance under different process angles, power supply voltages and ambient temperature conditions. The detection result is fed back to the counter, and the circuit can adapt to these changes and automatically adjust to maintain a suitable matching range, thereby improving the reliability and adaptability of the circuit.

[0117] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A foreground calibration circuit of a time domain analog-to-digital converter, characterized in that: include: Calibrate the clock generation circuit, oscillation period detection and processing circuit, and current adjustment circuit; The calibration clock generation circuit is connected to the oscillation period detection and processing circuit and is used to calibrate the circuit clock; The oscillation period detection and processing circuit is connected to the counter and the current adjustment circuit, and is used to detect the oscillation period and adjust the oscillation period; The current adjustment circuit is connected to the input current and is used to adjust the magnitude of the current.

2. The foreground calibration circuit of a time domain analog-to-digital converter according to claim 1, characterized in that: The calibration clock generation circuit comprises: a D flip-flop (DFF0) with asynchronous low-level reset and a D flip-flop (DFF1) with asynchronous low-level reset; The reset terminal RST of the asynchronous low-level reset D flip-flop (DFF0) and the asynchronous low-level reset D flip-flop (DFF1) is connected to the calibration enable signal EN_CAL, the input clock terminal Clk of the asynchronous low-level reset D flip-flop (DFF0) is connected to the data acquisition clock CLK of the ring oscillator, and the data input terminal D and the reverse output terminal connected to the input clock terminal Clk of the D flip-flop (DFF1) with asynchronous low-level reset; The data input terminal D and the inverting output terminal of the D flip-flop (DFF1) with asynchronous low-level reset Connected, reverse output Connected to the sampling clock CLK_SIN, and the positive output terminal Q is connected to the code word output clock CLK_DOUT.

3. The foreground calibration circuit of a time domain analog-to-digital converter according to claim 1, characterized in that: The oscillation period detection and processing circuit comprises: a D flip-flop (DFF2), a D flip-flop with asynchronous low-level reset (DFF3), a D flip-flop with asynchronous low-level reset (DFF4), a D flip-flop with asynchronous low-level reset (DFF5), a D flip-flop with asynchronous low-level reset (DFF6), a D flip-flop with asynchronous low-level set (DFF7), a half adder (A1), a full adder (A2), a full adder (A3), a full adder (A4), and a full adder (A5); The input terminal D of the D flip-flop (DFF2) is connected to the cycle counting signal CNT, the input clock terminal Clk is connected to the sampling clock CLK_SIN, the positive output terminal Q is connected to the detection signal CNT_IN, and the reverse output terminal Q is connected to the detection signal CNT_INB; The input terminal A of the half adder (A1) is connected to the signal IN <0> , the input terminal B is connected to the power supply voltage VDD, and the output terminal summation result S is connected to the signal OUT <0> , the carry result CO at the output is connected to the input CI of the next full adder (A2); The input terminal A of the full adder (A2) is connected to the signal IN <1> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <1> , the carry result CO at the output is connected to the input CI of the next full adder (A3); The input terminal A of the full adder (A3) is connected to the signal IN <2> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <2> , the carry result CO at the output is connected to the input CI of the next full adder (A3); The input terminal A of the full adder (A4) is connected to the signal IN <3> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <3> , the carry result CO at the output is connected to the input terminal CI of the next stage full adder (A5); The input terminal A of the full adder (A5) is connected to the signal IN <4> , the input terminal B is connected to the detection signal CNT_INB, and the output terminal summation result S is connected to the signal OUT <4> ; The input terminal D of the asynchronous low-level reset D flip-flop (DFF3) is connected to the signal OUT <0> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <0> , the reverse output terminal Q is connected to the signal INB <0> ; The input terminal D of the asynchronous low-level reset D flip-flop (DFF4) is connected to the signal OUT <1> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <1> , the reverse output terminal Q is connected to the signal INB <1> ; The input terminal D of the asynchronous low-level reset D flip-flop (DFF5) is connected to the signal OUT <2> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <2> , the reverse output terminal Q is connected to the signal INB <2> ; The input terminal D of the asynchronous low-level reset D flip-flop (DFF6) is connected to the signal OUT <3> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <3> , the reverse output terminal Q is connected to the signal INB <3> ; The input terminal D of the asynchronous low-level set D flip-flop (DFF7) is connected to the signal OUT <4> , the input clock terminal Clk is connected to the code word output clock CLK_DOUT, the input set terminal SET is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN <4> , the reverse output terminal Q is connected to the signal INB <4> .

4. The foreground calibration circuit of a time domain analog-to-digital converter according to claim 1, characterized in that: The current regulating circuit comprises: a current source (I1), a PMOS tube (PM1), a PMOS tube (PM2), a PMOS tube (PM3), a PMOS tube (PM4), a PMOS tube (PM5), an NMOS tube (NM1), an NMOS tube (NM2), an NMOS tube (NM3), an NMOS tube (NM4), an NMOS tube (NM5), an NMOS tube (NM6), an NMOS tube (NM7), an NMOS tube (NM8), an NMOS tube (NM9), an NMOS tube (NM10), an NMOS tube (NM11), an NMOS tube (NM12), an NMOS tube (NM13), an NMOS tube (NM14), an NMOS tube (NM15), an NMOS tube (NM16), an NMOS tube (NM17), an NMOS tube (NM18), an NMOS tube (NM19), and a resistor (R1), and the size ratio of the five-way adjustable current mirror part is 16:8:4:2:1; The input end of the current source (I1) is connected to the power supply VDD, the output end is connected to VB1, both ends of the resistor (R1) are connected to VB1 and VB2, the drain of the NMOS tube (NM6) is connected to VB2, the gate is connected to VB1, the source is connected to the drain of the NMOS tube (NM13), the gate of the NMOS tube (NM13) is connected to VB2, and the source is connected to VSS; The drain terminal of the NMOS tube (NM7) is connected to the output terminal IBout, the gate is connected to VB1, the source is connected to the drain terminal of the NMOS tube (NM14), the gate terminal of the NMOS tube (NM14) is connected to VB2, and the source terminal is connected to VSS; The drain of the NMOS tube (NM8) is connected to the output terminal IBout, and the gate is connected to D <0> , the source is connected to the drain of the NMOS tube (NM15), the gate of the NMOS tube (NM15) is connected to VB2, and the source is connected to VSS; The drain of the NMOS tube (NM9) is connected to the output terminal IBout, and the gate is connected to D <1> , the source is connected to the drain of the NMOS tube (NM16), the gate of the NMOS tube (NM16) is connected to VB2, and the source is connected to VSS; The drain of the MOS tube (NM10) is connected to the output terminal IBout, and the gate is connected to D <2> , the source is connected to the drain of the NMOS tube (NM17), the gate of the NMOS tube (NM17) is connected to VB2, and the source is connected to VSS; The drain of the NMOS tube (NM11) is connected to the output terminal IBout, and the gate is connected to D <3> , the source is connected to the drain of the NMOS tube (NM18), the gate of the NMOS tube (NM18) is connected to VB2, and the source is connected to VSS; The drain of the NMOS tube (NM12) is connected to the output terminal IBout, and the gate is connected to D <4> , the source is connected to the drain of the NMOS tube (NM19), the gate of the NMOS tube (NM19) is connected to VB2, and the source is connected to VS; The drain of the PMOS tube (PM1) is connected to the bias voltage VB2, and the gate is connected to INB <0> , the source is connected to D <0> , NMOS tube NMOS tube (NM1) drain connected to VSS, gate connected to INB <0> , the source is connected to D <0> ; The drain of the PMOS tube (PM2) is connected to the bias voltage VB2, and the gate is connected to INB <1> , the source is connected to D <1> , NMOS tube NMOS tube (NM2) drain connected to VSS, gate connected to INB <1> , the source is connected to D <1> ; The drain of the PMOS tube (PM3) is connected to the bias voltage VB2, and the gate is connected to INB <2> , the source is connected to D <2> , NMOS tube NMOS tube (NM3) drain connected to VSS, gate connected to INB <2> , the source is connected to D <2> ; The drain of the PMOS tube (PM4) is connected to the bias voltage VB2, and the gate is connected to INB <3> , the source is connected to D <3> , NMOS tube NMOS tube (NM1) drain connected to VSS, gate connected to INB <3> , the source is connected to D <3> ; The drain of the PMOS tube (PM5) is connected to the bias voltage VB2, and the gate is connected to INB <4> , the source is connected to D <4> , NMOS tube NMOS tube (NM1) drain connected to VSS, gate connected to INB <4> , the source is connected to D <4> .

5. A method for controlling a foreground calibration circuit of a time domain analog-to-digital converter, applied to a foreground calibration circuit of a time domain analog-to-digital converter according to any one of claims 1 to 4, characterized in that: include: Reset the circuit; Calibrate the circuit after reset.

6. The method for controlling a foreground calibration circuit of a time domain analog-to-digital converter according to claim 5, characterized in that: The calibrating the reset circuit comprises: Sampling the signal; The sampled signal is adjusted.

7. The method for controlling a foreground calibration circuit of a time domain analog-to-digital converter according to claim 5, characterized in that: The resetting of the circuit comprises: The RST_CAL signal is at a low level, the EN_CAL signal is at a low level, the outputs of the D flip-flop (DFF3), the D flip-flop with asynchronous low-level reset (DFF4), the D flip-flop with asynchronous low-level reset (DFF5), the D flip-flop with asynchronous low-level reset (DFF6), and the D flip-flop with asynchronous low-level set (DFF7) are reset, and the corresponding inverted output signal INB<4:0>=01111 controls the PMOS tube (PM1), NMOS tube (NM2), NMOS tube (NM3), NMOS tube (NM4), and NMOS tube (NM5) to turn on, making the D <4> =VB2,D <0> ,D <1> ,D <2> , D <3> All are VSS, so that the NMOS tube (NM12) is turned on, and the input current is composed of two branches of the NMOS tube (NM7), the NMOS tube (NM14) and the NMOS tube (NM12), the NMOS tube (NM19).

8. The method for controlling a foreground calibration circuit of a time domain analog-to-digital converter according to claim 6, characterized in that: The sampling of the signal comprises: When the rising edge of CLK_SIN arrives, the D flip-flop (DFF2) samples the cycle count result CNT. If CNT is 1, it is latched to obtain CNT_IN=1, CNT_INB=0, indicating that the oscillation period exceeds the preset value. CNT is 0, and it is latched to obtain CNT_IN=0, CNT_INB=1, indicating that the oscillation period is less than the preset value. Through the subsequent processing circuit composed of a half adder and a full adder, when CNT_IN=1, CNT_INB=0, the output code word OUT<4:0> is increased by 1 compared to IN<4:0>. When CNT_IN=0, CNT_INB=1, the input code word IN<4:0> is equivalent to adding 11111. Since the output is only 5 bits, it is equivalent to the output code word OUT<4:0> minus 1 compared to IN<4:0>, completing the code word conversion.

9. The method for controlling a foreground calibration circuit of a time domain analog-to-digital converter according to claim 6, characterized in that: The adjusting the sampled signal comprises: When the rising edge of CLK_DOUT arrives, the output code word OUT<4:0> is triggered and latched as IN<4:0>. The reverse signal INB<4:0> sets the value of D<4:0> by selecting the PMOS and NMOS transmission level VB2 or VSS, and then adjusts the conductive part of the current mirror circuit to achieve current adjustment; When the oscillation period exceeds the preset value, the input code word is increased by 1, the PMOS is turned on, so that the control end output is VB2, the current tube is turned on, and the current is increased to reduce the output time range of the voltage-to-time converter. When the oscillation period is less than the preset value, the input code word is reduced by 1, the NMOS is turned on, so that the control end output is VSS, the current tube is turned off, and the current is reduced to increase the output time range of the voltage-to-time converter.

10. The method for controlling a foreground calibration circuit of a time domain analog-to-digital converter according to claim 5, characterized in that: The calibrating the reset circuit comprises: The RST_CAL signal is at a high level. With the rising edge of the data acquisition clock CLK of the ring oscillator, the asynchronous low-level reset D flip-flop (DFF0) and the asynchronous low-level reset D flip-flop (DFF1) flip the output level under the control of the clock CLK to achieve the function of four-division. The frequency of the output clocks CLK_SIN and CLK_DOUT is 1 / 4 of the original.

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