A digital front-end calibration system and method for a successive approximation analog-to-digital converter based on RRAM

Abstract

The present invention discloses a digital front-end calibration system and method for a successive approximation analog-to-digital converter based on RRAM, belonging to the technical field of integrated circuits. The system includes: a stepped voltage generation module, a state monitoring module, an information storage module, and a data processing module; the stepped voltage generation module is only effective in the calibration mode, and the data processing module is effective in the working mode; the state detection module receives the output of the ADC to be calibrated and detects its mode, and the information storage module uses a storage array unit based on RRAM to store the calibration code generated by the stepped voltage generation module in the calibration mode, and continuously inputs data to the data processing module in the working mode for accumulation and truncation to generate a calibrated output code. The effective accuracy and conversion linearity of the SAR ADC to be calibrated are improved, the requirements for the size and area of the unit capacitance in the DAC of the SAR ADC to be calibrated are reduced, the power consumption of digital-to-analog conversion is reduced, the stability of data is improved, and the calibration period is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field related to integrated circuits, and more specifically, relates to a digital front-end calibration system and method for a successive approximation analog-to-digital converter based on RRAM. Background Art

[0002] For a successive approximation analog-to-digital converter (SAR ADC), the switching energy consumption of its capacitor array is the main energy consumption. If the area of the unit capacitor can be reduced, its energy consumption will be greatly reduced. However, reducing the area of the unit capacitor will increase the mismatch rate between unit capacitors, making the linearity of the entire ADC unable to meet the requirements. Front-end calibration of the SAR ADC can compensate for the error caused by capacitor mismatch to a certain extent, improve the linearity of the system, and reduce the requirement of linearity for capacitor mismatch.

[0003] However, the current digital front-end calibration schemes for SAR ADCs do not have non-volatility, resulting in the loss of stored data every time the power is turned off. Every time the SAR ADC works, it has to enter the calibration mode, which greatly wastes time and energy consumption.

[0004] Therefore, there is a need to design a front-end calibration scheme for SAR ADCs with non-volatility and extremely low power consumption, which is used to calibrate the error caused by capacitor mismatch of the ADC, improve the linearity of the SAR ADC, relax the requirement for the capacitor mismatch rate, and improve the energy efficiency of the entire SAR ADC system. Summary of the Invention

[0005] Aiming at the defects of the related technologies, the purpose of the present invention is to provide a digital front-end calibration system and method for a successive approximation analog-to-digital converter based on RRAM, aiming to solve the problem that the existing digital front-end calibration schemes do not have non-volatility, resulting in the loss of stored data every time the power is turned off, and every time it has to enter the calibration mode before working, which greatly wastes time and energy consumption.

[0006] To achieve the above purpose, in the first aspect, the present invention provides a digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM, including: a stepped voltage generation module, a state monitoring module, an information storage module, and a data processing module; the stepped voltage generation module is only effective in the calibration mode and is turned off in the working mode; the data processing module is turned off in the calibration mode and is effective in the working mode;

[0007] The step voltage generation module includes a counter with an N+M-bit width and a digital-to-analog converter with a resolution of N+M bits. The input end of the counter is connected to an external clock, the output end is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input end of the successive approximation analog-to-digital converter to be calibrated. The counter is used to generate a continuously incrementing digital code, and the digital-to-analog converter is used to convert the digital code into a continuously rising analog step voltage Vt and output it to the successive approximation analog-to-digital converter to be calibrated. Wherein, both M and N are positive integers;

[0008] The state monitoring module includes a state detection logic unit and a selector. In the calibration mode, the input end of the state detection logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the output end is connected to the input end of the selector, and the output end of the selector is connected to the information storage module. The state detection logic unit is used to detect the pattern of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the pattern of the digital output code. In the working mode, the input end of the state monitoring logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated. The state detection logic unit is used to detect the pattern of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the pattern of the digital output code;

[0009] The information storage module includes an address control unit and a storage array unit based on RRAM. In the calibration mode, the storage array unit is connected to the counter and is used to store N (N+M)-bit digital calibration codes generated by the step voltage generation module. The address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module and write the digital calibration codes into the storage array. In the working mode, the storage array unit is connected to the data processing module. The address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module and read the digital calibration codes from the storage array;

[0010] The data processing module includes an N+M-bit data accumulator and an N-bit data clipper. The input end of the data accumulator is connected to the information storage module, and the output end is connected to the input end of the data clipper. The data accumulator is used to accumulate the selected N+M-bit digital calibration codes in the information storage module, and the data clipper is used to clip the data and only retain its first N bits as the output of the calibrated successive approximation analog-to-digital converter.

[0011] Optionally, the counter receives an external clock signal and increments its output at the rising edge of each clock, generating a digital code with a bit width of N + M bits;

[0012] Under the control of the system clock, the digital-to-analog converter periodically converts the digital output code of the counter into an analog voltage to obtain a stepped voltage Vt, which is output to the successive approximation analog-to-digital converter; the stepped voltage Vt includes all cases of the N-bit digital output.

[0013] Optionally, in the calibration mode, the state monitoring module is used to automatically detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and detect whether its mode is that only one bit is "1" and all other bits are "0". If the detection result is true, then detect the position where the "1" is located in the digital output code. The selector is used to output different control signals to the information storage module according to the detected position; if the detection result is false, then directly skip this calibration cycle;

[0014] In the working mode, the state monitoring module is used to automatically monitor the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, detect the number n of digital codes with "1", and set the working cycle of this working mode to n accordingly, and detect the position of each "1" in the digital output code. The selector is used to respond to different control signals for each different "1" in the next n working cycles.

[0015] Optionally, in the calibration mode, the address control unit in the information storage module is used to receive the control signal responded by the state detection module, select different columns in the storage array, and store the digital output code corresponding to this cycle in the corresponding position as the digital calibration code;

[0016] In the working mode, the address control unit in the information storage module is used to receive the control signal responded by the state detection module, select different columns in the storage array, and read out the digital calibration code stored in the storage array according to the cycle and transmit it to the data processing module.

[0017] Optionally, the number of the storage array units is N * (N + M); each storage array unit includes 7 MOS transistors and 2 RRAMs. Among them, 3 MOS transistors are used as signal gating switches, 4 MOS transistors form an inverter connected end to end to enhance the storage signal, and 2 RRAMs are used as the medium for storing information;

[0018] In the calibration mode, the storage array unit is in the write mode and writes the digital calibration codes one by one;

[0019] In the working mode, the storage array unit is in the read mode, and the digital calibration codes are read out one by one to the data processing module.

[0020] Optionally, the data accumulator of the data processing module is used to accumulate the received N+M-bit digital calibration codes, and determine whether the accumulated result exceeds N+M bits. If it exceeds, N+M-bit "1" is output. If it does not exceed, the data truncator performs a truncation operation on the accumulated data, and only the high N bits of the data are retained as the output.

[0021] Optionally, N = 8 and M = 2.

[0022] In a second aspect, the present invention also provides a digital front-end calibration method for a successive approximation analog-to-digital converter based on RRAM, which is executed based on the digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM as described in any one of the first aspects. For a successive approximation analog-to-digital converter to be calibrated, a calibration mode is first performed, and subsequent modes are all working modes;

[0023] When in the calibration mode, the method includes:

[0024] The stepped voltage generation module generates a stepped voltage Vt and inputs it to the successive approximation analog-to-digital converter to be calibrated, so that it generates different digital output codes;

[0025] The state monitoring module detects the mode of the digital output codes. If it conforms to the preset output mode, the selector responds to a control signal according to the positions of "1" in the digital output codes and injects it into the storage array unit to control its writing operation of the corresponding digital calibration codes;

[0026] When in the working mode, the method includes:

[0027] The state monitoring module detects the mode of the digital output codes of the calibrated successive approximation analog-to-digital converter, records the number of "1" in its digital output codes and the positions of each "1", and the selector responds to different control signals according to different digital output codes and controls the storage array unit to read out the corresponding digital calibration codes respectively;

[0028] The data processing module obtains the digital calibration codes in cycles for data accumulation and truncation, and outputs the calibrated digital output codes.

[0029] Through the above technical solutions conceived by the present invention, compared with the prior art, the following beneficial effects can be achieved:

[0030] 1. A digital front-end calibration system for a successive approximation analog-to-digital converter (SAR ADC) based on RRAM provided by the present invention uses RRAM as a medium for storing digital signals. All digital signals are stored in the RRAM, making the stored data non-volatile and not lost due to power-on or power-off. Therefore, the stability is ensured. Once written, there will be no signal leakage, increasing the calibration accuracy and enhancing the anti-interference ability. Thus, for this calibration system, only one calibration mode is required for the SAR ADC. After obtaining sufficient calibration codes, when using this ADC again, there is no need for further calibration and it can directly enter the working mode. Therefore, it greatly saves the time consumed by calibration, significantly reduces the power consumption required for calibration, and improves the speed.

[0031] 2. A digital front-end calibration system for a successive approximation analog-to-digital converter (SAR ADC) based on RRAM provided by the present invention, during the calibration mode, after the stored N*M-bit digital calibration codes are accumulated and replace the digital output codes of the SAR ADC to be calibrated, the dynamic performance of the ADC, including the number of effective bits, is significantly improved, the unit capacitance value of the ADC is reduced, thereby greatly reducing its energy consumption, improving the energy efficiency of the calibrated ADC, and also reducing its area.

[0032] 3. A digital front-end calibration system for a successive approximation analog-to-digital converter (SAR ADC) based on RRAM provided by the present invention mainly includes a multiplexer, an accumulator, and a storage array composed of RRAM. It can complete the calibration function with relatively simple hardware overhead, reduce the area for the entire system, and improve the energy efficiency ratio of the system. Among them, RRAM is used to replace the traditional SRAM for data storage. RRAM has the advantages of small area, low power consumption, and high integration, so it can greatly save the area and power consumption required for storage. Brief Description of the Drawings

[0033] Figure 1 It is the system structure block diagram of the detection, search, and read-in part of the calibration codes in the digital front-end calibration system for a successive approximation analog-to-digital converter (SAR ADC) based on RRAM in the embodiment of the present application.

[0034] Figure 2 It is the system structure block diagram of the read-out part of the calibration codes in the digital front-end calibration system for a successive approximation analog-to-digital converter (SAR ADC) based on RRAM in the embodiment of the present application.

[0035] Figure 3 It is the calibration principle of the digital front-end calibration system for a successive approximation analog-to-digital converter (SAR ADC) based on RRAM in the embodiment of the present application.

[0036] Figure 4 It is the flowchart of the calibration algorithm of the digital front-end calibration system for a successive approximation analog-to-digital converter (SAR ADC) based on RRAM in the embodiment of the present application.

[0037] Figure 5 It is a schematic diagram of the RRAM storage array structure in the embodiment of the present application.

[0038] Figure 6 It is a schematic diagram of the specific circuit structure of the RRAM storage cell in the embodiment of the present application. Detailed implementation manners

[0039] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0040] The following will describe the content involved in the above embodiments in conjunction with a preferred embodiment.

[0041] Embodiment 1

[0042] The present invention provides a digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM, including: a stepped voltage generation module, a state monitoring module, an information storage module, and a data processing module; the stepped voltage generation module is only effective in the calibration mode and is turned off in the working mode; the data processing module is turned off in the calibration mode and is effective in the working mode;

[0043] The stepped voltage generation module includes a counter with an N+M-bit width and a digital-to-analog converter with a resolution of N+M bits. The input end of the counter is connected to an external clock, the output end is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input end of the successive approximation analog-to-digital converter to be calibrated; the counter is used to generate a continuously incrementing digital code, and the digital-to-analog converter is used to convert the digital code into an increasingly rising analog stepped voltage Vt and output it to the successive approximation analog-to-digital converter to be calibrated; where M and N are both positive integers;

[0044] The state monitoring module includes a state detection logic unit and a selector; in the calibration mode, the input end of the state detection logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the output end is connected to the input end of the selector, and the output end of the selector is connected to the information storage module; the state detection logic unit is used to detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the mode of the digital output code; in the working mode, the input end of the state monitoring logic unit is connected to the output end of the calibrated successive approximation analog-to-digital converter, the state detection logic unit is used to detect the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, and the selector is used to respond to different control signals according to the mode of the digital output code;

[0045] The information storage module includes an address control unit and a storage array unit based on RRAM; in the calibration mode, the storage array unit is connected to the counter and is used to store the N (N+M)-bit digital calibration codes generated by the staircase voltage generation module; the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module and write the digital calibration codes into the storage array; in the working mode, the storage array unit is connected to the data processing module, and the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module and read out the digital calibration codes from the storage array;

[0046] The data processing module includes an N+M-bit data accumulator and an N-bit data truncator. The input end of the data accumulator is connected to the information storage module, and the output end is connected to the input end of the data truncator; the data accumulator is used to accumulate the selected N+M-bit digital calibration codes in the information storage module, and the data truncator is used to truncate the data, only retaining its first N bits as the output of the calibrated successive approximation analog-to-digital converter.

[0047] When the RRAM-based digital front-end calibration method provided by the present invention is actually working, it is divided into two parts. First, enter the calibration mode. After the calibration is completed, enter the working mode when the calibrated ADC is working, that is, read out the calculated and stored calibration codes in the calibration mode to calibrate the output code of the ADC. The hardware system structure diagram of the calibration mode of the RRAM-based digital front-end calibration method is as Figure 1 shown. The hardware system corresponding to the calibration mode mainly consists of four modules, namely, a staircase voltage generation module, an ADC module to be calibrated, a state monitoring module, and an information storage module.

[0048] After the calibration mode is completed, the calibrated SAR ADC finishes calibration and starts to enter the working mode. The hardware system corresponding to the working mode mainly consists of four modules, namely the ADC to be calibrated module, the status monitoring module, the information storage module, and the data processing module. The system block diagram of the data reading and processing part in the working mode of the RRAM-based digital front-end calibration scheme for SAR ADC is as Figure 2 shown.

[0049] In the calibration mode, the analog staircase voltage Vt generated by the staircase voltage generation module is stored. The analog staircase voltage Vt is input into the successive approximation analog-to-digital converter to be calibrated. After passing through the analog-to-digital converter, a digital output code is generated. The status detection module receives the digital output code of the ADC to be calibrated and detects its mode, and selectively stores the digital output code at the corresponding position in the storage array as the digital calibration code. The RRAM storage array is composed of storage cells with a 7T2R structure. In the working mode, the information storage module continuously inputs data into the data processing module for accumulation and truncation to generate the calibrated output code.

[0050] Through the above structure, the effective precision and conversion linearity of the calibrated SAR ADC can be improved, and the requirements for the size and area of the unit capacitance in the DAC of the calibrated SAR ADC can be reduced. The power consumption of digital-to-analog conversion is reduced through the front-end calibration method, and a non-volatile memristor is introduced for storage, improving the data stability and reducing the calibration period.

[0051] Optionally, the counter receives an external clock signal and increments its output at the rising edge of each clock to generate a digital code with a bit width of N + M bits;

[0052] The digital-to-analog converter periodically converts the digital output code of the counter into an analog voltage under the control of the system clock to obtain the staircase voltage Vt, and outputs it to the successive approximation analog-to-digital converter; the staircase voltage Vt includes all cases of N-bit digital output.

[0053] Optionally, in the calibration mode, the status monitoring module is used to automatically detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and detect whether its mode is that only one bit is "1" and all other bits are "0". If the detection result is true, the position where the "1" is located in the digital output code is detected, and the selector is used to output different control signals to the information storage module according to the detected position; if the detection result is false, this calibration period is directly skipped;

[0054] In the working mode, the state monitoring module is used to automatically monitor the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, detect the number n of digital codes containing '1', and set the working cycle of this working mode to n based on this, and detect the positions of each '1' in the digital output code. The selector is used to respond to different control signals for each different '1' in the next n working cycles.

[0055] The solution of the present invention will be specifically described with reference to the accompanying drawings. As Figure 3 shown, it is a schematic diagram of the calibration principle of the digital front-end calibration solution of the RRAM-based SAR ADC. A counter generates a continuously incrementing digital input signal Din, and the number of bits of this digital signal is N + N extra bits, where N refers to the resolution N of the calibrated SAR ADC, and N extra refers to the difference between the number of bits of the digital signal output by the counter and the number of bits of the ADC. The continuously incrementing digital input signal Din drives an ideal DAC, so that the DAC generates a very ideal continuously rising staircase signal Vt. The staircase signal Vt is input into the calibrated SAR ADC, sampled by the ADC, and after N conversion cycles, the calibrated SAR ADC outputs an N-bit digital signal Dout.

[0056] When the output result Dout is 00...001, that is, only the LSB is '1' and the rest of the bits are all '0', then the corresponding Din in this case will be stored in the register implemented by RRAM. After the subsequent calibration mode is completed, the SAR ADC enters the working mode. When the LSB code is '1' in the working mode of the SAR ADC, then this Din will be called and replace the current output Dout. Then the staircase signal Vt continues to rise and is continuously input into the calibrated ADC. When the output result Dout of the ADC is 00...010, the above process is repeated, and the corresponding Din is stored in the corresponding RRAM register. Then the Vt signal continues to rise until the registers corresponding to all bits of Dout have stored the corresponding calibration code Din, and the calibration mode ends.

[0057] As Figure 4As shown in the figure, the flowchart of the calibration algorithm for the digital front-end calibration scheme of the RRAM-based SAR ADC. The ideal staircase signal Vt(i) generated by the counter and the ideal DAC is sampled and input by the SAR ADC. After N conversion cycles, the ADC outputs an N-bit digital signal Dout. Then, the output mode detection module will detect whether Dout contains only one '1' and the rest are '0'. If the detection result is yes, the detection module will continue to detect whether the register corresponding to the bit with the code value '1' is empty. If the corresponding register is empty, then the corresponding Din at this time, that is, the calibration code corresponding to this bit, will be written into the RRAM-based register; if the corresponding register is not empty, the cycle ends, the output value i of the counter is incremented by 1, and then the staircase signal Vt rises and continues to be input into the SAR ADC to start the next cycle; if the detection result is that Dout does not contain only one '1', then this cycle ends prematurely and directly enters the next cycle as described above.

[0058] There are two decision conditions for the end of the calibration mode. Meeting any one of the conditions can be directly regarded as the calibration being completed. These two decision conditions are respectively: whenever an operation of writing to the RRAM register is completed, the states of all registers are detected. If all the RRAM registers have been written full, it is regarded as the calibration being completed; or whenever the output i of the counter is incremented by one, it is judged whether the value of i is less than 2 N+Nextra , if the judgment result is no, it is also regarded as the calibration being completed.

[0059] Optionally, in the calibration mode, the address control unit in the information storage module is used to receive the control signal responded by the status detection module, select different columns in the storage array, and store the digital output code corresponding to this cycle to the corresponding position as the digital calibration code;

[0060] In the working mode, the address control unit in the information storage module is used to receive the control signal responded by the status detection module, select different columns in the storage array, and read out the digital calibration code stored in the storage array cycle by cycle and transmit it to the data processing module.

[0061] As Figure 5 shown, the schematic diagram of the RRAM storage array structure. The information storage module mainly consists of two parts, namely an 8*10 storage array based on RRAM and an address control logic module. The address control logic mainly includes a counter, an address pointer, and some small control logics.

[0062] In this embodiment, N = 8 and M = 2 are set. In this embodiment, the capacity of the RRAM storage array is 8*10, where 8 is the resolution N of the SAR ADC to be calibrated in this embodiment, and 10 is the bit width N+N of the output of the counter in this embodimentextra This RRAM storage array contains 8 RRAM registers, each with a width of 10 bits. Among them, each bit of data is stored in a storage cell composed of a 7T2R structure based on RRAM. In addition, the RRAM storage array also has a pointer controlled by pattern detection logic. After the pattern detection module detects that the output Dout of the SAR ADC at a certain moment meets the pattern detection condition, it determines the position of the '1' in Dout and passes the address of this bit to the pointer in the RRAM storage array, causing the pointer to point to the corresponding 10-bit register in the RRAM storage array. In this way, the corresponding 10-bit calibration code Din is stored in the corresponding register in the RRAM storage array. When the input signal Vt is swept from 0 to the MSB bit of the SAR ADC to be calibrated, that is, after the pointer finally points to the register corresponding to the MSB in the RRAM storage array, after the write operation is completed, it can be directly regarded as the calibration being completed, saving subsequent unnecessary calibration cycles and shortening the time required for the calibration mode. Compared with sweeping Vt across the full range, this solution can save 50% of the calibration cycles.

[0063] In the above content, each storage cell of the 8*10 RRAM storage array is not composed of traditional SRAM or DRAM, but is composed of a 7T2R structure based on RRAM. The schematic diagram of this structure is as attached Figure 6 shown.

[0064] Optionally, the number of the storage array units is N*(N + M); each of the storage array units includes 7 MOS transistors and 2 RRAMs. Among them, 3 MOS transistors serve as signal gating switches, 4 MOS transistors form an inverter connected end to end to enhance the stored signal, and 2 RRAMs serve as the medium for storing information;

[0065] In the calibration mode, the storage array units are in the write mode, and the digital calibration codes are written one by one;

[0066] In the working mode, the storage array units are in the read mode, and the digital calibration codes are read out one by one to the data processing module.

[0067] Specifically, the storage array unit consists of three transistors that control switches, two RRAM units responsible for information storage, and two inverters connected end to end and composed of four transistors. The input end of this storage unit is the drain of the switch transistor, named Din, and the output end is the source of the switch transistor, named Dout. The gate of this switch transistor is controlled by the WR signal, and the gates of the other two switch transistors are controlled by the E signal and the R signal respectively. Here, WR represents the read / write operation, E represents enable, and R represents the read operation. The source of the switch transistor controlled by the E signal is connected to the memristor R1, and the other end of this memristor R1 is connected to the voltage Vc, which is used to store the written 1-bit information; the source of the switch transistor controlled by the R signal is connected to the memristor R2, and the other end of this memristor R2 is connected to the ground, which is used to read the 1-bit information stored by the memristor R1.

[0068] Furthermore, the working principle of the 7T2R unit based on RRAM is as follows:

[0069] In the reset stage, all control signals, namely the WR signal, the E signal, and the R signal, are at low levels, turning off the three controlled switch transistors, and the initial states of the memristors R1 and R2 are both in the high-resistance state. When a 1-bit signal Din requests to be written, at this time the WR signal changes from low level to high level, indicating that the signal is valid, and at the same time turns on the controlled switch transistor, directly passing Din to the next node. At this time, the E signal also changes from low level to high level, indicating that the signal is valid. At the same time, the controlled switch transistor is turned on, but at this time the R signal is still at a low level, that is, the switch transistor controlled by the R signal remains off. At this time, Din will only be transmitted to the lower plate of the memristor R1, and the memristor R1 writes and stores the information by reducing the resistance state or keeping the resistance state unchanged; when Din is 1, the memristor R1 changes from the high-resistance state to the low-resistance state, representing the storage of "1"; when Din is 0, the memristor R1 keeps the initial high-resistance state unchanged, representing the storage of "0". When the next clock cycle arrives, the WR signal and the E signal are both reset to low levels, and the switch transistors are turned off. Thus, the writing of one piece of information is completed, and the information is stored in the form of different resistance states of the memristor R1.

[0070] When the read request for the stored 1-bit signal is made, at this time, the WR signal remains low and unchanged, the controlled switch transistor is turned off, isolating the input from the output. Then, both the E signal and the R signal simultaneously change from low level to high level, indicating that the signal is valid. At the same time, the two controlled switch transistors are turned on. At this time, a short pulse signal is input at the Vc terminal. Since both the E signal and the R signal are valid, the memristors R1 and R2 can be regarded as being directly connected. That is, the stored information can be read out by the resistance voltage division of the two memristors. If the stored information is "1", then the memristor R1 is in the low-resistance state and the memristor R2 is in the high-resistance state. After the resistance voltage division of the memristors, the output at the output terminal is Vc. Therefore, as long as the value of Vc is controlled to be greater than half of VDD, the output can be pulled to "1" through the subsequent inverter. If the stored information is "0", then the memristor R1 is in the high-resistance state and at this time the memristor R2 is also in the high-resistance state. After the resistance voltage division of the memristors, the output at the output terminal is approximately Vc / 2. Therefore, as long as the value of Vc / 2 is controlled to be less than half of VDD, the output can be pulled to "0" through the subsequent inverter. So as long as the high-level Vc of the short pulse is controlled to be less than VDD but greater than VDD / 2, such as taking 3 / 4VDD, the signal can be correctly read out, and there is enough noise margin at both the upper and lower ends, increasing the correctness and stability of signal reading. The two inverters connected end to end are responsible for signal holding during both read and write operations. Especially during read operations, the driving ability of the signal is enhanced.

[0071] Optionally, the data accumulator of the data processing module is used to accumulate the received N+M-bit digital calibration code, and judge whether the accumulated result exceeds N+M bits. If it exceeds, N+M bits of "1" are output. If it does not exceed, the data cutter performs a cutting operation on the accumulated data, and only retains the high N bits of the data as the output.

[0072] In the embodiment of the present invention, the storage part uses RRAM as the medium for storing digital signals, and all digital signals are stored in RRAM, making the stored data non-volatile and not lost due to power-on and power-off. The calibration system only needs to perform a calibration mode for the SAR ADC once. After obtaining enough calibration codes, when using this ADC again, there is no need to perform calibration again and it can directly enter the working mode. By reducing the unit capacitance area of the SAR ADC, its power consumption is reduced, and RRAM is used for storage therein, which is non-volatile and is suitable for the application scenario of in-memory computing. It solves the technical problem that the existing digital front-end calibration scheme is not non-volatile, resulting in the loss of stored data every time after power-off, and entering the calibration mode every time before work, which greatly wastes time and energy consumption. It realizes improving the stability and anti-interference ability of calibration, and has a smaller area and lower power consumption; saves the time and power consumption required for calibration, and improves the speed.

[0073] Embodiment 2

[0074] The present invention also provides a digital front-end calibration method for a successive approximation analog-to-digital converter based on RRAM, which is executed based on the digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM described in any one of the first embodiments. For a successive approximation analog-to-digital converter to be calibrated, a calibration mode is first performed, and subsequent modes are all working modes;

[0075] When in the calibration mode, the method includes:

[0076] The stepped voltage generation module generates a stepped voltage Vt and inputs it into the successive approximation analog-to-digital converter to be calibrated, so as to generate different digital output codes;

[0077] The state monitoring module detects the pattern of the digital output code. If it conforms to a preset output pattern, the selector responds a control signal according to the position where "1" is located in the digital output code, and injects it into the storage array unit to control its writing operation of the corresponding digital calibration code;

[0078] When in the working mode, the method includes:

[0079] The state monitoring module detects the pattern of the digital output code of the successive approximation analog-to-digital converter to be calibrated, records the number of "1"s in its digital output code and the position where each "1" is located. The selector responds different control signals according to different digital output codes, and controls the storage array unit to read out the corresponding digital calibration codes respectively;

[0080] The data processing module obtains the digital calibration codes in cycles for data accumulation and truncation, and outputs the calibrated digital output codes.

[0081] In a specific embodiment, when the calibration mode starts, wait for a rising edge of the start clock, the counter starts to work, and outputs a 10-bit continuously incrementing digital code. This digital code has 2 bits of redundancy compared to the 8-bit SAR ADC to be calibrated in this embodiment. Since these calibration codes will be accumulated in the working mode to replace the output code of the SAR ADC for calibration, making 2 bits of precision redundancy is relatively appropriate; while increasing the calibration accuracy, it does not introduce too many RRAM storage units, reduces the complexity of the involved logic circuits, and saves power consumption and hardware overhead.

[0082] The continuously incrementing 10-bit digital code is input into a 10-bit DAC. At this time, the incrementing digital code is converted into an ideal stepped voltage Vt in the analog domain. The accuracy of Vt, i.e., the step size of the stepped voltage, is 1 LSB value of the 10-bit DAC. Since the resolution or accuracy of the pre-stage DAC is higher than that of the 8-bit SAR ADC to be calibrated in the post-stage, the step size of the stepped voltage is small enough to cover all equivalent input signals of the post-stage SAR ADC. That is, after the stepped signal Vt with 10-bit accuracy is input into the 8-bit SAR ADC to be calibrated, the output code value of this ADC must gradually increase from the minimum value 0...00 to the maximum value 1...11, covering all possible output code values of this 8-bit SAR ADC. Then, among the output codes of these ADCs, there must be all output codes that meet the state detection conditions, and there will be no missing codes.

[0083] The output codes of the 8-bit SAR ADC with the above characteristics are input into the state monitoring module. The state monitoring module will automatically detect the output codes of the ADCs that meet the conditions and perform subsequent operations simultaneously. This module consists of two parts, namely, the state detection logic and an 8-to-1 data selector. According to the aforementioned calibration algorithm, the state detection logic will detect the ADC output codes whose characteristic is that only 1 bit is "1" and the rest of the bits are "0". If the detection logic finds that a certain ADC output code meets all the characteristics required or specified by the algorithm, such as 0...010, then the detection logic will regard this output code as a valid signal and generate different 3-bit selection signals according to the position of the "1" in the output code to control the subsequent 8-to-1 selector. Assuming that the position of the "1" is the nth bit of the output code, then the detection logic will generate a 3-bit selection signal representing n - 1. In this example, if the code value "1" is in the second bit of the ADC output code, then after passing through the detection logic, a 3-bit selection signal sel representing "1", i.e., 001, will be generated to control the subsequent logic circuit. If the detected ADC output code is 010...0, then the detection logic will generate a selection signal sel<2:0> representing "6", i.e., 110. Then, after passing through the 8-to-1 selector, the selection signal sel<2:0> will select a unique valid address channel corresponding to the "1" in different bits of the ADC output code.

[0084] In the information storage module, initially, the address pointer points to the RRAM-based storage cells in the first column with 10 bits. The storage cells in this column correspond to the LSB bits of the 8-bit SAR ADC to be calibrated. When the channel strobe signal from the 8-to-1 multiplexer is received, a certain column of RRAM registers is selected by the address pointer, and then the 10-bit calibration code corresponding to this cycle is stored in the corresponding RRAM column storage cells, that is, the RRAM column pointed to by the address pointer at this time. When the 8x10 RRAM array is filled with 8 columns of 10-bit calibration codes, that is, when the address pointer points to the address of the highest column RRAM register and this column register is not empty, a finish signal is generated to indicate the end of the calibration mode and the completion of calibration. 8 columns of 10-bit calibration codes have been stored in the RRAM storage array, and these calibration codes correspond to the calibration codes when the output mode of the ADC to be calibrated is 0...01 to 10...0 from low to high in sequence.

[0085] After the calibration mode is completed, the SAR ADC to be calibrated is calibrated and starts to enter the working mode. The system block diagram of the data reading and processing part in the working mode of the SAR ADC for this RRAM-based digital front-end calibration scheme is as Figure 2As shown. After the calibrated 8-bit SAR ADC completes a data conversion, it generates an 8-bit digital output code, which is called the pre-calibration output code here. The read control logic in the read control module is responsible for reading the pre-calibration output code of the SAR ADC. First, it detects the number of bits with a value of "1" in the pre-calibration output code, calculates the number of "1"s in the pre-calibration output code through a detection and accumulation logic. If there are n "1"s, then the working cycle of the entire digital front-end calibration module is set to n. Then, in each cycle, it separately detects the position of each "1", and controls the subsequent 8-to-1 MUX selector according to the read control logic to generate different outputs and select different stored calibration codes. For example, if the 8-bit pre-calibration output code generated by the calibrated 8-bit SAR ADC in a certain conversion cycle is 1001_0010, then the read control logic will successively accumulate the number of "1"s in the pre-calibration output code, which is 3 in this example. Then the timing control module sets the working cycle of the digital front-end calibration module to 3. In the first working cycle, first detect the position of the "1" with the lowest bit among the "1"s. In this example, it is the second bit. Therefore, the read control logic will pass the information "2" to the subsequent information storage module through the subsequent 8-to-1 selector, and select the 10-bit calibration code stored in the RRAM-based register in the second column corresponding to the information "2" through the address control module. Similarly, in the second working cycle, detect the position of the "1" with the second lowest bit among the "1"s. In this example, it is the fifth bit. Therefore, the read control logic will pass the information "5" to the subsequent information storage module through the subsequent 8-to-1 selector, and select the 10-bit calibration code stored in the RRAM-based register in the fifth column corresponding to the information "5" through the address control module. Finally, in the third working cycle, detect the position of the "1" with the highest bit among the "1"s. In this example, it is the eighth bit. Therefore, the read control logic will pass the information "8" to the subsequent information storage module through the subsequent 8-to-1 selector, and select the 10-bit calibration code stored in the RRAM-based register in the eighth column corresponding to the information "8" through the address control module.

[0086] After the read control module has completed the detection of the number of "1"s in the pre-calibration output code and the extraction of the information of the position of each "1", the 8×10 RRAM storage array in the information storage module outputs the corresponding 10-bit digital calibration code to the data accumulator in the subsequent data processing module in cycles under the control of the address control module. In each working cycle, 1 column of the 10-bit calibration code corresponding to a certain "1" in the pre-calibration output code is extracted. When the last working cycle specified by the timing control module is reached, an EN valid signal is sent to the data processing module, and this module starts to process all the received data. First, the data accumulator continuously accumulates the n 10-bit calibration codes from the 8×10 RRAM storage array, where n depends on the number of "1"s in the pre-calibration output code of the calibrated SAR ADC detected by the read control module. After the accumulation is completed, since the accumulation result is a 10-bit digital code, while what we need is an 8-bit post-calibration output code, so the 10-bit accumulated digital code is input into the data cutter for data cutting, and only the high eight bits of the data are taken. The final output is the 8-bit calibration output. Thus, the digital front-end calibration in the working mode of the SAR ADC is completed once.

[0087] The execution of the digital front-end calibration method for the successive approximation analog-to-digital converter based on RRAM provided by the embodiment of the present invention depends on the digital front-end calibration system for the successive approximation analog-to-digital converter based on RRAM provided by any embodiment of the present invention, and has corresponding beneficial effects.

[0088] It is easy for those skilled in the art to understand that the above are only the preferred embodiments of the present invention, and are not used to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital front-end calibration system for a successive approximation analog-to-digital converter based on RRAM, characterized in that: include: A step voltage generation module, a state monitoring module, an information storage module and a data processing module; the step voltage generation module is only effective in the calibration mode and is turned off in the working mode; the data processing module is turned off in the calibration mode and is effective in the working mode; The step voltage generation module includes a counter with an N+M bit width and a digital-to-analog converter with an N+M bit resolution, wherein the input end of the counter is connected to an external clock, the output end is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input end of the successive approximation analog-to-digital converter to be calibrated; The counter is used to generate a continuously self-increasing digital code, and the digital-to-analog converter is used to convert the digital code into a continuously increasing analog step voltage Vt, and output it to the successive approximation analog-to-digital converter to be calibrated; wherein M and N are both positive integers; The state monitoring module includes a state detection logic unit and a selector; in the calibration mode, the input end of the state detection logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the output end is connected to the input end of the selector, and the output end of the selector is connected to the information storage module; the state detection logic unit is used to detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the mode of the digital output code; in the working mode, the input end of the state detection logic unit is connected to the output end of the successive approximation analog-to-digital converter to be calibrated, the state detection logic unit is used to detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and the selector is used to respond to different control signals according to the mode of the digital output code; The information storage module includes an address control unit and a storage array unit based on RRAM; in a calibration mode, the storage array unit is connected to the counter and is used to store the N (N+M)-bit digital calibration code generated by the step voltage generation module; the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module, and write the digital calibration code into the storage array; in an operating mode, the storage array unit is connected to the data processing module, and the address control unit is used to select different columns in the storage array according to the control signal output by the state monitoring module, and read the digital calibration code from the storage array; The data processing module includes an N+M-bit data accumulator and an N-bit data chopper, the input end of the data accumulator is connected to the information storage module, and the output end is connected to the input end of the data chopper; the data accumulator is used to accumulate the N+M-bit digital calibration code selected in the information storage module, and the data chopper is used to chop the data and only retain the first N bits as the output of the calibrated successive approximation analog-to-digital converter.

2. The system according to claim 1, characterized in that The counter receives an external clock signal and self-increments the output at each rising edge of the clock to generate a digital code with a bit width of N+M bits; The digital-to-analog converter periodically converts the digital output code of the counter into an analog voltage under the control of the system clock to obtain a step voltage Vt, which is output to a successive approximation analog-to-digital converter; the step voltage Vt includes all situations of the N-bit digital output.

3. The system according to claim 2, characterized in that In the calibration mode, the state monitoring module is used to automatically detect the mode of the digital output code of the successive approximation analog-to-digital converter to be calibrated, and detect whether the mode is that only one bit is "1" and all other bits are "0". If the detection result is true, the position of the "1" in the digital output code is detected, and the selector is used to respond to different control signals according to the detected position and output them to the information storage module; If the test result is false, this calibration cycle is skipped directly; In the working mode, the state monitoring module is used to automatically monitor the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, detect the number n of digital codes containing "1", and set the working cycle of the working mode to n, and detect the number of bits of each "1" in the digital output code. The selector is used to respond to different control signals for each different "1" in the next n working cycles.

4. The system according to claim 2, characterized in that In the calibration mode, the address control unit in the information storage module is used to receive the control signal responded by the state monitoring module, select the columns at different positions in the storage array, and store the digital output code corresponding to the cycle in the corresponding position as the digital calibration code; In working mode, the address control unit in the information storage module is used to receive the control signal responded by the status monitoring module, select columns at different positions in the storage array, and read out the digital calibration code stored in the storage array periodically and transmit it to the data processing module.

5. The system according to claim 4, characterized in that The number of the storage array units is N*(N+M); each of the storage array units includes 7 MOS tubes and 2 RRAMs, wherein 3 MOS tubes are used as signal selection switches, 4 MOS tubes form inverters connected end to end to enhance storage signals, and 2 RRAMs are used as media for storing information; In the calibration mode, the storage array unit is in a write mode, and the digital calibration codes are written one by one; In the working mode, the storage array unit is in the reading mode, and reads the digital calibration codes one by one to the data processing module.

6. The system according to claim 1, characterized in that The data accumulator of the data processing module is used to accumulate the received N+M-bit digital calibration code and determine whether the accumulated result exceeds N+M bits. If so, N+M-bit "1" is output; if not, the data chopper chops the accumulated data and only retains the high N bits of the data as output.

7. The system according to claim 1, characterized in that N=8,M=2.

8. A digital foreground calibration method for a successive approximation analog-to-digital converter based on RRAM, performed based on a digital foreground calibration system for a successive approximation analog-to-digital converter based on RRAM as claimed in any one of claims 1 to 7, characterized in that: For a successive approximation analog-to-digital converter to be calibrated, a calibration mode is first performed, and the subsequent modes are all working modes; When in calibration mode, the method comprises: The step voltage generating module generates a step voltage Vt which is input into the successive approximation analog-to-digital converter to be calibrated, so that it generates different digital output codes; The state monitoring module detects the mode of the digital output code. If it meets the preset output mode, the selector responds to a control signal according to the position of "1" in the digital output code and injects it into the storage array unit to control it to write the corresponding digital calibration code; When in working mode, the method comprises: The state monitoring module detects the mode of the digital output code of the calibrated successive approximation analog-to-digital converter, records the number of "1"s in the digital output code and the position of each "1", and the selector responds to different control signals according to different digital output codes, and controls the storage array unit to read out corresponding digital calibration codes respectively; The data processing module acquires the digital calibration code periodically to perform data accumulation and chopping, and outputs a calibrated digital output code.

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