Digital-to-analog converter, current compensation method for digital-to-analog converter and storage medium

Abstract

The present disclosure relates to the technical field of electronic circuits, including a digital-to-analog conversion device, a current compensation method of the digital-to-analog conversion device and a storage medium. By predicting the first current of the core DAC according to the input code word, and then controlling the first compensation DAC to generate a compensation current with an opposite change trend, the current flowing through the internal resistance is kept constant on the reference bus of the reference voltage source shared by the core DAC and the first compensation DAC, so that the voltage drop generated by the internal resistance is kept constant, thereby avoiding the problem that the first current of the core DAC affects the output linearity with the input change, and eliminating the non-linear error. In addition, by determining the node voltage corresponding to each resistance branch of the first resistance bridge to determine the branch reference current, the control unit can determine the branch reference current based on the same method for different resistance branches, thereby obtaining the first current of the core DAC, and the generality of the compensation current determination method can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and in particular to a digital-to-analog converter, a current compensation method for the digital-to-analog converter, and a storage medium. Background Technology

[0002] A digital-to-analog converter (DAC) is used to convert digital inputs into analog outputs. The DAC is the core component in the digital-to-analog conversion process. The DAC's input terminals are connected to a reference voltage source and an input source, respectively. The input source is used to input digital signals, and the reference voltage source is used to provide a stable reference current to the DAC. The DAC's output terminal is used to output analog voltage or current.

[0003] The stability of the reference voltage source is crucial for ensuring the conversion accuracy and linearity of a DAC. However, in actual digital-to-analog converter circuits, there are trace resistances between the reference voltage source and the DAC core, such as PCB traces, bonding lines, and internal interconnects. The reference current passing through these trace resistances is related to the input digital signal; that is, this reference current is non-linear. In this case, the reference voltage connected to the DAC core has a non-linear voltage error, leading to DAC non-linearity issues. Summary of the Invention

[0004] In view of this, this disclosure proposes a digital-to-analog converter, a current compensation method for the digital-to-analog converter, and a storage medium, which can avoid the problem that the first current of the core DAC affects the output linearity due to changes in the input, eliminate nonlinear errors, and ensure the linearity of the core DAC.

[0005] According to one aspect of this disclosure, a digital-to-analog converter is provided, the converter comprising:

[0006] A core DAC is used to implement digital-to-analog conversion. The core DAC includes an input terminal and an output terminal. The input terminal is connected to an input source and a reference voltage source, respectively. The output terminal outputs an analog signal. The core DAC is an R-2R type DAC, which includes a main resistor circuit and multiple resistor branches connected to the main resistor circuit. The main resistor circuit includes multiple series-connected first resistors, and adjacent resistor branches are bridged by a first resistor. The multiple resistor branches correspond one-to-one with the bits of the core DAC. One end of the main resistor circuit is connected to the output terminal, and the other end is grounded through a grounding resistor. The end of a resistor branch not bridged with a first resistor is grounded or connected to the reference voltage source through a switch control.

[0007] as well as,

[0008] The compensation circuit includes a first compensation DAC and a control unit; wherein the first compensation DAC is connected to the reference voltage source and is used to compensate the reference current of the reference voltage source to a constant current value; one end of the control unit is connected to the input source and the other end is connected to the first compensation DAC, and the control unit is used for:

[0009] Based on the voltage division of the resistor network in each resistor branch, determine the node voltage corresponding to each resistor branch;

[0010] Based on the node voltage corresponding to the resistor branch and the grounding resistance, determine the branch reference current of the resistor branch;

[0011] The first compensation current value is determined based on the difference between the first current and the constant current value; the first current is the sum of the branch reference currents of each resistor branch;

[0012] The first compensation DAC is controlled to output a compensation current according to the first compensation current value, so as to compensate the reference current of the reference voltage source to the constant current value.

[0013] In one possible implementation, determining the node voltage corresponding to each resistor branch based on the voltage division of the resistor network in each resistor branch includes:

[0014] For any bit corresponding to a resistor branch in the first resistor bridge, based on the voltage division of the resistor branch, determine the influence of the bit corresponding to the resistor branch on the node voltage of the corresponding resistor branch, and obtain the weight of the bit on the node voltage.

[0015] Based on the voltage division between the node voltage and other resistor branches, the influence of the bit corresponding to the resistor branch on the other node voltages corresponding to other resistor branches is determined, and the weight of the bit on the other node voltage is obtained.

[0016] For each node voltage, the weight of each bit in the node voltage is multiplied by the product of the corresponding bit to obtain the node voltage.

[0017] In one possible implementation, the output of the core DAC is connected to a shunt device; the shunt device is also connected to the positive terminal of the reference voltage source, but not to the negative terminal, and the current diverted from the positive terminal of the reference voltage source by the shunt device is related to the input codeword of the input source; accordingly,

[0018] The compensation circuit further includes a second compensation DAC, one end of which is connected to the control unit and the other end is connected to the negative terminal of the reference voltage source, so as to compensate the reference current of the negative terminal of the reference voltage source.

[0019] Accordingly, the control unit is also used for:

[0020] Determine the second current of the shunt device;

[0021] The first compensation current value is determined based on the difference between the sum of the first current and the second current and the first constant current value at the positive terminal of the reference voltage source.

[0022] The second compensation current value is determined based on the difference between the sum of the first current and the first compensation current value and the second constant current value of the negative terminal of the reference voltage source.

[0023] The second compensation DAC is controlled to output a compensation current according to the second compensation current value, so as to compensate the negative current of the reference voltage source to a second constant current value.

[0024] In one possible implementation, the shunt device includes an amplifier that scales the analog signal to bipolarity.

[0025] In one possible implementation, the non-inverting input of the amplifier is connected to the output of the core DAC, and the inverting input of the amplifier is connected to the positive terminal of the reference voltage source through a second resistor and to the output of the amplifier through a third resistor; accordingly,

[0026] Determining the second current of the shunt device includes:

[0027] The second current is determined based on the difference between the reference voltage value at the positive terminal of the reference voltage source and the output voltage value at the output terminal of the core DAC, and the resistance value of the second resistor.

[0028] In one possible implementation, the second compensation DAC is a current-mode DAC.

[0029] In one possible implementation, the second compensation DAC includes a first amplifier and a first MOS transistor whose control terminal is connected to the output terminal of the first amplifier. The input terminal of the first MOS transistor is connected to a current source unit, and the output terminal of the first MOS transistor is connected to a resistor unit.

[0030] The non-inverting input terminal of the first amplifier is connected to the positive terminal of the reference voltage source, and the inverting input terminal of the first amplifier is connected to the output terminal of the first MOS transistor.

[0031] The current source unit includes: a first MOS transistor branch and multiple second MOS transistor branches, each second MOS transistor branch being connected to a current branch; the first MOS transistor branch is connected to the input terminal of the first MOS transistor through a fourth resistor; both the first MOS transistor branch and the second MOS transistor branch include a set of second MOS transistors and a set of third MOS transistors, the input terminal of the second MOS transistor is connected to the output terminal of the third MOS transistor, the output terminals of the second MOS transistors in each first MOS transistor branch and the second MOS transistor branch are respectively connected and connected to a compensation power supply; the input terminals of the third MOS transistors in each second MOS transistor branch are respectively connected to the corresponding current branch, the control terminals of the second MOS transistors in each first MOS transistor branch and the second MOS transistor branch are respectively connected to obtain a first voltage control point, the control terminals of the third MOS transistors in each first MOS transistor branch and the second MOS transistor branch are respectively connected to obtain a second voltage control point, and the first voltage control point and the second voltage control point are connected across the two ends of the fourth resistor;

[0032] Each current branch includes a control switch, one end of which is connected to the current source unit, the other end of which is connected to the resistor unit and connected to the negative terminal of the reference voltage source.

[0033] In one possible implementation, the second compensation DAC is a resistive DAC.

[0034] In one possible implementation, the second compensation DAC includes: a second amplifier, and multiple first compensation resistor branches with one end connected to the output terminal of the second amplifier;

[0035] The non-inverting input terminal of the second amplifier is connected to the positive terminal of the reference voltage source, and the inverting input terminal of the second amplifier is connected to the plurality of first compensation resistor branches; the second amplifier is also connected to a compensation power supply.

[0036] The other end of each first compensation resistor branch is connected to the negative terminal of the reference voltage source; each first compensation resistor branch includes a resistor and a control switch connected to the resistor; the resistance value of the resistor in the (m+1)th first compensation resistor branch is twice the resistance value of the resistor in the mth first compensation resistor branch; m is a positive integer.

[0037] In one possible implementation, the first compensation DAC is a resistive DAC.

[0038] In one possible implementation, the first compensation DAC includes multiple second compensation resistor branches, one end of each second compensation resistor branch is connected to the positive terminal of the reference voltage source, and the other end of each second compensation resistor branch is connected to the negative terminal of the reference voltage source.

[0039] Each of the second compensation resistor branches includes a resistor and a control switch connected to the resistor. The resistance value of the resistor in the (n+1)th second compensation resistor branch is twice the resistance value of the resistor in the nth second compensation resistor branch; where n is a positive integer.

[0040] According to another aspect of this disclosure, a digital-to-analog conversion apparatus is provided, the apparatus comprising:

[0041] The core DAC is used to implement digital-to-analog conversion; the core DAC includes an input terminal and an output terminal, the input terminal is connected to an input source and a reference voltage source respectively, and the output terminal is used to output an analog signal;

[0042] A shunt device is connected to the output terminal of the core DAC. The shunt device is also connected to the positive terminal of the reference voltage source, but not to the negative terminal of the reference voltage source. The current shunted from the positive terminal of the reference voltage source by the shunt device is related to the input codeword of the input source.

[0043] as well as,

[0044] The compensation circuit includes a first compensation DAC, a second compensation DAC, and a control unit; wherein one end of the first compensation DAC is connected to the control unit, and the other end is respectively connected to the positive and negative terminals of the reference voltage source, so as to compensate the reference current of the positive and negative terminals of the reference voltage source to a first constant current value; one end of the second compensation DAC is connected to the control unit, and the other end is connected to the negative terminal of the reference voltage source, so as to compensate the reference current of the negative terminal of the reference voltage source to a second constant current value; the control unit is used for:

[0045] Determine the first current of the core DAC;

[0046] Determine the second current of the shunt device;

[0047] The first compensation current value is determined based on the difference between the sum of the first current and the second current and the first constant current value at the positive terminal of the reference voltage source.

[0048] The second compensation current value is determined based on the difference between the sum of the second current and the first compensation current value and the second constant current value of the negative terminal of the reference voltage source.

[0049] The first compensation DAC is controlled to output a compensation current according to the first compensation current value, so as to compensate the positive current of the reference voltage source to the first constant current value;

[0050] The second compensation DAC is controlled to output a compensation current according to the second compensation current value, so as to compensate the negative current of the reference voltage source to the second constant current value.

[0051] In one possible implementation, the type of the device in the first compensation DAC is the same as the type of the device in the core DAC; and / or the type of the device in the second compensation DAC is the same as the type of the device in the core DAC.

[0052] According to another aspect of this disclosure, a current compensation method for a digital-to-analog converter is provided for use in the aforementioned digital-to-analog converter, the method comprising:

[0053] Based on the voltage division of the resistor network in each resistor branch, determine the node voltage corresponding to each resistor branch;

[0054] Based on the node voltage corresponding to the resistor branch and the grounding resistance, determine the branch reference current of the resistor branch;

[0055] The first compensation current value is determined based on the difference between the first current and the constant current value; the first current is the sum of the branch reference currents of each resistor branch;

[0056] The first compensation DAC is controlled to output a compensation current according to the first compensation current value, so as to compensate the reference current of the reference voltage source to a constant current value.

[0057] According to another aspect of this disclosure, a current compensation method for a digital-to-analog converter is provided for use in the aforementioned digital-to-analog converter, the method comprising:

[0058] Determine the first current of the core DAC;

[0059] Determine the second current of the shunt device;

[0060] The first compensation current value is determined based on the difference between the sum of the first current and the second current and the first constant current value at the positive terminal of the reference voltage source.

[0061] The second compensation current value is determined based on the difference between the sum of the second current and the first compensation current value and the second constant current value of the negative terminal of the reference voltage source.

[0062] The first compensation DAC is controlled to output a compensation current according to the first compensation current value, so as to compensate the positive current of the reference voltage source to the first constant current value;

[0063] The second compensation DAC is controlled to output a compensation current according to the second compensation current value, so as to compensate the negative current of the reference voltage source to the second constant current value.

[0064] According to another aspect of this disclosure, a digital-to-analog converter is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0065] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided that stores computer program instructions thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.

[0066] According to another aspect of this disclosure, a computer program product is provided, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0067] By predicting the first current of the core DAC based on the input codeword, and then controlling the first compensation DAC to generate a compensation current with the opposite trend, a current flowing through the internal resistance R is generated on the reference bus of the reference voltage source shared by the core DAC and the first compensation DAC. com The constant current ensures a constant voltage drop generated by the internal resistance, thus avoiding the problem of the first current of the core DAC affecting the output linearity due to changes in the input, eliminating nonlinear errors, and guaranteeing the linearity of the core DAC.

[0068] In addition, by determining the node voltage corresponding to each resistor branch of the first resistor bridge to determine the branch reference current, the control unit can determine the branch reference current based on the same method for different resistor branch design structures, thereby obtaining the first current of the core DAC, which can improve the versatility of the method for determining the compensation current.

[0069] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0070] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0071] Figure 1 A schematic diagram of the circuit structure of a conventional DAC circuit according to an embodiment of the present disclosure is shown;

[0072] Figure 2A schematic diagram of the circuit structure of a digital-to-analog converter according to an embodiment of the present disclosure is shown;

[0073] Figure 3 A schematic diagram of the circuit structure of a core DAC according to an embodiment of the present disclosure is shown;

[0074] Figure 4 A schematic diagram of the circuit structure of a resistive type second compensated DAC according to an embodiment of the present disclosure is shown;

[0075] Figure 5 A schematic diagram showing a compensated reference current according to an embodiment of the present disclosure is provided.

[0076] Figure 6 A schematic diagram showing the change in the core DAC output linearity curve before and after compensation according to an embodiment of the present disclosure;

[0077] Figure 7 A schematic diagram of the circuit structure of a digital-to-analog converter according to another embodiment of the present disclosure is shown;

[0078] Figure 8 A schematic diagram of the circuit structure of a current-mode second compensated DAC according to an embodiment of the present disclosure is shown;

[0079] Figure 9 A schematic diagram of the circuit structure of a resistive type second compensated DAC according to an embodiment of the present disclosure is shown;

[0080] Figure 10 A flowchart illustrating a current compensation method for a digital-to-analog converter according to an embodiment of the present disclosure is shown.

[0081] Figure 11 A flowchart illustrating a current compensation method for a digital-to-analog converter according to another embodiment of the present disclosure is shown.

[0082] Figure 12 This diagram shows a block diagram of a current compensation device for a digital-to-analog converter according to an embodiment of the present application;

[0083] Figure 13 A block diagram of a current compensation device for a digital-to-analog converter according to another embodiment of this application is shown. Detailed Implementation

[0084] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0085] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0086] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0087] Because the reference voltage of a DAC may experience nonlinear errors due to the influence of trace resistance, the traditional approach to reduce the impact of these nonlinear errors on the DAC's linearity is to minimize the impedance between the DAC core and the reference voltage source. However, as the precision of DACs increases, the difficulty of implementing this approach also increases. For example, in high-precision (e.g., 16-bit) DACs, the impedance between the DAC core and the reference voltage source needs to be reduced to a few tenths of an ohm, which significantly increases the difficulty of chip design and manufacturing.

[0088] Additionally, refer to Figure 1 The highest bit shown uses an R2R DAC structure of a thermometer code unit, according to Figure 1 It is known that traditional DAC circuits can also use operational amplifiers as input buffers for the reference voltage, by passing the externally input reference voltage (V) through the input buffer. refp / V refn The reference voltage is connected to the input of the buffer, and after being buffered, it provides a reference for the DAC. At this time, the reference current that varies with the DAC input is provided by the buffer, which is equivalent to significantly increasing the reference input impedance between the DAC and the reference voltage source, so that the DAC output is less affected by the changing reference current and the output linearity is improved.

[0089] Furthermore, in Figure 1 In the provided R2R DAC structure, by decomposing the same reference input terminal of different weighted reference nodes into a pair of matching switches 101, which are respectively connected to the output terminal and the feedback terminal of the buffer, the nonlinear effects generated by the reference current flowing through the buffer output bus and the switch impedance can be canceled in the first order, leaving only the higher-order nonlinear terms. This allows the DAC's integral nonlinearity (INL) / differential nonlinearity (DNL) performance to remain good at higher precision.

[0090] However, the buffer needs to have low noise and offset. If it is applied to a resistive voltage-type DAC, the appropriate gain and bandwidth also need to be selected according to the fast settling characteristics of the DAC, which will increase the overall chip area and power consumption.

[0091] To address the aforementioned technical issues, this application provides a digital-to-analog converter (DAC) and a current compensation method for the DAC. This method analyzes the relationship between the first current of the core DAC and the input codeword, compensates for the first current of the core DAC, and ultimately maintains a constant current on the reference bus of the reference voltage source. At this point, even if the reference input impedance of the core DAC is relatively large, a good INL / DNL can still be maintained, and complex amplifiers and loops are not required. This ensures the linearity of the DAC without increasing the overall chip area and power consumption.

[0092] The analog-to-digital converter provided in this application will be described below. Figure 2 A schematic diagram of the circuit structure of a digital-to-analog converter according to an embodiment of the present disclosure is shown. Figure 2 As shown, the digital-to-analog converter includes: a core DAC 210, a first compensation DAC 220, and a control unit 230.

[0093] The core DAC210 is used to implement digital-to-analog conversion. The input terminals of the core DAC210 are connected to the input source and the reference voltage source, respectively (see...). Figure 2 V refp V represents the positive terminal of the reference voltage source. refn (Indicates the negative terminal of the reference voltage source), the output terminal is used to output the analog signal V. out The input source is used to input digital signals (or codewords), and the reference voltage source is used to provide a reference voltage.

[0094] The first compensation DAC220 is connected to a reference voltage source and is used to compensate the current of the reference voltage source to a constant value. In other words, the output terminal of the first compensation DAC220 is connected to the positive and negative terminals of the reference voltage source respectively, so as to compensate the current at the positive terminal of the reference voltage source to a first constant value and the current at the negative terminal of the reference voltage source to a first constant value.

[0095] One end of the control unit 230 is connected to the input source and the other end is connected to the first compensation DAC 220. It predicts the first current of the core DAC 210 based on the input codeword, and then controls the first compensation DAC 220 to generate a compensation current with the opposite trend. On the reference bus of the reference voltage source shared by the core DAC 210 and the first compensation DAC 220, the compensation current keeps the total reference current constant, thus avoiding the problem that the reference current of the core DAC 210 changes with the input codeword, thereby affecting the output linearity.

[0096] The control unit 230 may be an arithmetic logic unit (ALU) or other components with computing and control capabilities. This embodiment does not limit the implementation of the control unit 230.

[0097] like Figure 2 As shown, the first current of the core DAC210 is I. ref I ref The non-linear change occurs as the input codeword changes. In this embodiment, the first compensation DAC220 generates a value related to I. ref Compensation current I with opposite trend comp This causes the reference current I of the reference bus at the positive and negative terminals of the reference voltage source to be... const for:

[0098] I const =I ref+ I comp , among which, I const It is a constant current value.

[0099] At this time, on the reference bus shared by the core DAC210 and the first compensation DAC220, the current flows through the internal resistance R. com The constant current ensures a constant voltage drop across the internal resistance, preventing the first current of the core DAC210 from affecting the output linearity due to input variations. This eliminates nonlinearity errors and guarantees the linearity of the core DAC210. ​​The internal resistance R... com The internal resistance of the digital-to-analog converter includes the internal resistance of the traces between the core DAC and the first compensation DAC and the reference voltage source. According to the above formula, the control unit 230 determines I. ref Then, it can be based on the preset I const Determine the compensation current I comp .

[0100] Optionally, the core DAC210 can be implemented using capacitors, resistors, or current-driven mechanisms. Depending on the output type, it can be divided into current-type and voltage-type. This embodiment does not limit the type of the core DAC210.

[0101] In one implementation, the core DAC210 is described as an R-2R type DAC. (See reference...) Figure 3 The R-2R type DAC includes a main resistor circuit 310 and multiple resistor branches 320 connected to the main resistor circuit.

[0102] The main resistor 310 includes multiple first resistors connected in series, as referenced. Figure 3 The 2R resistors are in the leftmost column. One end of the 310 resistor in the main circuit is connected to the output terminal V. out The other end is grounded through a 330Ω grounding resistor.

[0103] Two adjacent resistor branches 320 are bridged by a first resistor, wherein the resistance value in each resistor branch 320 is in a 2:1 ratio to the resistance value in the main resistor branch 310. For example: Figure 3 If the resistance of the resistor in the main resistor circuit 310 is 2R, then the resistance of the resistor in the branch resistor circuit 320 is 4R.

[0104] Each resistor branch 320 includes one resistor or multiple resistors connected in parallel. When multiple resistors are connected in parallel, the resistance of each parallel resistor is equal to the resistance of the resistor branch 320. For example: Figure 3 The resistor branch 320 in the area of ​​the dashed box includes two resistors connected in parallel with resistance values ​​of 12R and 6R respectively. The total resistance of these two resistors is 4R, which is twice the resistance value of the resistor in the main circuit.

[0105] Multiple resistor branches 320 correspond one-to-one with the bits of the core DAC210. ​​For example, if the core DAC210 has 16 bits, then there are 16 resistor branches 320, each corresponding to one of the 16 bits, so that the corresponding analog signal (such as voltage value) can be output according to the bit value of each bit.

[0106] The end of each resistor branch 320 that is not bridged with the first resistor is grounded or connected to a reference voltage source through a switch control.

[0107] In one example, the control unit 230 is configured to: determine the node voltage corresponding to each resistor branch based on the voltage division of the resistor network in each resistor branch; determine the branch reference current of the resistor branch based on the node voltage and grounding resistance of the resistor branch; determine a first compensation current value based on the difference between a first current and a constant current value; and control the first compensation DAC 220 to output a compensation current according to the first compensation current value, so as to compensate the reference current of the reference voltage source to a constant current value. Here, the first current is the sum of the branch reference currents of each resistor branch.

[0108] In practical implementation, resistor branches may be implemented in different ways to achieve redundancy, such as consisting of 12R and 6R resistors, or a single 4R resistor. However, adjacent resistor branches are all bridged by the first resistor. Based on this, in this embodiment, the branch reference current is determined by determining the node voltage corresponding to each resistor branch bridged by the first resistor. This allows the control unit 230 to determine the branch reference current using the same method for different resistor branch design structures, thereby obtaining the first current of the core DAC 210 and improving the versatility of the compensation current determination method.

[0109] Schematic, based on the voltage division of the resistor network in each resistor branch, the node voltage corresponding to each resistor branch is determined, including: for any bit corresponding to a resistor branch connected by a first resistor bridge, based on the voltage division of the resistor branch, the influence of the bit corresponding to the resistor branch on the node voltage corresponding to that resistor branch is determined, and the weight of the bit on the node voltage is obtained; based on the voltage division between the node voltage and other resistor branches, the influence of the bit corresponding to the resistor branch on the other node voltages corresponding to other resistor branches is determined, and the weight of the bit on the other node voltages is obtained; for each node voltage, the weight of each bit on the node voltage is superimposed on the product of the corresponding bit, respectively, to obtain the node voltage.

[0110] Specifically, refer to Figure 1 The binary-coded R-2R resistor network shown is for V i The node voltage at that point, the node voltage V i The equivalent resistance below is 2R, and the node voltage is V. i The equivalent resistance value in the dashed box above is R. i R i The value can be determined based on the specific network structure of the R-2R resistor network; at this time, the node voltage V i The connected resistor branch 2R is connected in series with the equivalent resistance 2R below the node voltage and R. i Parallel resistors; the bit B can be obtained according to the voltage divider principle. i For node voltage V i The impact.

[0111] Meanwhile, B i It will also affect the voltages of other nodes, specifically the node voltage V. i-1 For example, similarly, the node voltage V i The resistor below has an equivalent value of 2R, and the node voltage V i-1 The equivalent resistance value in the dashed box above is R. i-1 R i-1 The value can be determined based on the specific network structure of the R-2R resistor network; at this time, the node voltage V i-1 For node voltage V i In series resistors R1 and R2 i-1 After voltage division, at R i-1 The voltage on it gives B i For node voltage V i-1 The influence, and so on, leads to B. i The impact on the voltage of each node.

[0112] In this embodiment, any bit B j For a certain node voltage Vi The influence is represented by the weight w(i,j), and correspondingly, for any node voltage V i , composed of each bit B j The node voltage V i The node voltages are obtained by summing the weights.

[0113] Optionally, the most significant bit (Most Significant Bit) of the R-2R type DAC can also be implemented using thermocouple coding to reduce the area of ​​the core DAC210. ​​The thermocouple coding section includes multiple directly parallel resistor branches; that is, the resistor branches are not bridged by the first resistor. According to... Figure 3 It can be seen that the resistor branches include resistor branches composed of a single 2R resistor and resistor branches composed of 3R and 6R resistors connected in parallel. The resistance value of the resistor branch composed of 3R and 6R resistors connected in parallel is also 2R, that is, the resistance values ​​of each resistor branch are the same.

[0114] In the thermometer code, each resistor branch has the same weight.

[0115] Below, we will focus on the core DAC. Figure 3 Taking the R-2R type DAC shown as an example, the first 4 bits of the core DAC use a thermometer code design, and it also includes a 16-bit R-2R DAC with redundant bits. In this case, the reference current source of the core DAC is divided into the thermometer code part composed of a single 2R branch near the output, i.e., the MSB, and the network part bridged by 2Rs, i.e., the Least Significant Bit. Based on the above principle, the algebraic expression of the reference current of the DAC as a function of the input codeword can be derived according to the different actual control words as follows:

[0116]

[0117] Among them, I LSB (i) represents the reference current of the resistor branch corresponding to the i-th bit, V(i) represents the node voltage of the resistor branch corresponding to the i-th bit, and B(i) represents the bit value of the i-th bit.

[0118] Summing the reference currents for each resistor branch yields:

[0119]

[0120] against Figure 3 The design of the medium redundancy circuit shows that:

[0121]

[0122] in,

[0123] B(2)=B(2_1) / 3+2×B(2_2) / 3;

[0124] B(4)=B(4_1) / 3+2×B(4_2) / 3;

[0125]

[0126] Where B(j) represents the bit value of the j-th bit in the network section bridged by 2R. B(i_1) represents the input codeword of the 12R resistor in the 1-th redundant design bit of the network section bridged by 2R, and B(i_2) represents the input codeword of the 6R resistor in the 1-th redundant design bit of the network section bridged by 2R. T(i) represents the input codeword of the 1-th bit in the thermometer code; I MSB This represents the reference current for the most significant bit (MSB).

[0127] After obtaining I LSB and I MSB Then, the sum of the two can be used to obtain the first current I of the core DAC. ref Then, the preset constant current value I is calculated. const with I ref The difference between these values ​​yields the first compensation current value required for the output of the first compensation DAC. The input control word of the first compensation DAC is then controlled according to this first compensation current value to obtain a reference current that is relatively stable compared to the input codeword.

[0128] Optionally, the types of devices in the first compensation DAC are the same as those in the core DAC. This allows for better matching of the current of the first compensation DAC with that of the core DAC. For example, if the core DAC is a resistive DAC, then the first compensation DAC is also a resistive DAC; if the core DAC is a current-controlled DAC, then the first compensation DAC is also a current-controlled DAC.

[0129] by Figure 3 Taking the core DAC shown as an example, to adapt to the circuit structure of the core DAC, the first compensation DAC is also a resistive DAC. Optionally, the resistive type of the first compensation DAC can be a binary weighted resistor DAC or an R-2R type DAC. This embodiment does not limit the type of the first compensation DAC.

[0130] In one example, the first compensation DAC is implemented as a simple binary weighted resistor DAC. Since high-precision (16-bit) applications do not require very precise current compensation to make the core DAC insensitive to the internal impedance of the reference voltage source, this relatively area-intensive first compensation DAC design can be adopted. Because this first compensation DAC design is simple, it is easier to match the original core DAC on the layout. Therefore, the design difficulty of the first compensation DAC can be reduced while ensuring compensation accuracy.

[0131] refer to Figure 4 This embodiment uses a 5-bit first compensation DAC to compensate for the reference current as an example. The first compensation DAC includes multiple second compensation resistor branches. One end of each second compensation resistor branch is connected to the positive terminal of the reference voltage source, and the other end of each second compensation resistor branch is connected to the negative terminal of the reference voltage source.

[0132] Each of the second compensation resistor branches includes a resistor (R). comp ~2 n R comp ) and the control switches (Q1~Q) connected to the resistor. n The resistance value of the resistor in the (n+1)th second compensation resistor branch is twice the resistance value of the resistor in the nth second compensation resistor branch; n is a positive integer.

[0133] Combination Figure 3 The core DAC shown Figure 4 The first compensated DAC shown, with 16-bit precision and an external reference total impedance of 0.5 ohms, has the following compensated reference current: Figure 5 As shown, the linearity of the core DAC output before and after compensation is as follows: Figure 6 As shown. According to Figure 6 It can be seen that, for the original core DAC, before the addition of current compensation technology, its DNL / INL performance was significantly affected by the characteristics of the reference current changing with the input, resulting in fluctuations (see details). Figure 6 (Left half). After compensation, by Figure 6 As can be seen from the right half, DNL / INL tends to stabilize, from Figure 5 As can be seen from the total current curve ITOT, the current flowing through the reference bus is approximately constant at this time. Therefore, the output nonlinearity caused by the voltage drop of the reference current on the non-ideal impedance outside the core DAC is greatly reduced. The voltage drop of the compensated constant current value on the reference source impedance will only introduce gain error that is easy to calibrate.

[0134] Optionally, in some embodiments, the output of the core DAC is also connected to a shunt device. This shunt device is connected to the positive terminal of the reference voltage source but not to the negative terminal, and the current diverted from the positive terminal of the reference voltage source by the shunt device is related to the input codeword of the input source. In this case, a portion of the current at the positive terminal of the reference voltage source is drawn by the shunt device, but this portion of the current does not flow back to the negative terminal of the reference voltage source. Therefore, additional compensation is needed at the negative terminal of the reference voltage source for the current drawn by the shunt device. Based on this, the reference... Figure 7 The compensation circuit also includes a second compensation DAC710, one end of which is connected to the control unit 230 and the other end is connected to the negative terminal of the reference voltage source to compensate for the reference current of the negative terminal of the reference voltage source.

[0135] Accordingly, the control unit 230 is also configured to: determine the second current of the shunt device 720; determine the first compensation current value based on the difference between the sum of the first current and the second current and the first constant current value of the positive terminal of the reference voltage source; determine the second compensation current value based on the difference between the sum of the first current and the first compensation current value and the second constant current value of the negative terminal of the reference voltage source; and control the second compensation DAC 710 to output the compensation current according to the second compensation current value, so as to compensate the negative current of the reference voltage source to the second constant current value.

[0136] The calculation method for the first current is described in the above embodiment, and will not be repeated here.

[0137] When high accuracy is not required, ignoring the additional fixed voltage drop from the positive terminal of the reference voltage source, the second current I that needs to be compensated is... fb It can be represented as:

[0138] I fb =(V refp -I const1 R com -V DAC) / R1≈(V refp -V DAC ) / R1;

[0139] Among them, V refp I represents the voltage value at the positive terminal of the reference voltage source. const1 R represents the preset first constant current value. com R1 represents the resistance between the core DAC210 and the reference voltage source (i.e., the internal resistance or trace resistance mentioned above), and R2 represents the resistance between the shunt device 720 and R3. com The resistance between, V DAC This indicates the voltage value output by the core DAC210.

[0140] according to Figure 7It can be seen that the first constant current value at the positive terminal of the reference voltage source is expressed by the following formula:

[0141] I const1 =I ref +I fb +I comp1 ;

[0142] The second constant current value at the negative terminal of the reference voltage source is expressed by the following formula:

[0143] I const2 =I ref +I comp1 +I comp2 .

[0144] Among them, I ref The first current of the core DAC210 determined by the control unit 230; I comp1 I is the first compensation current value of the first compensation DAC220. comp2 This is the second compensation current value of the second compensation DAC710.

[0145] Optionally, the first constant current value may be the same as or different from the second constant current value.

[0146] Schematic, the shunt device 720 includes an amplifier that scales the analog signal (such as a voltage value) output from the core DAC 210 to bipolar form. Accordingly, as Figure 7 As shown, the non-inverting input of the amplifier is connected to the output of the core DAC210, and the inverting input is connected to the positive terminal of the reference voltage source through a second resistor R1 and to the output of the amplifier through a third resistor R2. Correspondingly, the second current of the shunt device 720 is determined, including: the reference voltage value V based on the positive terminal of the reference voltage source. refp The output voltage value V at the output terminal of the core DAC210 DAC The difference between the two currents, and the resistance of the second resistor, determine the second current. That is,

[0147] I fb =(V refp -V DAC ) / R1.

[0148] In one example, since the compensation accuracy requirement for the second current of the shunt device 720 is not high, a simple current-mode DAC (i.e., IDAC) can be used to implement the second compensation DAC 710 to compensate for this second current.

[0149] Indicatively, for reference Figure 8The second compensation DAC shown includes a first amplifier 810 and a first MOSFET 820 whose control terminal is connected to the output terminal of the first amplifier. The input terminal of the first MOSFET is connected to a current source unit 830, and the output terminal of the first MOSFET 820 is connected to the first terminal of a resistor unit 850. The non-inverting input terminal of the first amplifier 810 is connected to the positive terminal of a reference voltage source, and the inverting input terminal of the first amplifier 810 is connected to the output terminal of the first MOSFET 820.

[0150] The current source unit 830 includes: a first MOS transistor branch and multiple second MOS transistor branches, each second MOS transistor branch being connected to a current branch 840; the first MOS transistor branch is connected to the input terminal of the first MOS transistor through a fourth resistor R4; each first MOS transistor branch and second MOS transistor branch includes a set of second MOS transistors M2 and third MOS transistors M3, the input terminal of the second MOS transistor M2 is connected to the output terminal of the third MOS transistor M3, the output terminals of the second MOS transistors M2 in each first MOS transistor branch and second MOS transistor branch are respectively connected and connected to the compensation power supply AVDD; the input terminal of the third MOS transistor M3 in each second MOS transistor branch is respectively connected to the corresponding current branch, the control terminals of the second MOS transistors M2 in each first MOS transistor branch and second MOS transistor branch are respectively connected to obtain a first voltage control point VP1, the control terminals of the third MOS transistors M3 in each first MOS transistor branch and second MOS transistor branch are respectively connected to obtain a second voltage control point VP2, and the first voltage control point VP1 and the second voltage control point VP2 are connected across the four resistors R4.

[0151] Each current branch includes a control switch (B). C1 ~B Cn One end of the control switch is connected to the current source unit, and the other end is connected to the second end of the resistor unit 850, and connected to the negative terminal of the reference voltage source.

[0152] In this example, the first MOSFET is an N-channel MOSFET, and the second and third MOSFETs are P-channel MOSFETs. The control terminal is the gate of the MOSFET, the output terminal is the source of the MOSFET, and the input terminal is the drain of the MOSFET.

[0153] The resistor unit in the second compensation DAC mentioned above is a unit resistor matched to the core DAC, introducing V refp A unit compensation reference current is generated, and a second compensation current flows from the compensation power supply (or analog power supply AVDD) to the negative terminal V of the reference voltage source. refn By using a matching current mirror, acceptable accuracy can be achieved to compensate for the current flowing through V. refn The current ultimately causes a constant reference current to flow through the reference bus of the reference voltage source.

[0154] In another example, the components in the second compensation DAC are of the same type as those in the core DAC. This allows for a better match with the circuit structure of the core DAC. For instance, if the core DAC is a resistive DAC, then the second compensation DAC will also be a resistive DAC.

[0155] Indicatively, for reference Figure 9 The second compensation DAC shown includes a second amplifier 910 and multiple first compensation resistor branches 920, one end of which is connected to the output terminal of the second amplifier 910. The non-inverting input terminal of the second amplifier is connected to the positive terminal of a reference voltage source, and the inverting input terminal of the second amplifier is connected to the multiple first compensation resistor branches 920. The second amplifier 910 is also connected to a compensation power supply AVDD. The other end of each first compensation resistor branch is connected to the negative terminal of the reference voltage source. Each first compensation resistor branch includes a resistor (R). comp ~2 n R comp ) and the control switches (Q1~Q) connected to the resistor. n The resistance value of the first compensation resistor branch in the (m+1)th branch is twice the resistance value of the first compensation resistor branch in the mth branch; m is a positive integer.

[0156] At this point, the same V is introduced into the resistor units of all the second compensation DACs through the unity-gain feedback loop. refp -V refn The voltage drop, while the amplifier is powered by a compensated power supply AVDD, to achieve separate voltage drop. refn Current compensation. This second compensation DAC is mainly composed of resistors. In order to achieve resistance matching with the core DAC, the second compensation DAC occupies a lot of area. Therefore, this implementation method can be applied to digital-to-analog converters with a large area.

[0157] In summary, in this embodiment, by further compensating the second current diverted by the shunt device through the second compensation DAC, it can be ensured that the core DAC can still be unaffected by the external resistance when applied in a bipolar scenario, thereby ensuring the linearity of the core DAC.

[0158] In addition, the first and second compensation DACs have low circuit complexity and are suitable for high-precision DAC designs in most industrial control and testing fields where power consumption is not sensitive, thus having strong versatility.

[0159] In addition, by compensating the current on the reference bus through the first compensation DAC and the second compensation DAC, compared with the method of directly correcting the nonlinear points on the output curve, the technical solution provided in this embodiment consumes relatively fewer digital resources and is more adaptable to application environments with different internal resistances.

[0160] Optionally, this application also provides a current compensation method for a digital-to-analog converter.

[0161] Figure 10 A flowchart illustrating a current compensation method for a digital-to-analog converter according to an embodiment of the present disclosure is shown. This method is used in the digital-to-analog converter, specifically in the control unit of the digital-to-analog converter in the various embodiments described above. The core DAC in this digital-to-analog converter is an R-2R type DAC. For example... Figure 10 As shown, the method includes:

[0162] Step 1001: Based on the voltage division of the resistor network in each resistor branch, determine the node voltage corresponding to each resistor branch.

[0163] Step 1002: Determine the branch reference current of the resistor branch based on the node voltage and grounding resistance corresponding to the resistor branch.

[0164] Step 1003: Determine the first compensation current value based on the difference between the first current and the constant current value; the first current is the sum of the branch reference currents of each resistor branch;

[0165] Step 1004: Control the first compensation DAC to output a compensation current according to the first compensation current value, so as to compensate the reference current of the reference voltage source to a constant current value.

[0166] The relevant descriptions of this embodiment are the same as those in the above-described device embodiments, and will not be repeated here.

[0167] In this embodiment, the first current of the core DAC is predicted based on the input codeword, and then the first compensation DAC is controlled to generate a compensation current with the opposite trend. This compensation current flows through the internal resistance R on the reference bus of the reference voltage source shared by the core DAC and the first compensation DAC. com The constant current ensures a constant voltage drop generated by the internal resistance, thus avoiding the problem of the first current of the core DAC affecting the output linearity due to changes in the input, eliminating nonlinear errors, and guaranteeing the linearity of the core DAC.

[0168] In addition, by determining the node voltage corresponding to each resistor branch of the first resistor bridge to determine the branch reference current, the control unit can determine the branch reference current based on the same method for different resistor branch design structures, thereby obtaining the first current of the core DAC, which can improve the versatility of the method for determining the compensation current.

[0169] Figure 11A flowchart illustrating a current compensation method for a digital-to-analog converter according to another embodiment of the present disclosure is shown. This method is used in the digital-to-analog converter, specifically in the control unit of the digital-to-analog converter in the various embodiments described above. The output terminal of the core DAC in this digital-to-analog converter is connected to a shunt device, and the compensation circuit includes a first compensation DAC and a second compensation DAC. In this case, the core DAC can be capacitive, resistive, or current-type; this embodiment does not limit the type of the core DAC. Figure 11 As shown, the method includes:

[0170] Step 1101: Determine the first current of the core DAC;

[0171] Step 1102: Determine the second current of the shunt device;

[0172] Optionally, step 1102 can be executed before step 1101, or after step 1101, or synchronously with step 1101. This embodiment does not limit the execution order between steps 1101 and 1102.

[0173] Step 1103: Determine the first compensation current value based on the difference between the sum of the first current and the second current and the first constant current value at the positive terminal of the reference voltage source.

[0174] Step 1104: Determine the second compensation current value based on the difference between the sum of the second current and the first compensation current value and the second constant current value of the negative terminal of the reference voltage source.

[0175] Step 1105: Control the first compensation DAC to output a compensation current according to the first compensation current value, so as to compensate the positive current of the reference voltage source to the first constant current value.

[0176] Step 1105 can be executed after step 1103. This embodiment does not limit the timing of the execution of step 1105.

[0177] Step 1106: Control the second compensation DAC to output a compensation current according to the second compensation current value, so as to compensate the negative current of the reference voltage source to the second constant current value.

[0178] Optionally, step 1106 can be executed before step 1105, after step 1105, or synchronously with step 1105. This embodiment does not limit the order between steps 1105 and 1106.

[0179] The relevant descriptions of this embodiment are the same as those in the above-described device embodiments, and will not be repeated here.

[0180] In this embodiment, the second current diverted by the shunt device is further compensated by the second compensation DAC, which can ensure that the core DAC is not affected by the external resistance when applied in a bipolar scenario, thereby ensuring the linearity of the core DAC.

[0181] Figure 12 This is a block diagram of a current compensation device for a digital-to-analog converter according to an embodiment of this application. The device is used in the control unit of the digital-to-analog converter, and the core DAC in the digital-to-analog converter is an R-2R type DAC. The device includes at least the following modules: voltage determination module 1210, current determination module 1220, compensation determination module 1230, and compensation control module 1240.

[0182] The voltage determination module 1210 is used to determine the node voltage corresponding to each resistor branch based on the voltage division of the resistor network in each resistor branch.

[0183] The current determination module 1220 is used to determine the branch reference current of the resistor branch based on the node voltage corresponding to the resistor branch and the grounding resistance.

[0184] The compensation determination module 1230 is used to determine a first compensation current value based on the difference between the first current and the constant current value; the first current is the sum of the branch reference currents of each resistor branch;

[0185] The compensation control module 1240 is used to control the first compensation DAC to output a compensation current according to the first compensation current value, so as to compensate the reference current of the reference voltage source to a constant current value.

[0186] For details, please refer to the above embodiments.

[0187] Figure 13 This is a block diagram of a current compensation device for a digital-to-analog converter according to another embodiment of this application. The device is used in the control unit of the digital-to-analog converter, where the output of the core DAC is connected to a shunt device. The compensation circuit includes a first compensation DAC and a second compensation DAC. The device includes at least the following modules:

[0188] First current determination module 1310 is used to determine the first current of the core DAC;

[0189] The second current determination module 1320 is used to determine the second current of the shunt device;

[0190] The first compensation determination module 1330 is used to determine the first compensation current value based on the difference between the sum of the first current and the second current and the first constant current value of the positive terminal of the reference voltage source.

[0191] The second compensation determination module 1340 is used to determine the second compensation current value based on the difference between the sum of the second current and the first compensation current value and the second constant current value of the negative terminal of the reference voltage source.

[0192] The first compensation control module 1350 is used to control the first compensation DAC to output a compensation current according to the first compensation current value, so as to compensate the positive current of the reference voltage source to the first constant current value.

[0193] The second compensation control module 1360 is used to control the second compensation DAC to output a compensation current according to the second compensation current value, so as to compensate the negative current of the reference voltage source to the second constant current value.

[0194] For details, please refer to the above embodiments.

[0195] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0196] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium can be volatile or non-volatile.

[0197] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0198] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0199] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A digital-to-analog conversion device, characterized by, The device comprises: a core DAC for realizing a digital-to-analog conversion function; the core DAC comprises an input end and an output end, the input end is connected with an input source and a reference voltage source respectively, and the output end is used for outputting an analog signal; the core DAC is an R-2R type DAC, the R-2R type DAC comprises a resistance main path and a plurality of resistance branches connected with the resistance main path; the resistance main path comprises a plurality of first resistances connected in series, and two adjacent resistance branches are bridged by a first resistance; the plurality of resistance branches correspond to bit positions of the core DAC one by one; one end of the resistance main path is connected with the output end, and the other end is grounded through a grounding resistance; one end of the resistance branch not bridged by the first resistance is connected with the reference voltage source through a switch control to realize grounding or access to the reference voltage source; the output end of the core DAC is connected with a shunt device; the shunt device is also connected with a positive electrode of the reference voltage source but not connected with a negative electrode of the reference voltage source, and a current drawn by the shunt device from the positive electrode of the reference voltage source is related to an input code word of the input source; the shunt device comprises an amplifier for scaling the analog signal to bipolarity; a non-inverting input end of the amplifier is connected with the output end of the core DAC, an inverting input end of the amplifier is connected to the positive electrode of the reference voltage source through a second resistance and connected to an output end of the amplifier through a third resistance; and, a compensation circuit comprising a first compensation DAC, a second compensation DAC and a control unit; wherein the first compensation DAC is connected with the reference voltage source and is used for compensating a reference current of the reference voltage source to a constant current value; one end of the control unit is connected with the input source, and the other end is connected with the first compensation DAC; one end of the second compensation DAC is connected with the control unit, and the other end is connected with the negative electrode of the reference voltage source to compensate a reference current of the negative electrode of the reference voltage source; the control unit is used for: determining a node voltage corresponding to each resistance branch based on resistance voltage division of a resistance network in each resistance branch; determining a branch reference current of the resistance branch based on the node voltage corresponding to the resistance branch and the grounding resistance; determining a second current of the shunt device based on a difference between a reference voltage value of a positive pole of the reference voltage source and an output voltage value of an output end of the core DAC and a resistance value of the second resistor, the second current can be represented as I fb = (V refp -V DAC ) / R1, wherein I fb represents the second current, V refp represents the reference voltage value of the positive pole of the reference voltage source, V DAC represents the output voltage value of the output end of the core DAC, and R1 represents the resistance value of the second resistor. determining a first compensation current value based on a difference between a sum of a first current and a second current and a first constant current value of the positive electrode of the reference voltage source; the first current is a sum of the branch reference currents of the resistance branches; determining a second compensation current value based on a difference between a sum of the first current and the first compensation current value and a second constant current value of the negative electrode of the reference voltage source; to additionally compensate a current drawn by the shunt device at the negative electrode of the reference voltage source; controlling the first compensation DAC to output a compensation current according to the first compensation current value, so as to compensate the positive electrode current of the reference voltage source to the first constant current value; controlling the second compensation DAC to output a compensation current according to the second compensation current value, so as to compensate the negative electrode current of the reference voltage source to the second constant current value.

2. The apparatus of claim 1, wherein, The node voltage corresponding to each resistance branch is determined based on resistance voltage division of the resistance network in each resistance branch, and includes: For a bit corresponding to any one of the resistance branches of the first resistance bridge, the influence of the bit on the node voltage corresponding to the resistance branch is determined based on the resistance voltage division of the resistance branch, to obtain a weight of the bit on the node voltage; The influence of the bit on other node voltages corresponding to other resistance branches is determined based on the resistance voltage division between the node voltage and the other resistance branches, to obtain a weight of the bit on the other node voltages; For each node voltage, the weight of each bit on the node voltage is multiplied by the corresponding bit to obtain the node voltage.

3. The apparatus of claim 1, wherein, The second compensation DAC is a current type DAC.

4. The apparatus of claim 3, wherein, The second compensation DAC includes a first amplifier and a first MOS tube with a control end connected to an output end of the first amplifier, an input end of the first MOS tube connected to a current source unit, and an output end of the first MOS tube connected to a resistance unit. A positive input end of the first amplifier is connected to a positive electrode of the reference voltage source, and a negative input end of the first amplifier is connected to an output end of the first MOS tube. The current source unit includes a first MOS tube branch and a plurality of second MOS tube branches, each second MOS tube branch connected to a current branch; the first MOS tube branch is connected to the input end of the first MOS tube through a fourth resistance; the first MOS tube branch and the second MOS tube branch each include a group of second MOS tubes and third MOS tubes, the input end of the second MOS tube connected to the output end of the third MOS tube, the output ends of the second MOS tubes in each first MOS tube branch and second MOS tube branch connected to each other and to a compensation power supply; the input end of the third MOS tube in each second MOS tube branch connected to the corresponding current branch, the control ends of the second MOS tubes in each first MOS tube branch and second MOS tube branch connected to each other to obtain a first voltage control point, and the control ends of the third MOS tubes in each first MOS tube branch and second MOS tube branch connected to each other to obtain a second voltage control point, the first voltage control point and the second voltage control point connected across the fourth resistance. Each current branch includes a control switch, one end of the control switch connected to the current source unit and the other end connected to the resistance unit and connected to a negative electrode of the reference voltage source.

5. The apparatus of claim 1, wherein, The second compensation DAC is a resistance type DAC.

6. The apparatus of claim 5, wherein, The second compensation DAC includes a second amplifier and a plurality of first compensation resistance branches with one end connected to an output end of the second amplifier. A positive input end of the second amplifier is connected to a positive electrode of the reference voltage source, and a negative input end of the second amplifier is connected to the plurality of first compensation resistance branches; the second amplifier is also connected to a compensation power supply. Another end of each first compensation resistance branch is connected to a negative pole of the reference voltage source; each first compensation resistance branch comprises a resistance and a control switch connected to the resistance, and a resistance in an (m+1)th first compensation resistance branch is twice a resistance in an mth first compensation resistance branch; m is a positive integer.

7. The apparatus of any one of claims 1 to 6, wherein, The first compensation DAC is a resistance type DAC.

8. The apparatus of claim 7, wherein, The first compensation DAC comprises a plurality of second compensation resistance branches, one end of each second compensation resistance branch is connected to a positive pole of the reference voltage source, and another end of each second compensation resistance branch is connected to a negative pole of the reference voltage source. Each second compensation resistance branch comprises a resistance and a control switch connected to the resistance, and a resistance in an (n+1)th second compensation resistance branch is twice a resistance in an nth second compensation resistance branch; n is a positive integer.

9. A digital-to-analog conversion device, characterized by The device comprises: a core DAC for realizing a digital-to-analog conversion function; the core DAC comprises an input end and an output end, the input end is connected to an input source and a reference voltage source respectively, and the output end is used for outputting an analog signal; a shunt device connected to the output end of the core DAC, the shunt device is also connected to a positive pole of the reference voltage source but not connected to a negative pole of the reference voltage source, and a current drawn by the shunt device from the positive pole of the reference voltage source is related to an input code word of the input source; the shunt device comprises an amplifier for scaling the analog signal to be bipolar; a non-inverting input end of the amplifier is connected to the output end of the core DAC, an inverting input end of the amplifier is connected to the positive pole of the reference voltage source through a second resistance and connected to an output end of the amplifier through a third resistance; and a compensation circuit comprising a first compensation DAC, a second compensation DAC and a control unit; one end of the first compensation DAC is connected to the control unit, and another end thereof is connected to the positive pole and the negative pole of the reference voltage source respectively, so as to compensate reference currents of the positive pole and the negative pole of the reference voltage source to be a first constant current value; one end of the second compensation DAC is connected to the control unit, and another end thereof is connected to the negative pole of the reference voltage source, so as to compensate a reference current of the negative pole of the reference voltage source to be a second constant current value; the control unit is used for: determining a first current of the core DAC; determining a second current of the shunt device based on a difference between a reference voltage value of a positive pole of the reference voltage source and an output voltage value of an output end of the core DAC and a resistance value of the second resistor, the second current can be represented as I fb = (V refp -V DAC ) / R1, wherein I fb represents the second current, V refp represents the reference voltage value of the positive pole of the reference voltage source, V DAC represents the output voltage value of the output end of the core DAC, and R1 represents the resistance value of the second resistor. determining a first compensation current value based on a difference between a sum of the first current and the second current and the first constant current value of the positive pole of the reference voltage source; determining a second compensation current value based on a difference between a sum of the second current and the first compensation current value and the second constant current value of the negative pole of the reference voltage source, so as to additionally compensate a current drawn by the shunt device from the negative pole of the reference voltage source; controlling the first compensation DAC to output a compensation current according to the first compensation current value, so as to compensate the positive pole current of the reference voltage source to be the first constant current value. controlling the second compensation DAC to output compensation current according to the second compensation current value, so as to compensate the negative electrode current of the reference voltage source to the second constant current value.

10. The apparatus of claim 9, wherein, the type of device in the first compensation DAC is the same as the type of device in the core DAC; and / or the type of device in the second compensation DAC is the same as the type of device in the core DAC.

11. A current compensation method for a digital-to-analog conversion device, characterized by, The method comprises: determining the node voltage corresponding to each resistance branch based on the resistance voltage division of the resistance network in each resistance branch; determining the branch reference current of the resistance branch based on the node voltage corresponding to the resistance branch and the grounding resistance; determining a second current of the shunt device based on a difference between a reference voltage value of a positive pole of the reference voltage source and an output voltage value of an output end of the core DAC and a resistance value of the second resistor, the second current can be represented as I fb = (V refp -V DAC ) / R1, wherein I fb represents the second current, V refp represents the reference voltage value of the positive pole of the reference voltage source, V DAC represents the output voltage value of the output end of the core DAC, and R1 represents the resistance value of the second resistor. determining the first compensation current value based on the difference between the sum of the first current and the second current and the first constant current value of the positive electrode of the reference voltage source; the first current is the sum of the branch reference currents of the resistance branches; determining the second compensation current value based on the difference between the sum of the first current and the first compensation current value and the second constant current value of the negative electrode of the reference voltage source, so as to additionally compensate the current drawn by the shunt device at the negative electrode of the reference voltage source; controlling the first compensation DAC to output compensation current according to the first compensation current value, so as to compensate the positive electrode current of the reference voltage source to the first constant current value; controlling the second compensation DAC to output compensation current according to the second compensation current value, so as to compensate the negative electrode current of the reference voltage source to the second constant current value.

12. A current compensation method for a digital-to-analog conversion device, characterized by, The method comprises: determining the first current of the core DAC; determining a second current of the shunt device based on a difference between a reference voltage value of a positive pole of the reference voltage source and an output voltage value of an output end of the core DAC and a resistance value of the second resistor, the second current can be represented as I fb = (V refp -V DAC ) / R1, wherein I fb represents the second current, V refp represents the reference voltage value of the positive pole of the reference voltage source, V DAC represents the output voltage value of the output end of the core DAC, and R1 represents the resistance value of the second resistor. determining the first compensation current value based on the difference between the sum of the first current and the second current and the first constant current value of the positive electrode of the reference voltage source; determining the second compensation current value based on the difference between the sum of the second current and the first compensation current value and the second constant current value of the negative electrode of the reference voltage source, so as to additionally compensate the current drawn by the shunt device at the negative electrode of the reference voltage source; controlling the first compensation DAC to output compensation current according to the first compensation current value, so as to compensate the positive electrode current of the reference voltage source to the first constant current value; controlling the second compensation DAC to output compensation current according to the second compensation current value, so as to compensate the negative electrode current of the reference voltage source to the second constant current value.

13. A digital-to-analog conversion device, comprising: comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the method of claim 11 or 12 when executing the instructions stored in the memory.

14. A non-transitory computer readable storage medium having stored thereon computer program instructions, wherein, The computer program instructions, when executed by the processor, implement the method of claim 11 or 12. The computer program instructions, when executed by the processor, implement the method of claim 11 or 12.

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