Differential data transfer between galvanically isolated circuits within circuit package

Abstract

The invention relates to differential data transfer between galvanically isolated circuits within a circuit package. In some examples, a method includes transmitting first data between a first circuit and a second circuit across a galvanic isolation barrier via a differential communication channel within a circuit package, where the first data is encoded via a first encoding technique including on-off shift keying (OOK) using a differential carrier signal. The method further includes transmitting second data between the first circuit and the second circuit across the galvanic isolation barrier via the differential communication channel within the circuit package, where the second data is encoded via a second encoding technique including differential pulse encoding.

Description

Technical Field

[0001] The present disclosure relates to devices including a galvanic isolation barrier formed between two different circuits within a circuit package, and techniques for transmitting data across the galvanic isolation barrier within the circuit package. Background Art

[0002] Galvanic isolation can be used in electronic devices to separate two voltage domains within a circuit package. As an example, a microcontroller can generate and deliver control signals to a low-side gate driver and a high-side gate driver for controlling a low-side power switch and a high-side power switch arranged in a half-bridge circuit. Galvanic isolation may be desirable to ensure that the microcontroller is protected from the influence of a high voltage domain associated with one or two gate drivers. The microcontroller and one or two gate drivers can be configured to operate in different power domains.

[0003] A gate driver for a power switch is just one example in which galvanic isolation is used, but galvanic isolation can also be used for other purposes. Typically, when galvanic isolation is required, a circuit package can be defined by two different galvanically isolated circuits. Galvanic isolation is achieved by galvanically isolating a low voltage domain of a first circuit from a high voltage domain of a second circuit using a transformer, or by galvanically isolating a low voltage domain of a first circuit from a high voltage domain of a second circuit using one or more capacitors. It is desirable to transmit data across a galvanic isolation barrier (e.g., within a circuit package) to facilitate control of a circuit in a high voltage domain based on a control signal generated in a low voltage domain. Summary of the invention

[0004] The present disclosure describes a circuit package device and a technique for transmitting data within the circuit package device. In particular, the present disclosure describes a technique for communicating over a galvanic isolation barrier between two different circuits formed within a circuit package. A differential communication channel can be configured to transmit data between a first circuit and a second circuit across the galvanic isolation barrier within the circuit package.

[0005] According to the present disclosure, a first circuit and a second circuit may be configured to encode data within a circuit package using two different encoding techniques, and the circuit may transmit the encoded data over a galvanic isolation barrier. The first encoding technique for communicating over the galvanic isolation barrier in the circuit package may include on-off shift keying (OOK) using a differential carrier signal, and the second encoding technique for communicating over the galvanic isolation barrier in the circuit package may include differential pulse encoding.

[0006] In some examples, the present disclosure describes a device arranged to include a galvanic isolation barrier between a first voltage domain and a second voltage domain, the device comprising: a first circuit configured to operate in the first voltage domain; a second circuit configured to operate in the second voltage domain; one or more isolation elements configured to define a galvanic isolation barrier between the first voltage domain and the second voltage domain; and a differential communication channel configured to transmit data between the first circuit and the second circuit across the galvanic isolation barrier, wherein the first circuit and the second circuit are configured to encode the data across the differential communication channel using a first encoding technique and a second encoding technique, wherein the first encoding technique includes OOK using a differential carrier signal, and wherein the second encoding technique includes differential pulse encoding.

[0007] In some examples, the present disclosure describes a method comprising: transmitting first data between a first circuit and a second circuit via a differential communication channel across a galvanic isolation barrier within a circuit package, wherein the first data is encoded via a first encoding technique, the first encoding technique comprising OOK using a differential carrier signal; and transmitting second data between the first circuit and the second circuit via a differential communication channel across the galvanic isolation barrier within the circuit package, wherein the second data is encoded via a second encoding technique, the second encoding technique comprising differential pulse encoding.

[0008] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A – Figure 1C is a conceptual cross-sectional side view of a circuit package including two distinct circuits separated by a galvanic isolation barrier.

[0010] Figure 2 is a block diagram illustrating galvanic isolation between a receiver circuit and a transmitter circuit.

[0011] Figure 3 is a set of graphs illustrating differential on-off shift keying (OOK) consistent with the present disclosure.

[0012] Figure 4 is a set of graphs illustrating differential pulse encoding consistent with the present disclosure.

[0013] Figure 5 is a set of graphs illustrating a combination of differential OOK and differential pulse encoding consistent with the present disclosure.

[0014] Figure 6 – Fig. 9is a block diagram illustrating circuitry configured to communicate across a galvanic isolation barrier consistent with the present disclosure.

[0015] Fig.10 is a more detailed block diagram illustrating an example of a circuit configured to communicate across a galvanic isolation barrier consistent with the present disclosure.

[0016] Fig.11 is a set of graphs illustrating the combination of OOK and pulse coding consistent with the present disclosure.

[0017] Fig.12 is a diagram illustrating a system including a high-side driver and a low-side driver, and a high-side switch and a low-side switch arranged in a half-bridge according to an example of the present disclosure.

[0018] Fig.13 It is shown that the present disclosure is consistent with the Fig.12 A set of diagrams showing more details of the driver circuit communication technique.

[0019] Fig.14 is a flow chart consistent with the present disclosure. DETAILED DESCRIPTION

[0020] The present disclosure describes a circuit package device and a technique for transmitting data within the circuit package device. In particular, the present disclosure describes a technique for communicating over a galvanic isolation barrier between two different circuits formed within a circuit package. As an example, a first circuit may operate in a first voltage domain (e.g., a low voltage domain of less than 40 volts) and a second circuit may operate in a second voltage domain (e.g., a high voltage domain of greater than 100 volts).

[0021] The first circuit and the second circuit can be embedded in a molding material within the circuit package, and the first circuit and the second circuit can be mechanically separated from each other within the circuit package at a distance of less than 5 mm, less than 3 mm, or less than 1 mm. One or more inductors and / or one or more capacitors can be used to implement a galvanic isolation barrier. One or more inductors and / or one or more capacitors that define galvanic isolation can also form a communication channel for transmitting data between two different circuits within the circuit package.

[0022] The communication channel across the galvanic isolation barrier and between the first circuit and the second circuit may include a differential communication channel. According to the present disclosure, the first circuit and the second circuit may be configured to encode data across the differential communication channel using two different encoding techniques. The first encoding technique for communicating over the galvanic isolation barrier in the circuit package may include on-off shift keying (OOK) using a differential carrier signal, and the second encoding technique for communicating over the galvanic isolation barrier in the circuit package may include differential pulse encoding.

[0023] Figure 1A 1 is a conceptual cross-sectional side view of a device including a circuit package 100A. The circuit package 100A includes a first circuit 102A configured to operate in a first voltage domain and a second circuit 112A configured to operate in a second voltage domain. The first voltage domain is different from the second voltage domain. For example, the first voltage domain may include a low voltage domain of less than 40 volts, and the second voltage domain may include a high voltage domain of greater than 100 volts. The circuit 102A may include a first circuit die 106A, and the circuit 112A may include a second circuit die 116A. One or more first outer conductors 108A may be electrically connected to the first circuit die 106A, and similarly, one or more second outer conductors 118A may be electrically connected to the second circuit die 116A. The insulator material 104A may be formed over the first circuit die 106A, and similarly, the insulator material 114A may be formed over the second circuit die 116A.

[0024] In circuit package 100A, one or more isolation elements (e.g., inductor(s) 152A or capacitor(s) 154A) are configured to define a galvanic isolation barrier between a first voltage domain and a second voltage domain. For example, inductor 152A may be arranged to define a transformer such as a coreless transformer. One or more isolation elements (e.g., inductor(s) 152A or capacitor(s) 154A) also define a differential communication channel 150A that is configured to transmit data between first circuit 102A and second circuit 112A across the galvanic isolation barrier. Figure 1AIn the example shown in , one or more isolation elements (e.g., (multiple) inductors 152A or (multiple) capacitors 154A) can be embedded in an insulator 104A associated with a first circuit 102A operating in a low voltage domain. In some examples, a ground protection band can surround the isolation element, and in some examples, the ground protection band can also surround the circuit 102A operating in the low voltage domain. A ground protection band (not shown) can improve the galvanic isolation between two different circuits. Molding material 110A can encapsulate circuits 102A, 112A to define a circuit package 100A. Other devices or circuits can be connected to the circuit package 100A via external conductors 108A, 118A.

[0025] As described in more detail below, the first circuit 102A and the second circuit 112A can be configured to encode data across the differential communication channel 150A within the circuit package 100A using two different encoding techniques. The first encoding technique includes on-off shift keying (OOK) using a differential carrier signal, while the second encoding technique includes differential pulse coding.

[0026] Figure 1B is a conceptual cross-sectional side view of a device including the circuit package 100B. Figure 1B The circuit package 100B is similar in many respects to Figure 1A Circuit package 100B is very similar to circuit package 100A. Circuit package 100B includes a first circuit 102B configured to operate in a first voltage domain and a second circuit 112B configured to operate in a second voltage domain. The first voltage domain is different from the second voltage domain. Again, for example, the first voltage domain may include a low voltage domain of less than 40 volts, and the second voltage domain may include a high voltage domain of greater than 100 volts. Circuit 102B may include a first circuit die 106B, and circuit 112B may include a second circuit die 116B. One or more first outer conductors 108B may be electrically connected to the first circuit die 106B, and similarly, one or more second outer conductors 118B may be electrically connected to the second circuit die 116B. Insulator material 104B may be formed on the first circuit die 106B, and similarly, insulator material 114B may be formed on the second circuit die 116B.

[0027] In the circuit package 100B, one or more isolation elements (e.g., inductor(s) 152B or capacitor(s) 154B) are configured to define a galvanic isolation barrier between a first voltage domain and a second voltage domain. The one or more isolation elements (e.g., inductor(s) 152B or capacitor(s) 154B) also define a differential communication channel 150B that is configured to transmit data between the first circuit 102B and the second circuit 112B across the galvanic isolation barrier. Figure 1B In the example shown in , one or more isolation elements (e.g., (multiple) inductors 152B or (multiple) capacitors 154B) are embedded in an insulator 104B associated with a first circuit 102B and within an insulator 114B associated with a second circuit 112B. In some examples, a ground guard band can surround the isolation elements, and in some examples, the ground guard band can also surround one or both of the circuits 102B, 112B. Molding material 110B can encapsulate circuits 102B, 112B to define circuit package 100B. Other devices or circuits can be connected to circuit package 100B via external conductors 108B, 118B.

[0028] and Figure 1A As in the example shown in Figure 1B In the embodiment, the first circuit 102B and the second circuit 112B can be configured to encode data across the differential communication channel 150B within the circuit package 100B using two different encoding techniques. The first encoding technique OOK uses a differential carrier signal, while the second encoding technique includes differential pulse encoding.

[0029] Figure 1C is a conceptual cross-sectional side view of a device including the circuit package 100C. Figure 1C The circuit package 100C is similar in many respects to Figure 1A and Figure 1B The circuit packages 100A and 100B are very similar. The circuit package 100C includes a first circuit 102C configured to operate in a first voltage domain, and a second circuit 112C configured to operate in a second voltage domain. The first voltage domain is different from the second voltage domain. Again, for example, the first voltage domain may include a low voltage domain of less than 40 volts, and the second voltage domain may include a high voltage domain of greater than 100 volts. Figure 1C In the example shown in , the first circuit 102C and the second circuit 112C are formed in the same circuit die. In this case, in order to ensure the current isolation between the first circuit 102C and the second circuit 112C, a deep trench 120C is formed in the circuit die between the first circuit 102C and the second circuit 112C to achieve isolation.

[0030] One or more first outer conductors 108C may be electrically connected to a first portion of die 106C, and similarly, one or more second outer conductors 118C may be electrically connected to a second portion of die 116C.Insulator material 104C may be formed over the circuit dies defining first circuit 102C and second circuit 112C.

[0031] In the circuit package 100C, one or more isolation elements (e.g., inductor(s) 152C or capacitor(s) 154C) are located within the insulator 104C and are configured to define a galvanic isolation barrier between a first voltage domain and a second voltage domain. The one or more isolation elements (e.g., inductor(s) 152C or capacitor(s) 154C) also define a differential communication channel 150C that is configured to transmit data between the first circuit 102C and the second circuit 112C across the galvanic isolation barrier. Figure 1C In the example shown in , one or more isolation elements (e.g., (multiple) inductors 152B or (multiple) capacitors 154B) are embedded in an insulator 104C, which is formed on a common circuit die defining a first circuit 102C and a second circuit 112C. In some examples, a ground guard band can surround the isolation elements, and in some examples, the ground guard band can also surround one or both of the circuits 102C, 112C. Molding material 110C can encapsulate circuits 102C, 112C to define a circuit package 100C. Other devices or circuits can be connected to the circuit package 100C via external conductors 108C, 118C.

[0032] and Figure 1A and Figure 1B As in the example shown in Figure 1C In the example shown in , the first circuit 102C and the second circuit 112C can be configured to encode data across a differential communication channel 150C within the circuit package 100C using two different encoding techniques. The first encoding technique OOK uses a differential carrier signal, while the second encoding technique includes differential pulse encoding.

[0033] In some various examples, the first circuit 102A, 102B, 102C can operate in a low voltage domain (such as a voltage domain associated with a microcontroller, such as 5 volts, 3.3 volts, or another voltage commonly used for low voltage microcontrollers). The second circuit 112A, 112B, 112C can operate in a high voltage domain (such as a voltage domain associated with a high voltage power switch, such as 400-6000 volts associated with an insulated gate bipolar transistor (IGBT), 600-1200 volts associated with a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET), 600-1200 volts associated with a gallium nitride (GaN) field effect transistor (FET), or an even higher voltage associated with a gate turn-on (GTO) thyristor, another type of thyristor, or another type of power switch). In other examples, the techniques and circuits of the present disclosure can be used in any circuit package device where communication is performed over a galvanic isolation barrier within the circuit package device.

[0034] Figure 2 2 is a block diagram illustrating galvanic isolation between a receiver circuit and a transmitter circuit. As an example, a transmitter circuit (TX) 202 may correspond to Figure 1A , Figure 1B , Figure 1C The first circuit 102A, 102B, 102C in FIG. 1 and the receiver circuit (RX) 204 may correspond to Figure 1A , Figure 1B , Figure 1C As shown in the figure, there is a galvanic isolation barrier 206 between TX 202 and RX 204. Figure 2 The "a" and "b" signal paths shown in correspond to differential signals, which are ideal for achieving high common mode transient immunity (CMTI). TX 202 and RX 204 may reside within a circuit package. In addition, according to the present disclosure, TX 202 and RX 204 may communicate using two different communication protocols (e.g., OOK and pulse coding).

[0035] Figure 3 is a set of graphs illustrating differential OOK consistent with the present disclosure. Figure 3 OOK is a form of amplitude shift keying (ASK) modulation that converts digital data (such as Figure 3 The input data shown) is represented as a carrier wave (eg Figure 3 For differential OOK, carrier “a” can be phase shifted relative to carrier “b”. Differential carrier data (e.g. Figure 3a and b) in may be transmitted from TX 202 and received by RX 204 and then decoded to generate Figure 3 The output data may represent binary bits similar to the input data, and time t1 represents, for example, the output data generated by an envelope detector based on differential carrier data (e.g. Figure 3 a and b) The delay time required to reconstruct the data.

[0036] Figure 4 is a set of graphs illustrating differential pulse encoding consistent with the present disclosure. For differential pulse encoding (i.e., pulse encoding over differential communication channels), a first pulse (e.g., Figure 4 ) and then encodes a second pulse (e.g., Figure 4 The output data may represent the time delay between the first pulse and the second pulse, and the output data may include binary bits similar to the input data, where time t2 represents the time delay between the first pulse and the second pulse (e.g., Figure 4 a and b) The delay time required to reconstruct the data (e.g. the delay time of the amplitude detector and any additional latch time required).

[0037] According to this disclosure, Figure 3 and Figure 4 The two different modulation schemes shown in are used simultaneously and in parallel within the circuit package, which can increase the amount of data that can be sent over the galvanic isolation barrier using differential signaling. In addition, some data (such as more data-intensive projects) may be better suited for pulse encoding, while some data (such as data requiring higher integrity) may be better suited for OOK.

[0038] Figure 5 is a set of graphs illustrating a combination of differential OOK and differential pulse coding consistent with the present disclosure. In this example, input data 1 and input data 2 are encoded in parallel. In particular, input data 1 is encoded with differential OOK, while input data 2 is encoded with differential pulse coding. Figure 5 Figures "b" and "a" shown in FIG. 1 show the combined pulse and differential carrier signals in each channel of differential communication.

[0039] Based on the pulses encoded in the first channel relative to the second channel (e.g. Figure 5 The output data 2 is reconstructed at the receiver side based on the time envelope defined by the differential carrier encoded on both the first channel and the second channel. The output data (output data 1 and output data 2) has a slight delay relative to the input data. Figure 5The time t1 shown in is the delay time for the envelope detector to reconstruct the output data 1 from the differential carrier encoded on both the first channel and the second channel. Figure 5 The time t2 shown in is the delay time (eg the delay time of the amplitude detector and any additional latching time required) required to reconstruct the output data 2 (reconstructing the data based on the pulses encoded in the first channel and the second channel).

[0040] In some examples, to facilitate or improve the ability to decode two different types of data in parallel, the differential pulse coding can define pulses having an amplitude greater than the differential carrier signal such that the amplitude detector can detect the pulses in the presence of the differential carrier signal. Additionally, the pulse length of the pulses can be less than a detection time associated with an envelope detector such that the envelope detector can detect the differential carrier signal in the presence of the pulses associated with the differential pulse coding.

[0041] Figure 6-Figure 9 is a block diagram illustrating some example circuits configured to communicate across a galvanic isolation barrier consistent with the present disclosure.

[0042] Figure 6 One example of a device (eg, a circuit package) arranged to include a galvanic isolation barrier 640 between a first voltage domain (on the left side of 640 ) and a second voltage domain (on the right side of 640 ) is shown. Figure 6 The device shown in FIG. 1 may include: a first circuit 602 configured to operate in a first voltage domain; a second circuit 612 configured to operate in a second voltage domain. An isolation element 650 is configured to define a current isolation barrier 640 between the first voltage domain and the second voltage domain. In addition, the isolation element 650 defines a current isolation barrier 640 for transmitting Figure 6 . The differential communication channel is configured to transmit data between the first circuit 602 and the second circuit 612 across the galvanic isolation barrier 640. In addition, the first circuit 602 and the second circuit 612 are configured to encode the data across the differential communication channel using a first encoding technique and a second encoding technique, wherein the first encoding technique includes OOK using a differential carrier signal, and wherein the second encoding technique includes differential pulse encoding.

[0043] exist Figure 6 In the example shown in FIG. 6 , the first circuit 602 includes a first transmitter (TX1) 604 and a second transmitter (TX2) 606. TX1 604 is configured to perform OOK encoding, and TX2 606 is configured to perform pulse encoding. The second circuit 612 includes a first receiver (RX1) 614 and a second receiver (RX 2) 616. RX1 614 is configured to perform OOK decoding, and RX2 616 is configured to perform pulse decoding. Compared to conventional device packages, Figure 6 The device may facilitate unidirectional communication with improved bandwidth for inter-circuit communication.

[0044] Figure 7 One example of a device (eg, a circuit package) is shown that is arranged to include a galvanic isolation barrier 740 between a first voltage domain (left side of 740 ) and a second voltage domain (right side of 740 ). Figure 7 The device shown in FIG. 7 may include a first circuit 702 configured to operate in a first voltage domain, and a second circuit 712 configured to operate in a second voltage domain. The isolation element 750 is configured to define a galvanic isolation barrier 740 between the first voltage domain and the second voltage domain. In addition, the isolation element 750 defines a current isolation barrier 740 for transmitting Figure 7 . The differential communication channel is configured to transmit data between the first circuit 702 and the second circuit 712 across the galvanic isolation barrier 740. In addition, the first circuit 702 and the second circuit 712 are configured to encode the data across the differential communication channel using a first encoding technique and a second encoding technique, wherein the first encoding technique includes OOK using a differential carrier signal, and wherein the second encoding technique includes differential pulse encoding.

[0045] exist Figure 7 In the example shown in , the first circuit 702 includes a first transmitter (TX1) 704 and a first receiver (RX2) 706. TX1 704 is configured to perform OOK encoding, and RX2 706 is configured to perform pulse decoding. The second circuit 612 includes a second receiver (RX1) 714 and a second transmitter (TX2) 716. RX1 714 is configured to perform OOK decoding, and TX2 616 is configured to perform pulse encoding. Figure 7 The device can facilitate bidirectional communication over the galvanic isolation barrier 740 within the device, where higher bandwidth pulse coding is used for communication from circuit 712 to circuit 702, and higher reliability OOK coding is used for communication from circuit 702 to circuit 712. Of course, the OOK and pulse coding directions can also be reversed, such that higher bandwidth pulse coding can be used for communication from circuit 702 to circuit 712, and higher reliability OOK coding can be used for communication from circuit 712 to circuit 702.

[0046] Figure 8 One example of a device (eg, a circuit package) arranged to include a galvanic isolation barrier 840 between a first voltage domain (left side of 840 ) and a second voltage domain (right side of 840 ) is shown. Figure 8The device shown in FIG. 1 may include a first circuit 802 configured to operate in a first voltage domain, and a second circuit 812 configured to operate in a second voltage domain. Isolation elements in the form of inductors 852, 854 are configured to define a galvanic isolation barrier 840 between the first voltage domain and the second voltage domain. In addition, the inductors 852, 854 define a current isolation barrier 840 for transmitting Figure 8 8. In some examples, inductors 852, 854 may include so-called coreless transformers.

[0047] The differential communication channel is configured to transmit data between the first circuit 802 and the second circuit 812 across the galvanic isolation barrier 840. In addition, the first circuit 802 and the second circuit 812 are configured to encode the data across the differential communication channel using a first encoding technique and a second encoding technique, wherein the first encoding technique includes OOK using a differential carrier signal, and wherein the second encoding technique includes differential pulse encoding.

[0048] and Figure 6 Similar, in Figure 8 In the example shown in , the first circuit 802 includes a first transmitter (TX1) 804 and a second transmitter (TX2) 806. TX1 804 is configured to perform OOK encoding, and TX2 806 is configured to perform pulse encoding. The second circuit 812 includes a first receiver (RX1) 814 and a second receiver (RX2) 816. RX1 814 is configured to perform OOK decoding, and RX2 816 is configured to perform pulse decoding. Compared to conventional device packages, Figure 8 The device may facilitate unidirectional communication with improved bandwidth for inter-circuit communication.

[0049] Fig. 9 One example of a device (eg, a circuit package) is shown that is arranged to include a galvanic isolation barrier 940 between a first voltage domain (on the left side of 940 ) and a second voltage domain (on the right side of 940 ). Fig. 9 The device shown in FIG. 1 may include a first circuit 902 configured to operate in a first voltage domain and a second circuit 912 configured to operate in a second voltage domain. Isolation elements in the form of capacitors 952, 954 are configured to define a galvanic isolation barrier 940 between the first voltage domain and the second voltage domain. In addition, capacitors 952, 954 define a current isolation barrier 940 for transmitting Fig. 9 The differential communication channels of signals "a" and "b" are shown in FIG.

[0050] The differential communication channel is configured to transmit data between the first circuit 902 and the second circuit 912 across the galvanic isolation barrier 940. In addition, the first circuit 902 and the second circuit 912 are configured to encode the data across the differential communication channel using a first encoding technique and a second encoding technique, wherein the first encoding technique includes OOK using a differential carrier signal, and wherein the second encoding technique includes differential pulse encoding.

[0051] and Figure 6 Similar, in Fig. 9 In the example shown in , the first circuit 902 includes a first transmitter (TX1) 904 and a second transmitter (TX2) 906. TX1 904 is configured to perform OOK encoding, and TX2 906 is configured to perform pulse encoding. The second circuit 912 includes a first receiver (RX1) 914 and a second receiver (RX2) 916. RX1 914 is configured to perform OOK decoding, and RX2 916 is configured to perform pulse decoding. Compared to conventional device packages, Fig. 9 The device may facilitate unidirectional communication with improved bandwidth for inter-circuit communication.

[0052] In some examples, Figure 8 The inductors 852 and 854 can be used to Figure 7 In some examples, Figure 8 The inductors 852 and 854 can be used to Figure 6 In some examples, Fig. 9 The capacitors 952 and 954 can be used for Figure 7 In some examples, Fig. 9 The capacitors 952 and 954 can be used for Figure 6 The isolation element 650 is provided.

[0053] and Figure 6 , Figure 8 ,as well as Fig. 9 In accordance with the present invention, the first circuit 602, 802, 902 may include a first transmitter (TX1) 604, 804, 904 configured to decode the first information using the first coding technique, and a second transmitter (TX2) 606, 806, 906 configured to decode the second information using the second coding technique. The second circuit 612, 812, 912 may include a first receiver (RX1) 614, 814, 914 configured to decode the first information using the first coding technique, and a second receiver (RX2) 616, 816, 916 configured to decode the second information using the second coding technique.

[0054] and Figure 7In accordance with the present invention, the first circuit 702 may include a first transmitter TX1 704 configured to decode the first information using the first coding technique, and a first receiver RX2 706 configured to decode the second information using the second coding technique. The second circuit 712 includes a second transmitter TX2 716 configured to decode the second information using the second coding technique, and a second receiver RX1 714 configured to decode the first information using the first coding technique.

[0055] Fig.10 One example of a device (eg, a circuit package) arranged to include a galvanic isolation barrier 1040 between a first voltage domain (left side of 1040 ) and a second voltage domain (right side of 1040 ) is shown. Fig.10 The device shown in FIG. 1 may include a first circuit 1002 configured to operate in a first voltage domain, and a second circuit 1012 configured to operate in a second voltage domain. Isolation elements in the form of inductors 1052, 1054 are configured to define a galvanic isolation barrier 1040 between the first voltage domain and the second voltage domain. In addition, the inductors 1052, 1054 define a current isolation barrier 1040 for transmitting Fig.10 1054. In some examples, inductors 1052, 1054 may include so-called coreless transformers.

[0056] The differential communication channel is configured to transmit data between the first circuit 1002 and the second circuit 1012 across the galvanic isolation barrier 1040. In addition, the first circuit 1002 and the second circuit 1012 are configured to encode the data across the differential communication channel using a first encoding technique and a second encoding technique, wherein the first encoding technique includes OOK using a differential carrier signal, and wherein the second encoding technique includes differential pulse encoding.

[0057] As with some of the other examples above, in Fig.10 In the example shown in , the first circuit 1002 includes a first transmitter (TX1) 1004 and a second transmitter (TX2) 1006. TX1 1004 is configured to perform OOK encoding, and TX2 1006 is configured to perform pulse encoding. The second circuit 1012 includes a first receiver 1014 and a second receiver 1016. The first receiver 1014 is configured to perform OOK decoding, and the second receiver 1016 is configured to perform pulse decoding. Compared to conventional device packages, Fig.10 The device may facilitate unidirectional communication with improved bandwidth for inter-circuit communication.

[0058] Fig.11is a set of diagrams showing OOK combined with pulse coding consistent with the present disclosure. The OOK data may include first data 1104a, 1104b encoded with a differential carrier signal, and the second pulse coded data may include second data 1102a, 1102b encoded with differential pulse coding. The differential coded channel is composed of Fig.11 The individual graphs of "a" and "b" shown in FIG. Fig.11 The signal "a" includes a portion of the first data 1104a and a portion of the second data 1102a, and Fig.11 The signal "b" includes a portion of the first data 1104b and a portion of the second data 1102b.

[0059] Reference again Fig.10 , in order to Fig.11 1004 may include an RF oscillator 1034 configured to generate a carrier signal. TX1 1004 may also include an AND circuit 1036 configured to receive input data 1 and decode the input data 1 on a carrier frequency. For example, the input data 1 may define a pulse length, and the pulse length may be combined with the carrier frequency by the AND circuit 1036 to generate a carrier with a pulse duration of the pulse length defined by the input data 1, thereby generating Fig.11 The first data 1104a, 1104b shown in FIG.

[0060] For the sake of Fig.11 1006 may include an edge detection + pulse shaping unit 1026 configured to receive input data 2. Unit 1026 generates a short pulse at a defined time defined by input data 2, and drivers 1028, 1032 amplify the short pulse to generate Fig.11 The second data 1102a, 1102b shown in FIG.

[0061] Fig.10 The signals "a" and "b" shown in FIG. Fig.11 The inductors 1052 and 1054 are defined for transmitting the signals "a" and "b" shown in FIG. Fig.10 The differential communication channels of signals "a" and "b" are shown in FIG.

[0062] On the receiver side, the second circuit 1012 includes a first receiver 1014 and a second receiver 1016. The first receiver 1014 is configured to perform OOK decoding, and the second receiver 1016 is configured to perform pulse decoding. The second receiver 1016 may include an amplitude detector 1060 for detecting the first data 1102a, 1102b. The first data 1102a, 1102b may include pulses associated with differential pulse coding. The amplitude detector 1060 may include a comparison unit 1062 and a memory circuit (e.g., a flip-flop 1064) to latch any pulses identified by the comparison unit 1062. In some examples, the differential pulse coding defines a pulse having an amplitude greater than a differential carrier signal, so that the amplitude detector 1060 can detect the pulse in the presence of a differential carrier signal. In other words, the amplitude detector 1060 can identify the data 1102a, 1102b in the presence of the data 1104a, 1104b because the amplitude of the data 1102a, 1102b is greater than the amplitude of the differential carrier signal of the data 1104a, 1104b. For example, the comparison unit 1062 can be configured to identify the pulse by comparing the data amplitude with a threshold defined based on the amplitude of the differential carrier.

[0063] The first receiver 1014 may include an envelope detector 1070 for detecting the differential carrier signal. A detection time associated with the envelope detector 1070 is configured relative to the pulse length of the pulse coded data to ensure that the envelope detector can detect the differential carrier signal in the presence of pulses associated with the differential pulse coding. In other words, the pulse length of the pulses in the data 1102a, 1102b is less than the detection time associated with the envelope detector, so that the envelope detector can detect the differential carrier signal in the data 1104a, 1104b in the presence of pulses associated with the differential pulse coding in the data 1102a, 1102b.

[0064] In some examples, the envelope detector 1070 may include a differential to single-ended conversion unit 1072, which is configured to convert the received differential signal into a single-ended signal. The envelope detector 1070 may also include a peak detector 1074, which is configured to identify the peak value of the carrier signal. For example, the peak detector 1074 may include a diode 1082 connected to an RC circuit. The peak detector 1074 is configured to operate as a filter with an integral behavior. The RC circuit may include a capacitor 1084 and a resistor 1086 connected in series between a ground voltage and the output of the diode 1082. The comparator 1076 identifies the carrier signal by comparing the output signal of the peak detector 1074 with a threshold value based on the expected voltage amplitude of the carrier signal. In some examples according to the present disclosure, the pulse length of the pulse coding is short (e.g., about 2 nanoseconds) relative to the detection time of the envelope detector 1070, which can help ensure that the second circuit 1012 can separate and identify signals of two different modulation schemes. The second circuit 1012 is configured to output data 1 (OOK data) and output data 2 (pulse coded data). Output data 1 corresponds to input data 1 encoded in OOK, and output data 2 corresponds to input data 2 encoded in pulse.

[0065] In some examples, the techniques and circuits of the present disclosure can be used for high voltage gate drivers where input data from a low voltage microcontroller or processor side is transmitted over a galvanic isolation barrier to a high voltage domain on the power supply side, and vice versa.

[0066] Fig.12 1 is a diagram showing a system including a high-side driver 1220 and a low-side driver 1240, and a high-side power switch 1260 and a low-side power switch 1280 arranged in a half-bridge according to an example of the present disclosure. For example, the high-side power switch 1260 and the low-side power switch 1280 may include any type of field effect transistor (FET), including a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), a high electron mobility transistor (HEMT), or any one or a combination of other types of elements that use voltage or current for control.

[0067] The power switches 1260, 1280 may be formed of various material compounds, such as silicon, silicon carbide, gallium nitride, or any other combination of one or more semiconductor materials. In some examples, silicon carbide switches may experience lower switching power losses. Magnetic improvements and faster switches (such as gallium nitride switches) may allow power transistors to absorb short bursts of current. These higher frequency devices may need to send control signals (e.g., voltage signals delivered to the control terminals of the power transistors) with more precise timing than low frequency devices.

[0068] Fig.12 The system shown in FIG. 1 includes a first device 1202 (i.e., a first circuit package) and a second device 1204 (i.e., a second circuit package). The first device 1202 and the second device 1204 may each correspond to any device shown and described above, such as in FIG. Figure 1A – Figure 1C , or Figure 6 – Fig.10 The details of the first device 1202 and the second device 1204 are not repeated here, but have been described above.

[0069] like Fig.12 , the first device 1202 is configured to transmit data to the high-side driver 1220, and the second device 1204 is configured to transmit data to the low-side driver 1240. In this case, OOK encoded data may be more suitable for the first type of data of the drivers 1220, 1240, and pulse encoded data may be more suitable for the second type of data of the drivers 1220, 1240.

[0070] The drivers 1220 and 1240 each include a current source 1222, 1224, 1242, 1244. The drivers 1220 and 1240 also include control switches 1226 and 1246. More specifically, the high-side driver 1220 includes current sources 1222, 1224 and a control switch 1226, and the low-side driver 1240 includes current sources 1242, 1244 and a control switch 1246. In some examples, the first device 1202 is configured to transmit a switch signal to the switch 1226 to control the gate of the high-side switch 1260. Similarly, the second device 1204 is configured to transmit a switch signal to the switch 1246 to control the gate of the low-side switch 1280. It is desirable that the switch signal has a relatively low error rate, and therefore, OOK is well suited for the first device 1202 to control the switch 1226, and is also well suited for the second device 1204 to control the switch 1246. RX1 of device 1202 may be configured to output the OOK signal to control switch 1226 , and RX1 of device 1204 may be configured to output the OOK signal to control switch 1226 .

[0071] In some cases, it is desirable to control or adjust the settings of the current sources 1222, 1224 and the current sources 1242, 1244, such as the settings for the intensity on / off of the switch drivers 1220 and 1240 or other settings. For example, the current sources 1222, 1224 and the current sources 1242, 1244 can be configured in terms of the current or level used. However, the setting changes do not necessarily require the robustness required for controlling the switches 1226, 1246. Due to error signals or other problems, a delay of several cycles when adjusting the settings of the current sources 1222, 1224 and the current sources 1242, 1244 may be acceptable. In addition, the setting changes may require more bandwidth (e.g., more data) than the signals used to control the switches 1226, 1246. Pulse coded data is very suitable for the first device 1202 to control or adjust the settings of the current sources 1222, 1224, and is very suitable for the second device 1204 to control or adjust the settings of the current sources 1242, 1244. RX2 of device 1202 may be configured to output a pulse coded signal to control or adjust the settings of current sources 1222 , 1224 , and RX2 of device 1204 may be configured to output a pulse coded signal to control or adjust the settings of current sources 1242 , 1244 .

[0072] Accordingly, the first data (OOK data) transmitted by the device 1202 may include a switching signal for controlling the high-side power switch 1260 via the high-side driver circuit 1220 operating in the second voltage domain, and the second data (pulse coded data) may include configuration data for the high-side driver circuit 1220 operating in the second voltage domain.

[0073] Similarly, the first data (OOK data) transmitted by device 1204 may include a switching signal for controlling the low-side power switch 1280 via a low-side driver circuit 1240 operating in the second voltage domain, and the second data (pulse coded data) may include configuration data for the low-side driver circuit 1240 operating in the second voltage domain.

[0074] and Fig.12 Consistently, in some examples, when the high-side power switch 1260 or the low-side power switch is in the on state, the first data (OOK data) can be transmitted from the first device 1202 or the second device 1204, wherein the high-side power switch 1260 and the low-side power switch 1280 are arranged in a half-bridge configuration, and wherein when both the high-side power switch 1260 and the low-side power switch 1280 are in the off state, the second data (pulse coded data) is transmitted during the dead time. Fig.13 An example of the timing details of such a signal is shown.

[0075] Fig.13This is consistent with the present disclosure. Fig.12 A set of diagrams showing more details of the communication technique for the driver circuit. In this example, the dead time (t d ) during the first time period (t 1 ) to transmit input data 2 (such as pulse coded data). Dead time (t d ) refers to the time period in the switching cycle when both the high-side power switch 1260 and the low-side power switch 1280 are in the off state. A dead time (t d ) to prevent cross conduction in the half-bridge. The second time period (t2) may define sufficient time to transfer or implement the transmitted settings to the output stage (i.e., the time required to adjust the settings of the current sources 1222, 1224 of the driver 1220, or the time required to adjust the settings of the current sources 1242, 1244 of the driver 1240). Thus, according to this example, the dead time "time slot" 1302 may be used to configure the output strength of the driver 1220 or the driver 1240 using the pulse coded data. The third time period (t 3 ) can be used to send a switching signal to switch 1226 of driver 1220 or switch 1246 of driver 1240 using OOK data.

[0076] Fig.14 is a flow chart consistent with the present disclosure. Fig.14 As shown in FIG. 1 , a first circuit 102A, 102B, 102C, 602, 702, 802, 902, 1002 is configured to encode (e.g., decode) first data using OOK on a differential signal (1401). The first circuit 102A, 102B, 102C, 602, 702, 802, 902, 1002 is configured to be connected across a galvanic isolation barrier in the circuit package 100A, 100B, 100C, Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 The first circuit 102A, 102B, 102C, 602, 702, 802, 902, 1002 is further configured to encode (e.g., decode) second data using differential pulse coding (1403). The first circuit 102A, 102B, 102C, 602, 702, 802, 902, 1002 is configured to transmit first data across a galvanic isolation barrier within the circuit package 100A, 100B, 100C, Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10The second circuit 112A, 112B, 112C, 612, 712, 812, 912, 1012 is configured to be in the circuit package 100A, 100B, 100C, Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 The data can be decoded on the receiving side so that the data can be used appropriately.

[0077] The technology described in this disclosure may be implemented at least in part with circuit devices, hardware, software, firmware, or any combination thereof. Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various operations and functions described in this disclosure. In addition, any described unit, module, or component may be implemented together or individually as a discrete but interoperable circuit or device. Describing different features as modules or units is intended to highlight different functional aspects and does not necessarily mean that these modules or units must be implemented by separate components. On the contrary, the functionality associated with one or more modules or units may be performed by separate components or circuits, or may be integrated in common components or circuits. One or more aspects of this disclosure may also be implemented in software, in which case those aspects of the technology described in this disclosure may also be embodied or decoded in a computer-readable medium.

[0078] The following numbered aspects demonstrate one or more aspects of the present disclosure.

[0079] Item 1 - A device arranged to include a galvanic isolation barrier between a first voltage domain and a second voltage domain, the device comprising: a first circuit configured to operate in the first voltage domain; a second circuit configured to operate in the second voltage domain; one or more isolation elements configured to define a galvanic isolation barrier between the first voltage domain and the second voltage domain; and a differential communication channel configured to transmit data between the first circuit and the second circuit across the galvanic isolation barrier, wherein the first circuit and the second circuit are configured to encode data across the differential communication channel using a first encoding technique and a second encoding technique, wherein the first encoding technique includes OOK using a differential carrier signal, and wherein the second encoding technique includes differential pulse encoding.

[0080] Clause 2—The device of Clause 1, wherein the first circuit and the second circuit are formed on different circuit dies, and the device comprises a molding compound formed around the different circuit dies.

[0081] Clause 3 - The device of clause 1, wherein the first circuit and the second circuit are formed on a same circuit die during a semiconductor manufacturing process, wherein a trench is formed in the circuit die to isolate the first voltage domain from the second voltage domain, and wherein the device includes a molding compound formed around the circuit die.

[0082] Clause 4 - The apparatus of any of clauses 1 - 3, wherein the one or more isolation elements comprise a coreless transformer that galvanically isolates the first voltage domain from the second voltage domain.

[0083] Clause 5 - The apparatus of any of Clauses 1 - 3, wherein the one or more isolation elements include one or more capacitors that galvanically isolate the first voltage domain from the second voltage domain.

[0084] Clause 6 – A device according to any of clauses 1 – 5, wherein the first circuit includes a first transmitter and a second transmitter, the first transmitter is configured to encode the first information using a first encoding technique and the second transmitter is configured to encode the second information using a second encoding technique, and wherein the second circuit includes a first receiver and a second receiver, the first receiver is configured to decode the first information using the first encoding technique and the second receiver is configured to decode the second information using the second encoding technique.

[0085] Clause 7 – An apparatus as described in any of clauses 1 – 5, wherein the first circuit includes a first transmitter and a first receiver, the first transmitter being configured to encode the first information using a first encoding technique and the first receiver being configured to decode the second information using a second encoding technique, and wherein the second circuit includes a second transmitter and a second receiver, the second transmitter being configured to encode the second information using the second encoding technique and the second receiver being configured to decode the first information using the first encoding technique.

[0086] Clause 8 - An apparatus according to any of clauses 1 - 7, further comprising: an amplitude detector for detecting pulses associated with differential pulse coding, wherein the differential pulse coding defines pulses having an amplitude greater than a differential carrier signal, such that the amplitude detector is capable of detecting the pulses in the presence of the differential carrier signal.

[0087] Clause 9 - The apparatus of any one of clauses 1 - 8, further comprising: an envelope detector for detecting a differential carrier signal, wherein a pulse length of a pulse is less than a detection time associated with the envelope detector, such that the envelope detector is capable of detecting the differential carrier signal in the presence of a pulse associated with the differential pulse coding.

[0088] Clause 10—The apparatus of clauses 8 and 9, wherein the second circuit comprises an amplitude detector and an envelope detector.

[0089] Clause 11 - Apparatus according to any of clauses 1 - 10, wherein the data comprises first data encoded in a differential carrier signal and second data encoded in a differential pulse code.

[0090] Clause 12—The apparatus of clause 11, wherein the first data comprises a switching signal for controlling the high-side power switch via a high-side driver circuit operating in the second voltage domain, and wherein the second data comprises configuration data for the high-side driver circuit operating in the second voltage domain.

[0091] Clause 13 - A device according to clause 12, wherein the first data is transmitted when the high-side power switch or the low-side power switch is in an on-state, wherein the high-side power switch and the low-side power switch are arranged in a half-bridge configuration, and wherein the second data is transmitted during a dead time when both the high-side power switch and the low-side power switch are in an off-state.

[0092] Clause 14—The apparatus of any of Clauses 1-13, wherein the apparatus comprises a circuit package comprising a molding compound formed around the first circuit, the second circuit, the one or more isolation components, and the differential communication channel.

[0093] Item 15 - A method comprising: transmitting first data between a first circuit and a second circuit via a differential communication channel across a galvanic isolation barrier within a circuit package, wherein the first data is encoded via a first encoding technique, the first encoding technique comprising OOK using a differential carrier signal; and transmitting second data between the first circuit and the second circuit via a differential communication channel across a galvanic isolation barrier within the circuit package, wherein the second data is encoded via a second encoding technique, the second encoding technique comprising differential pulse encoding.

[0094] Clause 16—The method of Clause 15, further comprising: transmitting first data from the first circuit to the second circuit across the galvanic isolation barrier within the circuit package; and transmitting second data from the second circuit to the first circuit across the galvanic isolation barrier within the circuit package.

[0095] Clause 17—The method of Clause 15, further comprising: transmitting first data from the first circuit to the second circuit across the galvanic isolation barrier within the circuit package; and transmitting second data from the first circuit to the second circuit across the galvanic isolation barrier within the circuit package.

[0096] Clause 18 - A method according to any of clauses 15 - 17, wherein the second circuit includes an amplitude detector for detecting pulses associated with differential pulse coding, wherein the differential pulse coding defines pulses having an amplitude greater than a differential carrier signal, such that the amplitude detector can detect the pulses in the presence of the differential carrier signal.

[0097] Clause 19 - A method according to any of clauses 15 - 18, wherein the second circuit includes an envelope detector for detecting the differential carrier signal, wherein the pulse length of the pulse is less than a detection time associated with the envelope detector so that the envelope detector can detect the differential carrier signal in the presence of pulses associated with the differential pulse code.

[0098] Clause 20 - A method according to any of clauses 15 - 19, wherein the first data includes a switching signal for controlling a high-side power switch via a high-side driver circuit operating in a second voltage domain, the second voltage domain being different from a first voltage domain associated with the first circuit, and wherein the second data includes configuration data for the high-side driver circuit operating in the second voltage domain.

[0099] Clause 21 - A method according to clause 20, wherein the first data is transmitted when the high-side power switch or the low-side power switch is in an on-state, wherein the high-side power switch and the low-side power switch are arranged in a half-bridge configuration, and wherein the second data is transmitted during a dead time when both the high-side power switch and the low-side power switch are in an off-state.

[0100] Various examples of the disclosure have been described. Any combination of the described systems, operations, or functions is contemplated. These and other examples are within the scope of the following claims.

Claims

1. A device, the device being arranged to include a galvanic isolation barrier between a first voltage domain and a second voltage domain, the device comprising: a first circuit configured to operate in the first voltage domain; a second circuit configured to operate in the second voltage domain; one or more isolation elements configured to define the galvanic isolation barrier between the first voltage domain and the second voltage domain; as well as a differential communication channel configured to transmit data between the first circuit and the second circuit across the galvanic isolation barrier, wherein the first circuit and the second circuit are configured to encode the data across the differential communication channel using a first encoding technique and a second encoding technique, wherein the first encoding technique comprises on-off shift keying (OOK) using a differential carrier signal, and The second encoding technique includes differential pulse coding. 2 . The device of claim 1 , wherein the first circuit and the second circuit are formed on different circuit dies, and the device comprises a molding compound formed around the different circuit dies.

3. The device of claim 1 , wherein the first circuit and the second circuit are formed on the same circuit die during a semiconductor manufacturing process, a trench is formed in the circuit die to isolate the first voltage domain from the second voltage domain, and wherein the device includes a molding compound formed around the circuit die. 4 . The apparatus of claim 1 , wherein the one or more isolation elements comprise a coreless transformer that galvanically isolates the first voltage domain from the second voltage domain. 5 . The apparatus of claim 1 , wherein the one or more isolation elements comprise one or more capacitors that galvanically isolate the first voltage domain from the second voltage domain.

6. The device according to claim 1, wherein the first circuit includes a first transmitter and a second transmitter, the first transmitter is configured to decode the first information using the first encoding technique, the second transmitter is configured to decode the second information using the second encoding technique, and The second circuit includes a first receiver and a second receiver, the first receiver is configured to decode the first information using the first encoding technology, and the second receiver is configured to decode the second information using the second encoding technology.

7. The device according to claim 1, wherein the first circuit includes a first transmitter and a first receiver, the first transmitter is configured to decode the first information using the first encoding technique, the first receiver is configured to decode the second information using the second encoding technique, and The second circuit includes a second transmitter and a second receiver, wherein the second transmitter is configured to decode the second information using the second encoding technology, and the second receiver is configured to decode the first information using the first encoding technology.

8. The apparatus according to claim 1, further comprising: an amplitude detector for detecting pulses associated with the differential pulse code, Wherein the differential pulse code defines pulses having an amplitude greater than the differential carrier signal, such that the amplitude detector is able to detect the pulses in the presence of the differential carrier signal.

9. The device according to claim 8, further comprising: an envelope detector for detecting the differential carrier signal, Wherein a pulse length of the pulse is less than a detection time associated with the envelope detector, such that the envelope detector is able to detect the differential carrier signal in the presence of a pulse associated with the differential pulse code.

10. The apparatus of claim 9, wherein the second circuit comprises the amplitude detector and the envelope detector.

11. The apparatus of claim 1, wherein the data comprises first data encoded in the differential carrier signal and second data encoded in the differential pulse code.

12. The apparatus of claim 11 , wherein the first data comprises a switching signal for controlling a high-side power switch via a high-side driver circuit operating in the second voltage domain, and wherein the second data comprises configuration data for the high-side driver circuit operating in the second voltage domain.

13. The apparatus of claim 12 , wherein the first data is transmitted when the high-side power switch or the low-side power switch is in an on state, wherein the high-side power switch and the low-side power switch are arranged in a half-bridge configuration, and wherein the second data is transmitted during a dead time when both the high-side power switch and the low-side power switch are in an off state.

14. The device of claim 1, wherein the device comprises a circuit package comprising a molding compound formed around the first circuit, the second circuit, the one or more isolation elements, and the differential communication channel.

15. A method comprising: transmitting first data between a first circuit and a second circuit via a differential communication channel across a galvanic isolation barrier within a circuit package, wherein the first data is encoded via a first encoding technique comprising on-off shift keying (OOK) using a differential carrier signal; as well as Second data is transmitted between the first circuit and the second circuit via the differential communication channel within the circuit package across the galvanic isolation barrier, wherein the second data is encoded via a second encoding technique comprising differential pulse encoding.

16. The method according to claim 15, further comprising: transmitting the first data from the first circuit to the second circuit across the galvanic isolation barrier within the circuit package; as well as The second data is transmitted from the second circuit to the first circuit across the galvanic isolation barrier within the circuit package.

17. The method according to claim 15, further comprising: transmitting the first data from the first circuit to the second circuit across the galvanic isolation barrier within the circuit package; as well as The second data is transmitted from the first circuit to the second circuit across the galvanic isolation barrier within the circuit package.

18. The method of claim 15, wherein the second circuit comprises an amplitude detector for detecting pulses associated with the differential pulse code, The differential pulse code defines pulses having an amplitude greater than the differential carrier signal, such that the amplitude detector can detect the pulses in the presence of the differential carrier signal.

19. The method of claim 18, wherein the second circuit comprises an envelope detector for detecting the differential carrier signal, Wherein a pulse length of the pulse is less than a detection time associated with the envelope detector such that the envelope detector can detect the differential carrier signal in the presence of a pulse associated with the differential pulse code.

20. The method of claim 19, wherein the first data comprises a switching signal for controlling a high-side power switch via a high-side driver circuit operating in a second voltage domain, the second voltage domain being different from a first voltage domain associated with the first circuit, and wherein the second data comprises configuration data for the high-side driver circuit operating in the second voltage domain.

21. The method of claim 20, wherein the first data is transmitted when the high-side power switch or the low-side power switch is in an on state, wherein the high-side power switch and the low-side power switch are arranged in a half-bridge configuration, and wherein the second data is transmitted during a dead time when both the high-side power switch and the low-side power switch are in an off state.

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