Address allocation system, communication system, address allocation method and address identification method

Abstract

The invention provides an address distribution system, a communication system, an address distribution method and an address identification method. The address distribution system comprises an upper computer and a plurality of address signal generation modules, the plurality of address signal generation modules are electrically connected in sequence, the first address signal generation module is electrically connected with an upper computer, and each address signal generation module is electrically connected with corresponding electronic equipment; the upper computer is used for sending an address distribution signal to the first address signal generation module; and each address signal generation module is used for sending a new address distribution signal to the next address signal generation module and sending a target address signal to the corresponding electronic equipment according to the accessed address distribution signal, so that each electronic equipment determines a corresponding target communication address according to the accessed target address signal. Because only single interaction is needed between the upper computer and the address signal generation module, complex wiring and system control are not needed, and the related data interaction amount is small.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an address allocation system, a communication system, an address allocation method and an address identification method. Background Art

[0002] In industrial sites, when multiple electronic devices are involved, the communication between electronic devices and the communication between electronic devices and the host computer both require corresponding addresses to distinguish, so as to ensure the effectiveness of communication.

[0003] Each electronic device needs to complete the relevant functions of its setting location, including control, collection, feedback, etc. That is to say, the address of the electronic device corresponds to its setting location, so that its setting location can be determined based on its address later, which facilitates the implementation of relevant control.

[0004] In summary, the addresses of electronic devices cannot be fixed, but need to be assigned corresponding addresses according to the location of each electronic device after the system is built. However, some existing address allocation schemes require more complex system control and involve a large amount of data interaction. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides an address allocation system, a communication system, an address allocation method and an address identification method.

[0006] In a first aspect, in one embodiment, the present invention provides an address allocation system, the address allocation system comprising a host computer and a plurality of address signal generating modules;

[0007] The plurality of address signal generating modules are electrically connected in sequence, the first address signal generating module is also electrically connected to the host computer, and each address signal generating module is also respectively used to be electrically connected to a corresponding electronic device;

[0008] The host computer is used to send an address allocation signal to the first address signal generating module;

[0009] Each address signal generating module is used to send a new address allocation signal to the next address signal generating module and send a target address signal to the corresponding electronic device according to the received address allocation signal, so that each electronic device determines the corresponding target communication address according to the received target address signal.

[0010] In one embodiment, the address signal generating module includes a PWM generating unit;

[0011] Each PWM generating unit is used to send a new address allocation signal to the next PWM generating unit and send a target PWM signal to the corresponding electronic device according to the received address allocation signal, so that each electronic device can determine the corresponding target communication address according to the received target PWM signal; the target address signal includes the target PWM signal.

[0012] In one embodiment, the PWM generating unit includes a plurality of PWM output terminals;

[0013] The multiple PWM output terminals of each PWM generating unit are electrically connected to the multiple input terminals of the corresponding electronic device respectively;

[0014] Each PWM generating unit is used to send multiple sub-PWM signals to the corresponding electronic device, so that each electronic device determines the corresponding target communication address according to the multiple sub-PWM signals received; the target PWM signal includes multiple sub-PWM signals.

[0015] In one embodiment, the address signal generation module includes a PFM generation unit;

[0016] Each PFM generating unit is used to send a new address allocation signal to the next PFM generating unit and send a target PFM signal to the corresponding electronic device according to the received address allocation signal, so that each electronic device can determine the corresponding target communication address according to the received target PFM signal; the target address signal includes the target PFM signal.

[0017] In a second aspect, in one embodiment, the present invention provides a communication system, the communication system comprising a plurality of electronic devices and the address allocation system in any one of the above embodiments.

[0018] In a third aspect, in one embodiment, the present invention provides an address allocation method, which is applied to the communication system in any of the above embodiments; the address allocation method includes the following steps performed by a host computer:

[0019] Multiple data frames are obtained according to multiple target communication addresses allocated as needed;

[0020] According to the positional relationship of the address signal generating module corresponding to each target communication address, multiple data frames are spliced ​​to obtain an address allocation signal;

[0021] The obtained address allocation signal is sent to the first address signal generating module.

[0022] In one embodiment, the address allocation method further includes the following steps respectively performed by each address signal generating module:

[0023] Receive the address allocation signal sent by the host computer or the previous address signal generating module;

[0024] sending a target address signal to a corresponding electronic device according to a first data frame in the received address allocation signal;

[0025] A new address allocation signal is obtained according to other data frames except the first data frame in the received address allocation signal, and the obtained new address allocation signal is sent to the next address signal generating module.

[0026] In a fourth aspect, in one embodiment, the present invention provides an address allocation method, which is applied to the communication system in any of the above embodiments, wherein the address signal generating module includes a PWM generating unit; the address allocation method includes the following steps executed by a host computer:

[0027] According to the multiple target communication addresses allocated as needed, multiple target duty cycle parameters are obtained;

[0028] According to a plurality of target duty cycle parameters, an address allocation signal is obtained;

[0029] The obtained address allocation signal is sent to the first PWM generation unit.

[0030] In one embodiment, the address allocation method further includes the following steps respectively performed by each PWM generating unit:

[0031] Receive the address allocation signal sent by the host computer or the previous PWM generation unit;

[0032] According to the received address allocation signal, a corresponding target duty cycle parameter and a new address allocation signal are obtained;

[0033] According to the obtained target duty cycle parameter, a target PWM signal is sent to a corresponding electronic device; the target address signal includes the target PWM signal;

[0034] The obtained new address allocation signal is sent to the next address signal generating module.

[0035] In one embodiment, the PWM generating unit includes a plurality of PWM output terminals, and the plurality of PWM output terminals of each PWM generating unit are electrically connected to a plurality of input terminals of a corresponding electronic device respectively; and sending a target PWM signal to the corresponding electronic device according to the obtained target duty cycle parameter comprises:

[0036] According to the obtained multiple sub-duty cycle parameters, multiple sub-PWM signals are sent to the corresponding electronic device; the target duty cycle parameter includes multiple sub-duty cycle parameters, and the target PWM signal includes multiple sub-PWM signals.

[0037] In a fifth aspect, in one embodiment, the present invention provides an address recognition method, which is applied to the communication system in any of the above embodiments, wherein the address signal generating module includes a PWM generating unit; and the address allocation method includes the following steps respectively performed by each electronic device:

[0038] Receive a target PWM signal sent by a corresponding PWM generating unit;

[0039] Determine a corresponding target duty cycle result according to the received target PWM signal;

[0040] According to the determined target duty cycle result, the corresponding target communication address is determined.

[0041] In one embodiment, determining a corresponding target communication address according to the determined target duty cycle result includes:

[0042] Obtain a preset mapping table; the preset mapping table includes multiple sample duty cycle results and sample communication addresses corresponding to each sample duty cycle result;

[0043] According to the determined target duty cycle result, matching the corresponding sample duty cycle result in a preset mapping table;

[0044] The sample communication address corresponding to the matched sample duty cycle result is used as the corresponding target communication address.

[0045] In one embodiment, the PWM generating unit includes a plurality of PWM output terminals, and the plurality of PWM output terminals of each PWM generating unit are electrically connected to a plurality of input terminals of a corresponding electronic device respectively; and according to the determined target duty cycle result, determining the corresponding target communication address includes:

[0046] Determine a plurality of corresponding sub-communication addresses according to a plurality of sub-duty cycle results corresponding to a plurality of sub-PWM signals; the target PWM signal includes a plurality of sub-PWM signals, and the target duty cycle result includes a plurality of sub-duty cycle results;

[0047] According to the determined multiple sub-communication addresses, the corresponding target communication address is obtained.

[0048] Through the above-mentioned address allocation system, communication system, address allocation method and address identification method, a plurality of address signal generating modules electrically connected in sequence are set, so that the host computer only needs to send an address allocation signal to the first address signal generating module, and then the address allocation purpose for each address signal generating module can be achieved based on the signal transmission between two adjacent address signal generating modules, so that each address signal generating module can send a target address signal for determining the target communication address to the corresponding electronic device. Since only a single interaction is required between the host computer and the address signal generating module, no complicated wiring and system control are required, and the amount of data interaction involved is also small. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 A schematic diagram of the structure of a communication system in one embodiment of the present invention;

[0051] Figure 2 A schematic diagram of an address signal generating module including a PWM generating unit in one embodiment of the present invention;

[0052] Figure 3 A schematic diagram of a PWM generating unit including a plurality of PWM output terminals in one embodiment of the present invention;

[0053] Figure 4 A schematic diagram of changes in an address allocation signal during a transmission process in one embodiment of the present invention;

[0054] Figure 5 A schematic diagram of a host computer and an address signal generating module repeatedly sending an address allocation signal in one embodiment of the present invention;

[0055] Figure 6 FIG. 4 is a schematic diagram of a data frame corresponding to three sub-PWM signals in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0057] In the description of the present invention, it should be understood that the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In the present application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in the present application is not necessarily interpreted as being more preferred or more advantageous than other embodiments. In order to enable any person skilled in the art to implement and use the present invention, the following description is given. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present invention can be implemented without using these specific details. In other examples, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present invention obscure. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

[0058] First, as Figure 1 As shown, in one embodiment, the present invention provides an address allocation system, which includes a host computer and multiple address signal generating modules.

[0059] in, Figure 1 The three address signal generating modules shown in the figure are only examples. In other embodiments, more or fewer address signal generating modules may be included, which is not limited here.

[0060] Among them, a plurality of address signal generating modules are electrically connected in sequence, the first address signal generating module is also electrically connected to a host computer, and each address signal generating module is also used to be electrically connected to a corresponding electronic device.

[0061] Among them, the electronic device can be a corresponding terminal device in various industrial scenarios, for example, the electronic device can be a circuit breaker, etc.

[0062] The host computer is used to send an address allocation signal to the first address signal generating module.

[0063] The host computer can generate address allocation signals representing a corresponding number of target communication addresses according to the number of address signal generating modules.

[0064] Each address signal generating module is used to send a new address allocation signal to the next address signal generating module and send a target address signal to the corresponding electronic device according to the received address allocation signal, so that each electronic device determines the corresponding target communication address according to the received target address signal.

[0065] Among them, for the first address signal generating module, the address allocation signal it receives comes from the host computer; similarly, for the second address signal generating module, the address allocation signal it receives comes from the first address signal generating module, and for the third address signal generating module, the address allocation signal it receives comes from the second address signal generating module.

[0066] It should be noted that in Figure 1 In the embodiment, since there are only three address signal generating modules, the third address signal generating module is the last address signal generating module. After receiving the address allocation signal, it can still output a new address allocation signal to the next address signal generating module, but the address allocation signal it outputs cannot be received.

[0067] Among them, it can be understood that, since the address allocation signal sent by the host computer needs to enable all address signal generating modules to generate and send target address signals to the corresponding electronic devices, so that each connected electronic device can determine the corresponding target communication address, the address allocation signal sent by the host computer needs to include the characteristic parameters of all target communication addresses. Similarly, for each address signal generating module, since the address allocation signal sent by each address signal generating module needs to enable the subsequent address signal generating module to generate and send the target address signal to the corresponding electronic device, the address allocation signal sent by each address signal generating module at least needs to include the characteristic parameters of the target communication address corresponding to the subsequent address signal generating module.

[0068] Specifically, as an example, after the first address signal generating module receives the address allocation signal sent by the host computer, it obtains the characteristic parameters corresponding to itself, and then directly forwards the address allocation signal sent by the host computer to the second address signal generating module, so that each address signal generating module receives the same address allocation signal, that is, the address allocation signal sent by the host computer.

[0069] Through the above-mentioned address allocation system, multiple address signal generating modules electrically connected in sequence are set, so that the host computer only needs to send an address allocation signal to the first address signal generating module, and then the address allocation purpose for each address signal generating module can be achieved based on the signal transmission between two adjacent address signal generating modules, so that each address signal generating module can send a target address signal for determining the target communication address to the corresponding electronic device. Since only a single interaction is required between the host computer and the address signal generating module, no complicated wiring and system control are required, and the amount of data interaction involved is also small.

[0070] like Figure 2As shown, in one embodiment, the address signal generating module includes a PWM generating unit.

[0071] Among them, each PWM generating unit is used to send a new address allocation signal to the next PWM generating unit and send a target PWM signal to the corresponding electronic device according to the received address allocation signal, so that each electronic device can determine the corresponding target communication address according to the received target PWM signal; the target address signal includes the target PWM signal.

[0072] Among them, PWM refers to pulse width modulation, and the target PWM signal output by the PWM generation unit is a pulse signal based on the pulse width as a variable. The target PWM signals output by different PWM generation units are also different, which can be specifically reflected in the duty cycle representing the pulse width, that is, the duty cycles corresponding to different target PWM signals are different; in addition, it can also be reflected in the number of pulses, that is, the number of pulses corresponding to different target PWM signals is different.

[0073] The PWM generating unit may be specifically a PWM driving chip. In this case, the address allocation signal connected to the PWM driving chip is essentially a driving control signal, which is used to control all PWM driving chips to output different target PWM signals.

[0074] like Figure 3 As shown, in one embodiment, the PWM generating unit includes a plurality of PWM output terminals.

[0075] The multiple PWM output terminals of each PWM generating unit are electrically connected to the multiple input terminals of the corresponding electronic device. Figure 1 In the embodiment, each PWM generating unit has three PWM output terminals, and correspondingly, each electronic device has three input terminals. After each PWM generating unit is electrically connected to the corresponding electronic device, a PWM transmission channel C1, a PWM transmission channel C2 and a PWM transmission channel C3 are formed between the two.

[0076] Each PWM generating unit is used to send multiple sub-PWM signals to the corresponding electronic device, so that each electronic device determines the corresponding target communication address according to the multiple sub-PWM signals received; the target PWM signal includes multiple sub-PWM signals.

[0077] The constructed PWM transmission channel C1, PWM transmission channel C2 and PWM transmission channel C3 are respectively used to transmit a sub-PWM signal.

[0078] Among them, when the address signal connected to the electronic device is specifically a PWM signal, since the PWM signal can only reflect the difference in duty cycle and pulse number, and it is also necessary to ensure the error redundancy between each duty cycle or pulse number, when a single PWM signal is used, the address that can be mapped is limited, and it cannot cope with a large number of electronic devices. Taking the duty cycle as an example, the duty cycle ranges from 0% to 100% from small to large. If the error redundancy is set within 5%, it can only be divided into 0%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100% in one division method, which obviously cannot be applied to industrial scenarios with many electronic devices.

[0079] In this embodiment, when multiple sub-PWM signals are used, although each sub-PWM signal can map a limited number of addresses, after the multiple sub-PWM signals are combined, more addresses can be mapped and can be applied to industrial scenarios with more electronic devices.

[0080] In one embodiment, the address signal generating module includes a PFM generating unit.

[0081] Among them, each PFM generating unit is used to send a new address allocation signal to the next PFM generating unit and send a target PFM signal to the corresponding electronic device according to the accessed address allocation signal, so that each electronic device can determine the corresponding target communication address according to the accessed target PFM signal; the target address signal includes the target PFM signal.

[0082] Among them, PFM refers to pulse frequency modulation, and the target PFM signal output by the PFM generation unit is a pulse signal based on the pulse frequency as a variable. The target PFM signals output by different PFM generation units are also different, which can be specifically reflected in the pulse frequency, that is, the pulse frequencies corresponding to different target PFM signals are different; in addition, it can also be reflected in the number of pulses, that is, the pulse frequencies corresponding to different target PFM signals are different.

[0083] The PFM generating unit may specifically be a PFM driver chip. In this case, the address allocation signal connected to the PFM driver chip is essentially a drive control signal, which is used to control all PFM driver chips to output different target PFM signals.

[0084] Second, as Figure 1 As shown, in one embodiment, the present invention provides a communication system, which includes a plurality of electronic devices and the address allocation system in any one of the above embodiments.

[0085] Through the above communication system, multiple address signal generating modules electrically connected in sequence are set, so that the host computer only needs to send an address allocation signal to the first address signal generating module, and then the address allocation purpose for each address signal generating module can be achieved based on the signal transmission between two adjacent address signal generating modules, so that each address signal generating module can send a target address signal for determining the target communication address to the corresponding electronic device. Since only a single interaction is required between the host computer and the address signal generating module, no complicated wiring and system control are required, and the amount of data interaction involved is also small.

[0086] In a third aspect, in one embodiment, the present invention provides an address allocation method, which is applied to the communication system in any of the above embodiments; the address allocation method includes the following steps performed by a host computer:

[0087] Multiple data frames are obtained according to the multiple target communication addresses allocated as needed.

[0088] Each data frame corresponds to a target communication address, so that in the subsequent process, the address signal generating module can generate a corresponding target address signal based on the corresponding data frame, so that the corresponding electronic device can determine the corresponding target communication address.

[0089] According to the positional relationship of the address signal generating modules corresponding to each target communication address, multiple data frames are spliced ​​to obtain an address allocation signal.

[0090] Among them, Figure 1 and Figure 4 As shown, the address allocation signal D1 sent by the host computer includes data frame 1, data frame 2 and data frame 3. Data frame 1 corresponds to the first address signal generating module, which is used to enable the first address signal generating module to generate and send a target address signal to the corresponding electronic device. Data frame 2 corresponds to the second address signal generating module, which is used to enable the second address signal generating module to generate and send a target address signal to the corresponding electronic device. Data frame 3 corresponds to the third address signal generating module, which is used to enable the third address signal generating module to generate and send a target address signal to the corresponding electronic device.

[0091] Among them, based on the above statements, the first address signal generating module, the second address signal generating module and the third address signal generating module are electrically connected in sequence and arranged in sequence in terms of positional relationship, so data frame 1, data frame 2 and data frame 3 are also spliced ​​in sequence. In addition to data frame 1, data frame 2 and data frame 3, the address allocation signal sent by the upper computer can also include other data frames that meet the communication protocol or meet the data transmission requirements, which will not be repeated here.

[0092] The obtained address allocation signal is sent to the first address signal generating module.

[0093] Among them, since the address allocation signal sent by the host computer includes a plurality of data frames corresponding to each address signal generating module respectively, each address signal generating module can obtain the data frame corresponding to itself.

[0094] In one embodiment, the address allocation method further includes the following steps respectively performed by each address signal generating module:

[0095] Receive the address allocation signal sent by the host computer or the previous address signal generating module.

[0096] Among them, for the first address signal generating module, the address allocation signal it accesses comes from the host computer, and for the second and subsequent address signal generating modules, the address allocation signal they access comes from the previous address signal generating module.

[0097] According to the first data frame in the received address allocation signal, a target address signal is sent to the corresponding electronic device.

[0098] A new address allocation signal is obtained according to other data frames except the first data frame in the received address allocation signal, and the obtained new address allocation signal is sent to the next address signal generating module.

[0099] Among them, since the data frames corresponding to the address signal generating modules in the address allocation signal sent by the host computer are spliced ​​according to the positional relationship of the address signal generating modules, each address signal generating module can obtain the data frame corresponding to itself based on the positional relationship.

[0100] In this embodiment, when each address signal generating module sends a new address allocation signal to the next address signal generating module, in order to reduce the amount of data, it can only send the data frame corresponding to the subsequent address signal generating module. This method will make the address allocation signal accessed by each address signal generating module only have data frames corresponding to itself and the subsequent address signal generating module, and the data frames are spliced ​​according to the positional relationship of each address signal generating module, so that the first data frame in the address allocation signal accessed by each address signal generating module is the data frame corresponding to itself.

[0101] Specifically, Figure 1 and Figure 4As shown, the host computer sends an address allocation signal D1 including data frame 1, data frame 2 and data frame 3 to the first address signal generating module; the first address signal generating module obtains the current first data frame, i.e., data frame 1, and then sends an address allocation signal D2 including data frame 2 and data frame 3 to the second address signal generating module; the second address signal generating module obtains the current first data frame, i.e., data frame 2, and then sends an address allocation signal D3 including data frame 3 to the third address signal generating module; the third address signal generating module obtains the current first data frame, i.e., data frame 3.

[0102] like Figure 5 As shown, the host computer and each address signal generating module can complete the sending and receiving of the address allocation signal multiple times within a certain refresh cycle and reset interval to ensure that each address signal generating module can reliably obtain the data frame corresponding to itself.

[0103] In a fourth aspect, in one embodiment, the present invention provides an address allocation method, which is applied to the communication system in any of the above embodiments, wherein the address signal generating module includes a PWM generating unit; the address allocation method includes the following steps executed by a host computer:

[0104] According to the multiple target communication addresses allocated as needed, multiple target duty cycle parameters are obtained.

[0105] Among them, the above embodiment has mentioned that the address allocation signal sent by the host computer needs to include characteristic parameters representing all target communication addresses. In this embodiment, if the PWM signal is used as the transmission medium, the corresponding characteristic parameter can be the duty cycle, and each target duty cycle parameter corresponds to a target communication address.

[0106] An address allocation signal is obtained according to a plurality of target duty cycle parameters.

[0107] After obtaining a plurality of target duty cycle parameters, each target duty cycle parameter can be used as a data frame, and thus spliced ​​in the manner of the above embodiment to obtain an address allocation signal.

[0108] The obtained address allocation signal is sent to the first PWM generation unit.

[0109] In one embodiment, the address allocation method further includes the following steps respectively performed by each PWM generating unit:

[0110] Receive the address allocation signal sent by the host computer or the previous PWM generation unit.

[0111] Among them, for the first PWM generating unit, the address allocation signal it accesses is derived from the host computer, and for the second and subsequent PWM generating units, the address allocation signal they access is derived from the previous PWM generating unit.

[0112] According to the received address allocation signal, a corresponding target duty cycle parameter and a new address allocation signal are obtained.

[0113] After receiving the address allocation signal, the PWM generating unit can obtain the target duty cycle parameter corresponding to itself in the address allocation signal.

[0114] When a new address allocation signal is obtained, the received address allocation signal may be directly used as the new address allocation signal, or the target duty cycle parameter corresponding to the received address allocation signal may be removed from the received address allocation signal and used as the new address allocation signal.

[0115] According to the obtained target duty cycle parameter, a target PWM signal is sent to the corresponding electronic device; the target address signal includes the target PWM signal.

[0116] After the target duty cycle parameter is obtained, pulse width modulation can be performed accordingly to obtain the corresponding target PWM signal.

[0117] The obtained new address allocation signal is sent to the next address signal generating module.

[0118] In one embodiment, the PWM generating unit includes a plurality of PWM output terminals, and the plurality of PWM output terminals of each PWM generating unit are electrically connected to a plurality of input terminals of a corresponding electronic device respectively; and sending a target PWM signal to the corresponding electronic device according to the obtained target duty cycle parameter comprises:

[0119] According to the obtained multiple sub-duty cycle parameters, multiple sub-PWM signals are sent to the corresponding electronic device; the target duty cycle parameter includes multiple sub-duty cycle parameters, and the target PWM signal includes multiple sub-PWM signals.

[0120] Each sub-duty cycle parameter can be represented by two hexadecimal digits, and each sub-duty cycle parameter corresponds to 8 bits. Figure 3 As shown, three PWM transmission channels can be formed between the PWM generation unit and the electronic device, including PWM transmission channel C1, PWM transmission channel C2 and PWM transmission channel C3, so that each PWM generation unit needs to obtain three sub-duty cycle parameters to send three sub-PWM signals to the corresponding electronic device. Figure 6 As shown in , when there are three sub-duty cycle parameters, since each sub-duty cycle parameter corresponds to 8 bits, the data frame corresponding to the target duty cycle parameter is at least 24 bits. Figure 3and Figure 6 As shown, the host computer sends an address allocation signal D1 including the first 24 bits, the second 24 bits and the third 24 bits to the first PWM generating unit, the first PWM generating unit obtains the first 24 bits, and then sends the corresponding three sub-PWM signals to the corresponding electronic device according to the first 24 bits, and sends the address allocation signal D2 including the second 24 bits and the third 24 bits to the second PWM generating unit, the second PWM generating unit obtains the second 24 bits, and then sends the corresponding three sub-PWM signals to the corresponding electronic device according to the second 24 bits, and sends the address allocation signal D3 including the third 24 bits to the third PWM generating unit; the third PWM generating unit obtains the third 24 bits, and then sends the corresponding three sub-PWM signals to the corresponding electronic device according to the third 24 bits.

[0121] Specifically, if the target duty cycle parameter obtained by a PWM generation unit is 0x123456:

[0122] For PWM transmission channel C1, the sub-duty cycle parameter is 0x12, then the duty cycle of the sub-PWM signal is (0x12 / 0xFF)*100%=7.81%;

[0123] For PWM transmission channel C2, the sub-duty cycle parameter is 0x34, then the duty cycle of the sub-PWM signal is (0x34 / 0xFF)*100%=20.39%;

[0124] For PWM transmission channel C3, the sub-duty cycle parameter is 0x56, and the duty cycle of the sub-PWM signal is (0x56 / 0xFF)*100%=33.73%.

[0125] In a fifth aspect, in one embodiment, the present invention provides an address recognition method, which is applied to the communication system in any of the above embodiments, wherein the address signal generating module includes a PWM generating unit; and the address allocation method includes the following steps respectively performed by each electronic device:

[0126] Receive a target PWM signal sent by a corresponding PWM generating unit;

[0127] Determine a corresponding target duty cycle result according to the received target PWM signal;

[0128] According to the determined target duty cycle result, the corresponding target communication address is determined.

[0129] Among them, the PWM generating unit sends a target PWM signal to the electronic device according to the target duty cycle parameter. It can be understood that the target duty cycle parameter is a preset value before signal transmission. After the electronic device receives the target PWM signal, it determines the corresponding target duty cycle result. It can be understood that the target duty cycle result is an actual value after signal transmission. There may be differences between the preset value and the actual value, so two different expressions of target duty cycle parameter and target duty cycle result are adopted. In addition, with reference to the above embodiment, the target duty cycle parameter can be a hexadecimal number, and the target duty cycle result can specifically refer to the duty cycle percentage value of the PWM signal. The two may also be different in data structure, so two different expressions of target duty cycle parameter and target duty cycle result are adopted.

[0130] In one embodiment, the PWM generating unit includes a plurality of PWM output terminals, and the plurality of PWM output terminals of each PWM generating unit are electrically connected to a plurality of input terminals of a corresponding electronic device respectively; and according to the determined target duty cycle result, determining the corresponding target communication address includes:

[0131] According to the multiple sub-duty cycle results corresponding to the multiple sub-PWM signals, the corresponding multiple sub-communication addresses are determined; the target PWM signal includes the multiple sub-PWM signals, and the target duty cycle result includes the multiple sub-duty cycle results.

[0132] Among them, Figure 3 As shown, a PWM transmission channel C1, a PWM transmission channel C2 and a PWM transmission channel C3 are formed between the PWM generating unit and the electronic device.

[0133] The sub-communication address corresponding to the sub-PWM signal transmitted through the PWM transmission channel C1 can represent the device type of the electronic device; the sub-communication address corresponding to the sub-PWM signal transmitted through the PWM transmission channel C2 can represent the group address of the electronic device; the sub-communication address corresponding to the sub-PWM signal transmitted through the PWM transmission channel C3 can represent the address within the group of the electronic device.

[0134] Among them, taking the electronic device as a circuit breaker as an example, the device type can represent the cabinet where the circuit breaker is located, the group address can represent the group where the circuit breaker is located in a cabinet, and the group address can represent the specific position of the circuit breaker in a group.

[0135] The sub-duty cycle result may be a duty cycle percentage value. In this embodiment, the duty cycle percentage value may be calculated by a related calculation method to obtain a corresponding sub-communication address. For example, the duty cycle percentage value may be converted into a corresponding hexadecimal number, and the obtained hexadecimal number may be directly used as the sub-communication address.

[0136] According to the determined multiple sub-communication addresses, the corresponding target communication address is obtained.

[0137] Among them, taking the group address corresponding to the above-mentioned PWM transmission channel C2 and the intra-group address corresponding to the PWM transmission channel C3 as an example, if the obtained group address is 0x01 and the intra-group address is 0x0A, the combined target communication address is 0x1A. The specific combination method can be obtained by shifting and adding after conversion to binary numbers, which will not be repeated here.

[0138] In one embodiment, determining a corresponding target communication address according to the determined target duty cycle result includes:

[0139] Obtain a preset mapping table; the preset mapping table includes multiple sample duty cycle results and sample communication addresses corresponding to each sample duty cycle result.

[0140] Among them, Figure 3 As shown, when PWM transmission channel C1, PWM transmission channel C2 and PWM transmission channel C3 are included, the preset mapping table also specifically includes three sub-mapping tables. Taking device type, group address and intra-group address as examples, the preset mapping table may specifically include a device type sub-mapping table, a group address sub-mapping table and an intra-group address sub-mapping table.

[0141] According to the determined target duty cycle result, matching the corresponding sample duty cycle result in a preset mapping table;

[0142] The sample communication address corresponding to the matched sample duty cycle result is used as the corresponding target communication address.

[0143] Taking the device type sub-mapping table as an example, the corresponding specific mapping relationship can be as follows:

[0144]

[0145]

[0146] The duty cycle range determined according to the error range in the table includes the upper limit value itself but not the lower limit value itself, or includes the lower limit value itself but not the lower limit value itself. When the obtained sub-duty cycle result is 8%, the corresponding device type can be 0x01.

[0147] Taking the group address sub-mapping table as an example, the corresponding specific mapping relationship can be as follows:

[0148] Duty Cycle Error margin Upper limit duty cycle Lower duty cycle Group Address 10％ 5％ 15％ 5％ 0x01 20％ 10％ 25％ 15％ 0x02 30％ 10％ 35％ 25％ 0x03 40％ 10％ 45％ 35％ 0x04 50％ 10％ 55％ 45％ 0x05 60％ 10％ 65％ 55％ 0x06 70％ 10％ 75％ 65％ 0x07 80％ 10％ 85％ 75％ 0x08 90％ 10％ 95％ 85％ 0x09 100％ 10％ 100％ 95％ 0x0A

[0149] The duty cycle range determined according to the error range in the table includes the upper limit value itself but not the lower limit value itself, or includes the lower limit value itself but not the lower limit value itself. When the obtained sub-duty cycle result is 39%, the corresponding group address can be 0x04.

[0150] Taking the intra-group address sub-mapping table as an example, the corresponding specific mapping relationship can be as follows:

[0151] Duty Cycle Error margin Upper limit duty cycle Lower duty cycle Group address 10％ 5％ 15％ 5％ 0x01 20％ 10％ 25％ 15％ 0x02 30％ 10％ 35％ 25％ 0x03 40％ 10％ 45％ 35％ 0x04 50％ 10％ 55％ 45％ 0x05 60％ 10％ 65％ 55％ 0x06 70％ 10％ 75％ 65％ 0x07 80％ 10％ 85％ 75％ 0x08 90％ 10％ 95％ 85％ 0x09 100％ 10％ 100％ 95％ 0x0A

[0152] The duty cycle range determined according to the error range in the table includes the upper limit value itself but not the lower limit value itself, or includes the lower limit value itself but not the lower limit value itself. When the obtained sub-duty cycle result is 71%, the corresponding group address can be 0x07.

[0153] The above is a detailed introduction to an address allocation system, a communication system, an address allocation method and an address identification method provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0154] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. An address allocation system, characterized in that: The address allocation system includes a host computer and a plurality of address signal generating modules; The plurality of address signal generating modules are electrically connected in sequence, the first address signal generating module is also electrically connected to the host computer, and each of the address signal generating modules is also used to be electrically connected to a corresponding electronic device; The host computer is used to send an address allocation signal to the first address signal generating module; Each of the address signal generating modules is used to send a new address allocation signal to the next address signal generating module and send a target address signal to the corresponding electronic device according to the received address allocation signal, so that each electronic device determines the corresponding target communication address according to the received target address signal.

2. The address allocation system according to claim 1, characterized in that: The address signal generating module includes a PWM generating unit; Each of the PWM generating units is used to send a new address allocation signal to the next PWM generating unit and send a target PWM signal to the corresponding electronic device according to the received address allocation signal, so that each electronic device determines the corresponding target communication address according to the received target PWM signal; the target address signal includes the target PWM signal.

3. The address allocation system according to claim 2, characterized in that: The PWM generating unit comprises a plurality of PWM output terminals; The multiple PWM output terminals of each PWM generating unit are electrically connected to the multiple input terminals of the corresponding electronic device respectively; Each of the PWM generating units is used to send multiple sub-PWM signals to the corresponding electronic device, so that each electronic device determines the corresponding target communication address according to the multiple sub-PWM signals received; the target PWM signal includes multiple sub-PWM signals.

4. The address allocation system according to claim 1, characterized in that: The address signal generating module comprises a PFM generating unit; Each of the PFM generating units is used to send a new address allocation signal to the next PFM generating unit and send a target PFM signal to the corresponding electronic device according to the received address allocation signal, so that each electronic device can determine the corresponding target communication address according to the received target PFM signal; the target address signal includes the target PFM signal.

5. A communication system, characterized in that: The communication system comprises a plurality of electronic devices and the address allocation system according to any one of claims 1 to 4.

6. An address allocation method, characterized in that: The address allocation method is applied to the communication system according to claim 5; the address allocation method comprises the following steps performed by the host computer: Multiple data frames are obtained according to multiple target communication addresses allocated as needed; splicing the plurality of data frames according to the positional relationship of the address signal generating modules corresponding to each target communication address to obtain an address allocation signal; The obtained address allocation signal is sent to the first address signal generating module.

7. The address allocation method according to claim 6, characterized in that: The address allocation method further comprises the following steps respectively performed by each of the address signal generating modules: Receiving an address allocation signal sent by the host computer or a previous address signal generating module; sending a target address signal to a corresponding electronic device according to a first data frame in the received address allocation signal; A new address allocation signal is obtained according to other data frames in the received address allocation signal except the first data frame, and the obtained new address allocation signal is sent to the next address signal generating module.

8. An address allocation method, characterized in that: The address allocation method is applied to the communication system according to claim 5, the address signal generating module includes a PWM generating unit; the address allocation method includes the following steps performed by the host computer: According to the multiple target communication addresses allocated as needed, multiple target duty cycle parameters are obtained; Obtaining an address allocation signal according to the plurality of target duty cycle parameters; The obtained address allocation signal is sent to the first PWM generation unit.

9. The address allocation method according to claim 8, characterized in that: The address allocation method further includes the following steps respectively performed by each of the PWM generating units: Receiving an address allocation signal sent by the host computer or the previous PWM generation unit; According to the received address allocation signal, a corresponding target duty cycle parameter and a new address allocation signal are obtained; According to the obtained target duty cycle parameter, a target PWM signal is sent to the corresponding electronic device; The target address signal includes the target PWM signal; The obtained new address allocation signal is sent to the next address signal generating module.

10. The address allocation method according to claim 9, characterized in that: The PWM generating unit comprises a plurality of PWM output terminals, and the plurality of PWM output terminals of each PWM generating unit are electrically connected to a plurality of input terminals of a corresponding electronic device respectively; The step of sending a target PWM signal to a corresponding electronic device according to the obtained target duty cycle parameter comprises: Sending a plurality of sub-PWM signals to corresponding electronic devices according to the obtained plurality of sub-duty cycle parameters; The target duty cycle parameter includes a plurality of sub-duty cycle parameters, and the target PWM signal includes a plurality of sub-PWM signals.

11. An address recognition method, characterized in that: The address identification method is applied to the communication system according to claim 5, the address signal generating module includes a PWM generating unit; the address allocation method includes the following steps respectively performed by each of the electronic devices: Receive a target PWM signal sent by a corresponding PWM generating unit; Determine a corresponding target duty cycle result according to the received target PWM signal; According to the determined target duty cycle result, the corresponding target communication address is determined.

12. The address recognition method according to claim 11, characterized in that: Determining the corresponding target communication address according to the determined target duty cycle result includes: Obtaining a preset mapping table; the preset mapping table includes a plurality of sample duty cycle results and a sample communication address corresponding to each sample duty cycle result; According to the determined target duty cycle result, matching the corresponding sample duty cycle result in the preset mapping table; The sample communication address corresponding to the matched sample duty cycle result is used as the corresponding target communication address.

13. The address recognition method according to claim 11, characterized in that: The PWM generating unit includes a plurality of PWM output terminals, and the plurality of PWM output terminals of each PWM generating unit are electrically connected to a plurality of input terminals of a corresponding electronic device respectively; and determining the corresponding target communication address according to the determined target duty cycle result includes: Determine a plurality of corresponding sub-communication addresses according to a plurality of sub-duty cycle results corresponding to a plurality of sub-PWM signals; the target PWM signal includes a plurality of sub-PWM signals, and the target duty cycle result includes a plurality of sub-duty cycle results; According to the determined multiple sub-communication addresses, the corresponding target communication address is obtained.

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