Network-on-chip power management system and method

Abstract

The invention relates to a system for network-on-chip power management. The system comprises a primary network-on-chip, the primary network-on-chip comprising a plurality of components, each component having a power controller, characterized in that the system further comprises a secondary network-on-chip, the secondary network-on-chip comprising a secondary network-on-chip primary node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes being associated with the components of the primary network-on-chip, the power management module is used for performing power management on single and link components of a main on-chip network; and a power management unit connected to the secondary network-on-chip main node and configured to poll the state registers of the components of the main network-on-chip to obtain the power state of each component, obtain the routing information of the components of the main network-on-chip, and send a request to the secondary network-on-chip node, and the power supply controller is used for switching on or switching off a power supply of related components of the main network-on-chip. The invention also discloses a method for network-on-chip power management.

Description

Technical Field

[0001] The present invention generally relates to network-on-chip (NoC) power management. More specifically, the present invention relates to systems and methods for optimizing NoC power consumption. Background Art

[0002] NoC is a complex micro-architecture consisting of hardware components such as routers, node interfaces, slices, etc. The existence of these components leads to high power consumption. Therefore, managing the power supply of each component is crucial to optimize the power consumption of NoC.

[0003] Many efforts have been made to manage the power supply of NoCs. One of the efforts is discussed in the following references.

[0004] US9829962B2 discloses a method and system for executing power profile management instructions for NoC and / or System on Chip (SoC) using a hybrid combination of software and hardware, wherein the hardware elements of the NoC / SoC can run in parallel with other hardware elements of the NoC / SoC to generate and execute power profile management instructions for different segments or regions of the SoC / NoC, so that it can operate efficiently and safely. The system allows the user to abort an ongoing power state switching sequence. However, the power management block of the system can only manage the power of other blocks, but cannot autonomously manage its own power.

[0005] Therefore, there is still a need to provide a system and method involving the use of a dual parallel NoC topology, in which a lightweight secondary NoC acts as a secondary controller (co-pilot) to manage the power consumption of each component of the primary NoC. At the same time, the secondary NoC is also able to manage its own power without the need for a three-level NoC. In addition, it is also necessary to provide a system that can independently abort any power state entry based on the state of an internal trigger when there is incoming traffic that may potentially interrupt the flits in transit. The present invention provides such a system and method for NoC power management, which can manage NoC power very finely without sacrificing performance. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the present invention, a brief summary of the present invention is given below. This summary is not an extensive review of the present invention. Its only purpose is to present some concepts of the present invention in a simplified form as a prelude to a more detailed description presented later.

[0007] An object of the present invention is to provide a system for managing the power consumption of a primary NoC using a lightweight secondary NoC.

[0008] Another object of the present invention is to provide a system capable of managing the power consumption of each component of a main NoC.

[0009] Another object of the present invention is to provide a system including a lightweight slave NoC capable of power management of itself while power management of a master NoC is performed.

[0010] Another object of the present invention is to provide a method for NoC power management.

[0011] Accordingly, these objectives can be achieved by following the teachings of the present invention. The present invention relates to a system for NoC power management. The system includes a main NoC, the main NoC includes multiple components, each component has a power controller, characterized in that the system also includes a secondary NoC, the secondary NoC includes a secondary NoC master node and multiple secondary NoC nodes connected thereto, the multiple secondary NoC nodes are associated with the components of the main NoC, and are used to perform power management on single and link components of the main NoC; and a power management unit, the power management unit is connected to the secondary NoC master node, the power management unit is configured to poll the status registers of the components of the main NoC to obtain the power status of each component, obtain the routing information of the components of the main NoC, and send a request to the secondary NoC node to turn on or off the power of the relevant components of the main NoC through the power controller.

[0012] The present invention also relates to a computer-implemented method for NoC power management. The method comprises the following steps: receiving a power-off request from a power controller in a component of a primary NoC by a secondary NoC; performing an interrupt service check, checking a status register of an interrupt source to identify the interrupted component and the impact of the interrupt on a link component; accessing routing information of the primary NoC to obtain a traffic condition to determine the component of the primary NoC to be powered off; and, based on the interrupted component, the impact of the interrupt on the link component and the routing information, the secondary NoC powers off the component of the primary NoC, wherein the steps of performing the interrupt service check and accessing the routing information of the primary NoC are performed by a power management unit connected to the secondary NoC.

[0013] The foregoing and other objects, features, aspects and advantages of the present invention will be better understood by carefully reading the following detailed description provided in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to be able to understand in detail the above-listed features of the present invention, a more specific description of the present invention briefly outlined above may be made with reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present invention and are therefore not to be considered as limiting the scope of protection of the present invention, as the present invention may be applicable to other equivalent embodiments.

[0015] These and other features, benefits and advantages of the present invention will become apparent by reference to the following text and drawings, in which like reference numerals represent like structures throughout the several views, and in which:

[0016] Figure 1 is a schematic diagram showing a 1:1 relationship between the number of secondary NoC nodes and components of the primary NoC according to an embodiment of the present invention;

[0017] Figure 2 is an example showing a routing table and a secondary NoC node superimposed on a primary NoC, and the secondary NoC node is connected to the secondary NoC primary node;

[0018] Figure 3 is an example showing an inactive area in a routing table and a secondary NoC node superimposed on a primary NoC, and the secondary NoC node is connected to a secondary NoC primary node;

[0019] Figure 4 is an example showing an inactive area in a routing table and a secondary NoC node superimposed on a primary NoC, the routing table indicating a candidate for power failure, and the secondary NoC node connected to the secondary NoC primary node;

[0020] Figure 5 is a flow chart illustrating an interrupt service routine process for identifying a component to be powered off according to an embodiment of the present invention;

[0021] Figure 6 is an example showing a partial view of a link segment of a primary NoC;

[0022] Figure 7 is a diagram showing a power management module of a router;

[0023] Figure 8 is a schematic diagram showing a power controller and a pair of transmit link controllers and receive link controllers for a pair of adjacent routers;

[0024] Fig. 9 is a schematic diagram showing a power state finite state machine;

[0025] Fig.10 is a flowchart showing the process of powering on a router;

[0026] Fig.11 is a flow chart showing a process of powering off a router;

[0027] Fig.12 is a schematic diagram showing a link from a master node to a router;

[0028] Fig.13 is a schematic diagram showing a link from a node to a router;

[0029] Fig.14 is a schematic diagram showing a power management block of a home node;

[0030] Fig.15 is a schematic diagram illustrating a power failure abort scenario;

[0031] Fig.16 is an example showing power gating of a single power domain;

[0032] Fig.17 is an example showing power gating of a dual power domain NoC according to a first embodiment of the present invention; and

[0033] Fig.18 FIG. 2 is an example showing power gating of a dual-power domain NoC according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0034] As required, detailed embodiments of the present invention are disclosed herein; however, it should be understood that the disclosed embodiments are only exemplary embodiments of the present invention that can be implemented in various forms. Therefore, the specific structural and functional details disclosed herein should not be interpreted as limiting, but only as the basis of the claims. It should be understood that the drawings and their detailed description are not intended to limit the present invention to the specific forms disclosed, on the contrary, the present invention will cover all modifications, equivalents and substitutes within the scope of the present invention defined by the appended claims. As used in this application, the word "may" is used in a permissive sense (i.e., it means that it is possible), rather than a mandatory sense (i.e., it means that it must). Similarly, the words "include", "including" and "includes" mean including but not limited to. In addition, unless otherwise specified, the words "a" or "an" mean "at least one", and the word "some" means one or more. When abbreviations or technical terms are used, they represent the generally accepted meanings known in the technical field.

[0035] The present invention is described below by various embodiments with reference to the accompanying drawings, wherein the reference numerals used in the accompanying drawings correspond to similar elements throughout the description. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Specifically, embodiments are provided in order to make the present invention thoroughly and completely disclosed, and to fully convey the scope of the present invention to those skilled in the art. In the following detailed description, values ​​and ranges are provided for various aspects of the described embodiments. These values ​​and ranges are only considered as examples and are not intended to limit the scope of the claims. In addition, many materials are considered to be applicable to various aspects of the embodiments. These materials will be considered as exemplary and are not intended to limit the scope of the present invention.

[0036] The present invention relates to a system (10) for NoC power management. The system (10) includes a main NoC (20), the main NoC (20) includes a plurality of components (22), each component (22) having a power controller, characterized in that the system (10) also includes a secondary NoC (30), the secondary NoC (30) includes a secondary NoC master node (34) and a plurality of secondary NoC nodes (32) connected thereto, the plurality of secondary NoC nodes (32) being associated with the components (22) of the main NoC (20) and used to perform power management on individual and linked components (22) of the main NoC (20); and a power management unit (40) connected to the secondary NoC master node (34), configured to poll the status registers of the components (22) of the main NoC (20) to obtain the power status of each component (22), obtain the routing information of the components (22) of the main NoC (20), and send a request to the secondary NoC node (32) to turn on or off the power of the relevant components (22) of the main NoC (20) through the power controller.

[0037] The present invention also relates to a computer-implemented method for NoC power management. The method comprises the following steps: receiving a power-off request from a power controller in a component (22) of a main NoC (20) by a secondary NoC (30); performing an interrupt service check, checking a status register of an interrupt source to identify an interrupted component (22) and the effect of the interrupt on a link component (22); accessing routing information of the main NoC (20) to obtain a traffic condition to determine a component (22) of the main NoC (20) to be powered off; and, based on the interrupted component (22), the effect of the interrupt on the link component (22) and the routing information, the secondary NoC (30) powers off the component (22) of the main NoC (20), wherein the steps of performing the interrupt service check and accessing the routing information of the main NoC (20) are performed by a power management unit (40) connected to the secondary NoC (30).

[0038] The present invention will now be described in more detail with reference to the accompanying drawings.

[0039] Figure 1 1 is a schematic diagram showing a system (10) according to an embodiment of the present invention. It shows a 1:1 ratio of secondary NoC nodes (32) to components (22) of a primary NoC (20), specifically, one secondary NoC node (32) is associated with one component (22) of the primary NoC (20). Implementations using different ratios such as N:1 are not excluded, where N is a positive integer. One secondary NoC node (32) can manage the power supply of N components (22) of the primary NoC (20) associated with this secondary NoC node (32).

[0040] According to an embodiment of the present invention, the master NoC (20) is responsible for conventional packet routing between traffic sources and destinations within the system (10). The master NoC (20) typically has very high bandwidth capacity in the GBps range.

[0041] According to one embodiment of the present invention, the secondary NoC (30) is a lightweight NoC that coexists in parallel with the main NoC (20), but it does not necessarily adopt the same topology as the main NoC. Compared with the main NoC (20), the secondary NoC (30) has a relatively low bandwidth in the range of hundreds of Mbps, but its bandwidth is scalable to meet the bandwidth requirements required by the power management unit (40) to handle power management of main NoCs (20) of different sizes. It is worth noting that the secondary NoC (30) is usually located on a normally open domain. However, the secondary NoC (30) can also perform power gating in a self-management mode. In other words, the secondary NoC (30) has the ability to self-manage its own power under the control of the power management unit (40). The always-on feature allows the secondary NoC (30) to interoperate with the power management unit (40) to act as a secondary controller to monitor the power status of the primary NoC (20) and respond quickly through the power controller of the component (22) to changing conditions that affect which components (22) of the primary NoC (20) need to be turned on and which components can be turned off in a timely manner.

[0042] According to an embodiment of the present invention, the main NoC is a static route. In order to implement static routing, the NoC software will establish a routing map, a routing table or a routing activity table. The routing table includes routing information, which describes the components that the data packet needs to travel through from each source node interface to each destination node interface. Figure 2 1 is a schematic diagram showing an example of a routing table and a secondary NoC node (32) superimposed on a component (22) of a primary NoC (20), and the secondary NoC node (32) is connected to a secondary NoC primary node (34). An integer "1" in the routing table indicates a component (22), such as a router, that a data packet from a specified primary source ID node interface (NI) will pass through on the way to a specified destination ID node interface within the primary NoC (20).

[0043] According to one embodiment of the present invention, NoC power management is handled by firmware running on processing resources and storage resources. Processing resources include, but are not limited to, a power management unit (40), a central processing unit, or a microcontroller. Storage resources include static random access memory or dynamic random access memory with sufficient speed and storage capacity to monitor and control the power supply of the NoC. In the present invention, the key to managing power consumption is to timely understand which component (22) of the main NoC (20) and when the specific component (22) needs to be powered off and on. Therefore, the firmware running on the power management unit (40) must know the activity and pending traffic status of each source node interface and destination node interface, as well as the packet transmission flow within the main NoC (20).

[0044] Figure 3 1 is a schematic diagram showing an example of an inactive region in a routing table and a secondary NoC node (32) superimposed on a component (22) of a primary NoC (20), and the secondary NoC node (32) is connected to a secondary NoC primary node (34). When there is no active and pending traffic from or to the node interface NI0, the inactive region will be demarcated in the corresponding routing table by marking the relevant row as inactive. In addition, the component (22) in the primary NoC (20) represented by a column without any active traffic and any pending traffic, the particular component (22) will be considered as a candidate for powering off. Figure 4 As shown, router R0 may be powered off. For each component (22) identified as a candidate for power off, the power management unit (40) will execute a power off entry sequence.

[0045] According to an embodiment of the present invention, the components (22) of the master NoC (20) include routers, node interfaces, slices, and coherent hubs. More specifically, the node interfaces are master nodes and slave nodes, the slices are non-flow control slices or flow control slices, and the coherent hubs are home nodes. Each component (22) includes a power controller, which is always on and timed. This enables the power controller to continuously monitor and respond to power-off and power-on events of the component (22). The power controller works in conjunction with a pair of link controllers, which include a transmitter (TX) link controller and a receiver (RX) link controller, which are always on to monitor the link power status. When the power-off condition is ripe, the power controller of the component (22) will send an interrupt message to the power management unit (40) via the secondary NoC (30) to indicate that the component (22) is a power-off candidate. Alternatively, the power management unit (40) will be responsible for actively polling the status register of the component (22) of the master NoC (20) to obtain its power status.

[0046] According to an embodiment of the present invention, the power management unit (40) will react to the interrupt message or check the status register of the interrupt source by executing an interrupt service routine to poll the low power component (22) of the main NoC (20). The power management unit (40) will identify the interrupted component (22) of the main NoC (20) and the impact of the interrupt component (22) on the active area and the inactive area of ​​the routing table. This process is as follows Figure 5 As shown, it is designed to identify the component (22) to be powered off in the primary NoC (20). Given that the power management unit (40) maintains the routing activity table of the primary NoC (20), and it also tracks which traffic source-destination pairs have pending transactions; therefore, it has enough information to decide which component (22) of the primary NoC (20) can be powered off. If the component (22) can be powered off, the power management unit (40) will program the associated secondary NoC node (32) to power off the component (22) of the primary NoC (20) associated with the secondary NoC node (32). When a wake-up event is detected, the affected component (22) of the primary NoC (20) will send an interrupt message to the power management unit (40) via the secondary NoC (30). The power management unit (40) will then start the process of powering on the affected component (22) of the primary NoC (20). In addition, the power management unit (40) will also power on any components (22) of the primary NoC (20) along the path of the source packet to its destination via the secondary NoC nodes (32) associated with the components (22). If the destination node or its slaves are currently powered off, the power management unit (40) will also wake it up via the secondary NoC nodes (32) associated with the destination node or its slaves. The power management unit (40) will update the routing table accordingly to mark the newly powered on component (22) as active.

[0047] According to an embodiment of the present invention, the secondary NoC (30) is able to self-manage its own power supply without the need for assistance from the lighter-weight tertiary NoC. This is because the secondary NoC node (32) corresponds to the component (22) of the primary NoC (20) to be powered on and off at the same time. In other words, the power on and off of any component (22) of the primary NoC (20) will trigger the power on and off of its corresponding secondary NoC node (32).

[0048] According to an embodiment of the present invention, if the component (22) to be powered off suddenly receives traffic before acknowledging the power off request from the power management unit (40), the power management unit (40) allows the component (22) of the main NoC (20) to abort the power off request. The abort option is useful because the observe-decision-request point on the power management unit (40) may lag behind events that occur asynchronously in real time within and around the NoC that may reverse the power off decision. In addition, the abort option also helps avoid performance loss caused by erroneous power off.

[0049] Hereinafter, examples of the present invention will be provided to explain in more detail. Advantages of the present invention can be more easily understood and put into practice from these embodiments. However, it should be understood that the following embodiments are not intended to limit the scope of the present invention in any way.

[0050] Example

[0051] Figure 6 is a schematic diagram showing a partial view of a link segment of a primary NoC (20), including a master node, a router, a non-flow control slice, and a slave node. Examples 1 to 7 will describe the underlying details of how a hardware component (22) responds to a system-level command. This can be implemented by the firmware of the system (10) through the secondary NoC, or by the hardware of the system (10) through a sideband signal that directly controls the system-level activation request. In addition, Examples 8 to 10 will describe the hardware-firmware interaction flow when performing clock gating of a component (22) that is identified as being powered off.

[0052] Example 1: Router Power Management

[0053] Figure 7 is a schematic diagram illustrating the power management module of a router. Two types of functional modules, including the power controller and the TX / RX link controller, are kept always on to quickly respond to power-off and power-on events. The power supply of each router in the main NoC (20) is controlled by the following controllers:

[0054] (i) Power Controller (one per channel, shared among all link interfaces); and

[0055] (ii) TX / RX link controller (one pair per interface and channel).

[0056] Each router supports power management using the following signals:

[0057] (i) SYS_ACTREQ is a system-level (SYStem) activity (ACTive) request (REQuest). The system hardware driven by a dedicated signal or through software by the secondary NoC (30) asserts this signal when it wants to enter the running state, and deasserts this signal to enter the stop state.

[0058] (ii) SYS_ACTACK is a system-level activity acknowledgement (ACKnowledge). Whenever the router is in operation, it will enable this signal in the hardware and / or software of the system (10).

[0059] (iii) SYS_ACTNACK is a system-level negative acknowledgement. Whenever the router wants to abort a power-off request, it will enable this signal in the hardware and / or software of the system (10).

[0060] (iv) SACTIVE is a pending activity signal indicating that there is an ongoing transaction. Each link has one such signal. The transmitter asserts this signal whenever there is a pending flow control element (flit).

[0061] It is important to note that all of these signals must be positive polarity, meaning active high (1) when asserted and idle or inactive low (0) when deasserted, so they will signal inactivity whenever they are physically powered off or power gated.

[0062] Router power-on process

[0063] Figure 8 is a schematic diagram showing the power controller and TX / RX link controllers of an adjacent router pair. Fig. 9 1 is a schematic diagram illustrating a power state finite-state machine (FSM). When the reset is completed, the power state FSM is in a stopped state. The following describes the process of the power management unit (40) supplying power to the router 0 through the secondary NoC master node (34) and the secondary NoC node (32) associated with the router 0:

[0064] 1. The power management unit (40) supplies power to the router 0 (physical power-on).

[0065] 2. The power management unit (40) waits for the power supply of router 0 to stabilize.

[0066] 3. The power management unit (40) asserts SYS_ACTREQ_0 to request that router 0 be powered on (logical power on).

[0067] 4. Router 0 removes clock gating.

[0068] 5. Router 0 cancels its reset.

[0069] 6. Router 0 makes the ACTREQ_0 signal effective for Router 1.

[0070] 7. Router 1 performs the following steps:

[0071] (a) If Router 1 is ready to transition to the Run state. The ready criterion means that the SYS_ACTREQ signal is asserted, but the SYS_ACTACK signal is not currently asserted (but is in the process of transitioning to final assertion). Make the signals ACTACK_0 and ACTREQ_1 asserted for Router 0.

[0072] (b) If Router 1 is in the Stop state, Router 1 will keep ACTACK_0 and ACTREQ_1 invalid. When Router 1 is ready to transition to the Run state, continue with step (a).

[0073] 8. When Router 0 recognizes that Router 1 has validated ACTREQ_1, Router 0 will validate the ACTACK_1 signal to Router 1.

[0074] 9. When ACTACK_0, ACTACK_1 and ACTACK_<all other link interfaces of Router 0> are valid, Router 0 will make SYS_ACTACK_0 valid to indicate to the power management unit (40) that Router 0 is in operation.

[0075] Fig.10 It is a flowchart that illustrates the process of powering on a router.

[0076] Router power off process

[0077] Reference Figure 8 , the following describes the process of the power management unit (40) powering off the router 0 through the secondary NoC master node (34) and the secondary NoC node (32) associated with the router 0:

[0078] 1. The power management unit (40) deactivates the SYS_ACTREQ_0 signal to request that Router 0 be powered off.

[0079] 2. (a) If there are no pending flits, Router 0 fails ACTREQ_0 to Router 1 and returns all credits on its TX link. Continue to step 3.

[0080] (b) If there is a pending flit, then Router 0 will tell the Power Management Unit (40) to abort the power off request. Router 0 will assert SYS_ACTNACK_0 and wait until the Power Management Unit (40) deasserts the SYS_ACTREQ_0 signal (backoff). Router 0 will then deassert the SYS_ACTNACK_0 signal. For the abort case, the flow ends here.

[0081] 3. Neighboring router 1 or node detects the failure of ACTREQ_0 and reacts in the following ways:

[0082] (a) After receiving all credits, invalidate ACTACK_0 to Router 0.

[0083] (b) Make ACTREQ_1 invalid for Router 0 and return all its credits to Router 0.

[0084] 4. Router 0 fails ACTACK_1 when it receives all link credits from Router 1 and recognizes that ACTREQ_1 in Router 1 has failed.

[0085] 5. When Router 0 detects that ACTACK_0 and ACTACK_1 of all its link interfaces have been deasserted, it will deassert SYS_ACTACK_0 to the power management unit (40) to indicate that Router 0 is in a stopped state. At this point, the clocks and power supplies are ready for gating, except for the power controller and TX / RX link controller which are always open to control wakeup (power on) and sleep (power off) events.

[0086] Fig.11 is a flow chart illustrating the process of powering off a router.

[0087] Example 2: Master Node Power Management

[0088] The power supply of each master node in the master NoC (20) is controlled by the following controller:

[0089] (i) Power Controller (one per channel, shared among all link interfaces); and

[0090] (ii) TX / RX link controller (one pair per interface and channel).

[0091] Master node power-on process

[0092] Fig.12 is a schematic diagram showing a link from the master node to the router 0. The following describes the process of the power management unit (40) powering on the master node through the secondary NoC master node (34) and the secondary NoC node (32) associated with the master node:

[0093] 1. The power management unit (40) supplies power to the master node (physical power-on).

[0094] 2. The power management unit (40) waits for the power supply of the master node to stabilize.

[0095] 3. The power management unit (40) asserts SYS_ACTREQ_0 to request the master node to power on (logical power on).

[0096] 4. The master node releases clock gating.

[0097] 5. The master node cancels its reset.

[0098] 6. The master node makes ACTREQ_0 effective for neighbor router 0.

[0099] 7. Router 0 performs the following steps:

[0100] (a) If Router 0 is already in the running state (i.e., both SYS_ACTREQ_1 and SYS_ACTACK_1 of Router 0 are valid, or is ready to transition to the running state (i.e., SYS_ACTREQ_1 is valid, but SYS_ACTACK_1 is not valid but is in the process of transitioning to final validity)), it will make ACTACK_0 valid for the master node.

[0101] (b) If Router 0 is not in the running state, it will:

[0102] (i) Keep ACTACK_0 ineffective for the master node.

[0103] (ii) Keep ACTREQ_1 ineffective for the master node.

[0104] (iii) Continue with step (a) only when Router 0 is ready to transition to the operational state.

[0105] (c) When the master node recognizes that ACTREQ_1 is valid, it will make ACTACK_1 valid to neighbor router 0.

[0106] (d) When both ACTACK_0 and ACTACK_1 have been asserted, the master node will assert SYS_ACTACK to the power management unit (40) to indicate that the master node is now in operation, which means that the power-on process has been completed and the master node can start receiving data packets.

[0107] Master node power off process

[0108] If the master node has a coherent interface, the power management unit (40) must first disable system coherency via the SYSCOREQ / SYSCOACK flow. This is to prevent snoops from the home node or coherent hub that could interrupt the power down process. Fig.12 The following describes the process of the power management unit (40) powering off the master node through the secondary NoC master node (34) and the secondary NoC node (32) associated with the master node:

[0109] 1. The power management unit (40) deactivates SYS_ACTREQ_0 to request the master node to start the power-off process.

[0110] 2. (a) If there are no pending requests, responses, or flits, the master fails ACTREQ_0 to Router 0 and returns all credits on the TX link. Continue to step 3.

[0111] (b) If there are pending requests, responses, and flits, the master node will tell the power management unit (40) to abort the power off request. The master node will validate SYS_ACTNACK_0 and wait until the power management unit (40) SYS_ACTREQ_0 fails (rollback). The master node will then fail SYS_ACTNACK_0. For the abort case, the process ends here.

[0112] 3. Router 0 detects that ACTREQ_0 has failed, and then:

[0113] (a) Wait for all credits to be returned from the master before failing ACTACK_0 to the master.

[0114] (b) Router 0 will also fail ACTREQ_1 and return all credits to the master node.

[0115] 4. The master detects the failure of ACTREQ_1 and then waits for Router 0 to return all its credits before failing ACTACK_1 to Router 0.

[0116] 5. When the master detects that both ACTACK_0 and ACTACK_1 are invalid, it will invalidate (clear) SYS_ACTACK to the power management unit (40). This indicates that the logical power-off process has been completed and the master is in a stopped state. At this point, the master's clock and power are ready for gating, except for the power controller and TX / RX link controller, which are always in a normally open state to monitor wake-up and sleep events.

[0117] Example 3: Slave Node Power Management

[0118] The power supply of each slave node in the master NoC (20) is controlled by the following controller:

[0119] (i) Power Controller (one per channel, shared among all link interfaces); and

[0120] (ii) TX / RX link controller (one pair per interface and channel).

[0121] Power-on process of slave node

[0122] Fig.13is a schematic diagram showing a link from a slave node to router 0. The following describes the process of the power management unit (40) powering on a slave node through the secondary NoC master node (34) and the secondary NoC node (32) associated with the slave node:

[0123] 1. The power management unit (40) supplies power to the slave node (physical power-on).

[0124] 2. The power management unit (40) waits for the power supply of the slave node to stabilize.

[0125] 3. The power management unit (40) asserts SYS_ACTREQ_0 to request the slave node to power on (logical power on).

[0126] 4. Ungate the clock from the node.

[0127] 5. The slave node cancels its reset.

[0128] 6. The slave node makes ACTREQ_0 effective to neighboring router 0.

[0129] 7. Router 0 performs the following steps:

[0130] (a) If Router 0 is already in the operational state (i.e., both SYS_ACTREQ_1 and SYS_ACTACK_1 of Router 0 are valid) or is ready to transition to the operational state (i.e., SYS_ACTREQ_1 is valid, but SYS_ACTACK_1 is not valid but is in the process of finally transitioning to validity), it will make ACTACK_0 valid for the slave node.

[0131] (b) If Router 0 is not in the running state, it will:

[0132] (i) Keep ACTACK_0 invalid for the slave node.

[0133] (ii) Keep ACTREQ_1 disabled for slave nodes.

[0134] (iii) Step (a) is performed only when Router 0 is ready to transition to the operational state.

[0135] 8. When the slave node recognizes that ACTREQ_1 is valid, it will make ACTACK_1 valid to Router 0.

[0136] 9. When both ACTACK_0 and ACTACK_1 are valid, the slave node will make SYS_ACTACK valid to the power management unit (40) to indicate that the slave node is now in operation, that is, the power-on process has been completed and the slave node can start receiving data packets.

[0137] Power off process from node

[0138] Before the power management unit (40) starts the process of powering off the slave node, it must first ensure that all master nodes that can access the current slave node must be in a stopped state. This prerequisite measure is necessary to prevent new transactions from being sent to the current slave node when the current slave node is powered off. Fig.13 The following describes the process of the power management unit (40) powering off the slave node through the secondary NoC master node (34) and the secondary NoC node (32) associated with the slave node:

[0139] 1. The power management unit (40) deasserts SYS_ACTREQ_0 to request the slave node to start the power-off process.

[0140] 2. If there are no pending requests, responses, and FLITs, the slave node fails ACTREQ_0 to Router 0 and returns all credits on the TX link.

[0141] 3. Router 0 detects that ACTREQ_0 has failed, and then:

[0142] (a) Wait for all credits to be returned from the slave before failing ACTACK_0 to the slave.

[0143] (b) Router 0 will also fail ACTREQ_1 and return all credits to the slave nodes.

[0144] 4. The slave detects that ACTREQ_1 fails, and then waits for Router 0 to return all its credits before failing ACTACK_1 to Router 0.

[0145] 5. When the slave detects that both ACTACK_0 and ACTACK_1 are invalid, it will invalidate (clear) SYS_ACTACK to the power management unit (40). This indicates that the logical power-off process has been completed and the slave is in a stopped state. At this point, the slave's clock and power are ready for gating, except for the power controller and TX / RX link controller, which are in a normally open state to monitor sleep and wake-up events.

[0146] Example 4: Slice Power Management

[0147] A slice is a component (22) in the main NoC (20) that acts as a repeater on very long links. There are two types of slices, namely non-flow controlled slices and flow controlled slices. A non-flow controlled slice does not require any dedicated power management blocks because it will share the same power domain as the component (22) on one of its two adjacent links. A non-flow controlled slice can be powered on before or at the same time as any of its adjacent devices. Although it may be powered on later, doing so will result in a meaningless increase in logic power-on latency. At the same time, from a power management perspective, a flow controlled slice looks exactly like a router. Therefore, the power-on and power-off process is exactly the same as the router power-on and power-off process described in Example 1.

[0148] Example 5: Home Node Power Management

[0149] Home nodes or coherence hubs are components that manage coherence within a coherent NOC (22). They are responsible for performing snooping and other cache maintenance operations. The power supply of each home node is controlled by the following controllers:

[0150] (i) a power controller controls the power state of the home node;

[0151] (ii) requesting the Node (RN) link controller to control the power state of the master node or RN link interface; and

[0152] (iii) The Slave Node (SN) Link Controller controls the power state of the slave node or SN link interface.

[0153] Home Node Power-On Process

[0154] Fig.14 : is a schematic diagram showing a power management block of a home node. The following describes the process of the power management unit (40) supplying power to the home node through the secondary NoC master node (34) and the secondary NoC node (32) associated with the home node:

[0155] 1. The power management unit (40) supplies power to the home node (physical power-on).

[0156] 2. The power management unit (40) waits for the power supply of the home node to stabilize.

[0157] 3. The power management unit (40) asserts SYS_ACTREQ_0 to request the home node to power on (logical power on).

[0158] 4. The home node releases clock gating.

[0159] 5. The home node cancels its reset.

[0160] 6. The home node validates ACTREQ_0 and ACTREQ_2 on its neighbor link interfaces, where the home node links act like RN and SN respectively.

[0161] 7. On the adjacent link interface, the home node manages the link like the RN:

[0162] (a) If the adjacent link interface is ready to transition to the operational state. The ready criterion means that the adjacent component's (22) SYS_ACTREQ is asserted, but the SYS_ACTACK is not currently asserted (but the transition process to eventually transition to the assertion has begun). The adjacent device asserts ACTACK_0 and ACTREQ_1 to the home node.

[0163] (b) If the adjacent link is not in the operational state and is not ready to enter the operational state, it shall:

[0164] (i) Maintain the failure of ACTACK_0 to the home node.

[0165] (ii) Keep ACTREQ_1 disabled for the home node.

[0166] (iii) If the adjacent link interface is ready to transition to the operational state, proceed to step (a).

[0167] 8. On the adjacent link interface, the home node manages the link like the SN:

[0168] (a) If the neighbor link interface is ready to transition to the operational state. The readiness criterion means that the neighbor component's (22) SYS_ACTREQ is asserted, but the SYS_ACTACK is not currently asserted (but the transition process to eventually transition to the assertion has begun). The neighbor device asserts ACTACK_2 and ACTREQ_3 to the home node.

[0169] (b) If the adjacent link is not in the operational state and is not ready to enter the operational state, it shall:

[0170] (i) keep ACTACK_2 disabled to the home node; and

[0171] (ii) Maintain the failure of ACTREQ_3 to the home node.

[0172] (iii) If the adjacent link interface is ready to transition to the operational state, proceed to step (a).

[0173] 9. When the ACTACK_0, ACTACK_1, ACTACK_2 and ACTACK_3 signals are all asserted, SYS_ACTACK is asserted to the power management unit (40) to indicate that the home node is now in operation, i.e., the power-on process has been completed and the home node can start receiving data packets.

[0174] Home Node Power Off Process

[0175] Before powering off the home node, the power management unit (40) must ensure that all master nodes that can send transactions to the current home node must be in a stopped state, indicating that there are no pending requests and pending responses in the home node. Fig.14 The following describes the process of the power management unit (40) powering off the home node through the secondary NoC master node (34) and the secondary NoC node (32) associated with the home node:

[0176] 1. The power management unit (40) deactivates SYS_ACTREQ_0 to request the master node to start the power-off process.

[0177] 2. If there are no pending requests, responses, and flits, the home node invalidates ACTREQ_0 and ACTREQ_2 and returns all credits on its TX link.

[0178] 3. The adjacent link interface detects that ACTREQ_0 has failed, then:

[0179] (a) Wait for all credits to be returned from the home node before failing ACTACK_0 to the home node.

[0180] (b) It will also invalidate ACTREQ_1 and return all credits to the home node.

[0181] 4. The adjacent link interface detects that REQACT_2 fails, then:

[0182] (a) Wait for all credits to be returned from the home node before failing ACTACK_2 to the home node.

[0183] (b) It will also invalidate ACTREQ_3 and return all credits to the home node.

[0184] 5. When ACTACK_0, ACTACK_1, ACTACK_2 and ACTACK_3 are all invalid, the home node will invalidate (clear) SYS_ACTACK to the power management unit (40). This indicates that the logical power-off process has been completed and the home node is in a stopped state. At this point, the clock and power supply of the home node are ready for gating, except for the power controller and link controller that are always in a normally open state to monitor wake-up and sleep events.

[0185] Example 6: Power-off abort mechanism

[0186] Fig.15 is a schematic diagram showing a power-off abort scenario with a negative acknowledgement (NACK) option, in which the power management unit (40) is able to abort the power-off request in an immediate manner. Consider the following boundary conditions, at time T1, the power management unit (40) detects that component A is idle. At this time, the power management unit (40) invalidates ACTIVEREQ at T2 to request component A to power off. Component A invalidates ACTIVEACK at T3 to confirm that it can power off. Assume that in the time window between T2 and T3, a traffic packet unexpectedly appears. Ideally, the system should now change its mind and abort the power-off request. However, component A cannot back out of the power-off request because it lacks a mechanism to tell the requester to back out. Having the ability to back off is critical to the efficiency of the system because powering back on immediately after a forced power off is a slow process that may take hundreds of microseconds. The present invention introduces the ACTIVENACK option to provide a flexible alternative that allows the system (10) to gracefully back off in time without being dragged into an unnecessary power-off and power-on sequence.

[0187] Example 7: Power self-management of the secondary NoC (30)

[0188] In a 1:1 mapping of the primary NoC components (22) to the secondary NoC nodes (32), physical power failure of any component (22) of the primary NoC (20) will trigger its corresponding secondary NoC node (32) to be logically and physically powered off. When the secondary NoC node (32) is logically powered off, the change in its link state will be detected by its adjacent or neighboring nodes. These adjacent or neighboring nodes will now also be logically powered off, and this in turn triggers their own adjacent or neighboring nodes to also be logically powered off. This starts a chain reaction that affects the entire secondary NoC (30). Ultimately, the entire secondary NoC (30) will be in a logically powered off state. Once the entire secondary NoC (30) is powered off, the secondary NoC master node (34) will initiate a re-identification and counting process. When the re-identification process is complete, the secondary NoC node (32) that initiated the chain reaction will be logically cut off from the secondary NoC (30), and the data packets originally routed through it will now bypass it. They can also optionally be powered off physically when other slave NoC nodes (32) not participating in starting the chain reaction are powered off logically. However, this is not recommended as such power off is temporary. Therefore, it makes sense to keep them physically powered on to facilitate faster re-identification. This concept can be extended to N:1 mapping. The only difference is that as a prerequisite to powering off their single corresponding slave NoC node (32), all N components (22) of the master NoC (20) need to be powered off.

[0189] Example 8: Powering on and off a single domain

[0190] Fig.16 is a schematic diagram showing an example of power gating of a single power domain, which means that the entire main NoC (20) is grouped under a single power domain.

[0191] Power gating process for a single power domain

[0192] The following describes the power gating process of a single-domain NoC:

[0193] 1. Trigger the power gating sequence for all master nodes (M).

[0194] (a) This will prevent new requests from being accepted, but allow pending requests or responses to complete.

[0195] (b) After completing all pending transactions, enter the stop state and clock gating.

[0196] 2. Trigger power gating of all routers (R) and slave nodes (S).

[0197] (a) There should be no pending flits, requests, or responses in the router or slave nodes. Therefore, the router and slave nodes can enter the stopped state and clock gated.

[0198] 3. Prepare for power gating.

[0199] Power ungate flow for a single power domain

[0200] The following describes the power de-gating flow for a single-domain NoC:

[0201] 1. Cancel the power gate to ensure power stability.

[0202] 2. Trigger a power un-gating sequence on all masters, slaves and routers.

[0203] (a) The order of triggering is not important in the power de-gating process.

[0204] Example 9: Dual Domain Power On and Off

[0205] Fig.17 is a schematic diagram showing an example of power gating for a dual-power domain NoC, which means that the master NoC (20) is divided into two power domains consisting of power domain 1 and power domain 2. Each power domain includes a master node, a router, and a slave node.

[0206] Power gating flow for power domain 1

[0207] The following describes the power gating process for power domain 1:

[0208] 1. Trigger the power gating sequence of the master node M0.

[0209] (a) This will prevent new requests from being accepted, but allow pending requests / responses to complete.

[0210] (b) After completing all pending transactions, enter the stop state and clock gating.

[0211] 2. Trigger power gating of routers and slave nodes in power domain 1.

[0212] (a) There should be no pending flits, requests, or responses in the router or slave nodes, so the router and slave nodes can enter the stop state and clock gate.

[0213] (b) Assuming there are no requests or pending responses from M1 to slave node S0, this must be ensured by the power management unit (40).

[0214] 3. Prepare to enter power gating.

[0215] (a) After power gating, if there is a pending flit from a router in power domain 2 to power domain 1, i.e., a neighboring router is trying to send a flit to the current power-gated domain, an interrupt to the power management unit (40) should be triggered.

[0216] Power De-gating Flow for Power Domain 1

[0217] The following describes the power de-gating process for power domain 1:

[0218] 1. Cancel the power gate to ensure power stability.

[0219] 2. Trigger the power de-gating sequence for all masters, slaves, and routers within power domain 1.

[0220] (a) The order of triggering is not important in the power de-gating process.

[0221] Example 10: Another Dual Domain Power Up and Power Down

[0222] Fig.18 is a schematic diagram showing a power gating example of another dual-power domain NoC consisting of power domain 1 and power domain 2. Power domain 1 includes a master node and a router, while power domain 2 includes a slave node and a router.

[0223] Power gating flow for power domain 1

[0224] The following describes the power gating process for power domain 1:

[0225] 1. Trigger the power gating sequence of master nodes M0 and M1.

[0226] (a) This will prevent new requests from being accepted, but allow pending requests and responses to complete.

[0227] (b) After completing all pending transactions, enter the stopped state and clock gating.

[0228] 2. Trigger power gating of the router in power domain 1.

[0229] (a) There should be no pending flits, requests, and responses in the router. Therefore, the router can enter the stop state and clock gate.

[0230] (b) Assume that there are no pending responses from slave nodes S0 or S1, which is guaranteed since all master requests within the NoC are gated.

[0231] 3. Prepare to enter power gating.

[0232] Power De-gating Flow for Power Domain 1

[0233] The following describes the power de-gating process for power domain 1:

[0234] 1. Cancel the power gate to ensure power stability.

[0235] 2. Trigger the power de-gating sequence for all master nodes and routers within power domain 1. The order of triggering is not important in the power de-gating process.

[0236] Power gating flow for power domain 2

[0237] The following describes the power gating process of power domain 2:

[0238] 1. Trigger a power gating sequence for slave nodes S0 and S1 in power domain 2.

[0239] (a) After completing all pending transactions, it enters the stop state and clock gates.

[0240] (b) Assume that the power management unit (40) must ensure that M0 and M1 do not issue new requests.

[0241] 2. Trigger power gating of the router in power domain 2.

[0242] (a) There should be no pending flits, requests, and responses in the router. Therefore, the router can enter the stop state and clock gate.

[0243] (b) Assume that there are no pending responses from S0 or S1, which is guaranteed since all master requests within the NoC are gated.

[0244] 3. Prepare to enter power gating.

[0245] Power De-gating Flow for Power Domain 2

[0246] 1. Cancel the power gate to ensure power stability.

[0247] 2. Trigger the power de-gating sequence for all slave nodes and routers in power domain 2. The order of triggering is not important in the power de-gating process.

[0248] The system (10) and method of the present invention overcome the problems and shortcomings of existing solutions. For example, in addition to power management of the NoC at the link level, the present invention also provides power management at the component (22) level, which means that each component of the main NoC (20) will be managed and controlled to optimize power consumption. In addition, the secondary NoC (30) is able to power manage itself while managing the power of the main NoC (20). This is important because it eliminates the need to create a third-level NoC to power manage the second-level NoC. In addition, the power-off abort mechanism allows the system (10) to exit from unnecessary power cycles, thereby preventing any degradation in performance.

[0249] Various modifications to these embodiments will be apparent to those skilled in the art from the description and drawings. The principles associated with the various embodiments described herein may be applied to other embodiments. Therefore, the description is not intended to be limited to the attached Figure 1 The present invention is intended to provide the broadest scope consistent with the principles and novel and inventive features disclosed or suggested herein, and to retain all other such alternatives, modifications and variations that fall within the scope of the present invention and the appended claims.

[0250] In the following claims and the foregoing description of the present invention, unless the context requires otherwise due to explicit language or necessary implication, the word "comprise" or variations such as "include" or "comprising" are used in an inclusive sense, i.e. specifying the presence of stated features but not excluding the presence or addition of other features in various embodiments of the present invention.

Claims

1. A system (10) for power management of a network on chip, comprising: A main on-chip network (20), the main on-chip network (20) comprising a plurality of components (22), each component (22) having a power controller; Features A secondary network on chip (30), the secondary network on chip comprising a secondary network on chip master node (34) and a plurality of secondary network on chip nodes (32) connected thereto, the plurality of secondary network on chip nodes (32) being associated with components (22) of the primary network on chip (20) and used for power management of individual and link components (22) of the primary network on chip (20); and A power management unit (40), the power management unit (40) is connected to the secondary network-on-chip master node (34), and is configured to poll the status registers of the components (22) of the primary network-on-chip (20) to obtain the power status of each component (22), obtain the routing information of the components (22) of the primary network-on-chip (20), and send a request to the secondary network-on-chip node (32) to turn on or off the power of the relevant components (22) of the primary network-on-chip (20) through the power controller.

2. The system (10) according to claim 1, wherein: Each component (22) of the master on-chip network (20) also includes a transmitter link controller and a receiver link controller interoperating with the power controller.

3. The system (10) of claim 1, wherein: The components (22) of the master on-chip network (20) include routers, node interfaces, slices and coherent hubs.

4. The system (10) of claim 1, wherein: Each of the secondary on-chip network nodes (32) is connected to at least one component (22) of the primary on-chip network (20).

5. The system (10) of claim 1, wherein: The main on-chip network (20) is a static route including a routing table.

6. The system (10) of claim 1, wherein: The master on-chip network (20) includes a single, dual or multiple power domains.

7. A computer-implemented method for network-on-chip power management, comprising: Receiving, by the secondary network-on-chip (30), a power-off request from a power controller in a component (22) of the primary network-on-chip (20); performing an interrupt service check to check the status register of the interrupt source to identify the interrupted component (22) and the effect of the interrupt on the link component (22); Accessing the routing information of the primary on-chip network (20) to obtain traffic conditions, so as to determine the component (22) of the primary on-chip network (20) to be powered off; and According to the interrupted component (22), the impact of the interruption on the link component (22) and the routing information, the secondary on-chip network (30) powers off the component (22) of the primary on-chip network (20); The steps of performing interrupt service check and accessing routing information of the primary on-chip network (20) are performed by a power management unit (40) connected to the secondary on-chip network (30).

8. The method according to claim 7, wherein: The method further includes, when there is no power-off request, polling, by the power management unit (40), a status register of a component (22) of the primary on-chip network (20) before performing an interrupt service check, to detect a component (22) of the primary on-chip network (20) in a low power state.

9. The method according to claim 7, wherein: The method further comprises: The power management unit (40) receives a power-on request from a component (22) of the primary network on chip (20) through the secondary network on chip (30); Powering on corresponding components (22) of the master on-chip network (20); and Powering on the link component (22) of the master on-chip network (20); The link component (22) is a component (22) that acts as a path to transmit data packets from a traffic source to a destination.

10. The method according to claim 9, wherein: The power management unit (40) updates the routing information when power is supplied to the components (22) of the master on-chip network (20).

11. The method according to claim 7, wherein: The method also includes terminating the power-off request by the power management unit (40) when a change in the flow condition is detected.

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