PSOC-based airborne display system

Abstract

The invention provides a PSOC-based airborne display system, and belongs to the technical field of airborne display application, the PSOC-based airborne display system comprises a PSOC chip, a DDR3 memory module, a transceiver, an optical module and an Ethernet PHY, the PSOC chip comprises a PS part and a PL part which communicate with each other, the PS part is connected with the first DDR3 memory module, the transceiver and the Ethernet PHY, and the PL part is connected with the first DDR3 memory module, the transceiver and the Ethernet PHY. The PL part is connected with the second DDR3 memory module and the second optical module, and the first optical module is connected with the Ethernet PHY. A single PSOC is used as a main chip, airborne emergency graphics are drawn through an integrated CPU + GPU in the chip, integrated FPGA resources are used for avionics bus video decoding, video switching, video coding and transmitting display, and an integrated VPU compresses a display picture. The system integration level is improved, the weight and the size of a display product can be reduced, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of airborne display application, and in particular to an airborne display system based on PSOC. Background Art

[0002] With the development of the electronic information industry, higher requirements are placed on the integration, weight, volume and cost of airborne displays. In addition, in the face of increasingly higher data bandwidth, the problem of high-speed signal integrity in the design becomes prominent.

[0003] In airborne display products, FPGA is required to decode external avionics bus video or GPU is required to draw emergency graphics locally, and the video is switched to LCD display. The display screen is compressed with H.265 and streamed to the recorder via the network port. The existing technical solutions are multiple processing cores such as SOC+FPGA+VPU, CPU+GPU+FPGA+VPU, etc. The system design using discrete chip architecture is complex and requires the design of multiple minimum systems, which increases the product size and weight, and the cost is high. In addition, the high-speed interface cascade of PCI E, DP, HDMI, etc. is prone to signal integrity problems. Summary of the invention

[0004] In view of this, an embodiment of the present application provides an airborne display system based on PSOC, which at least partially solves the problems existing in the prior art such as increased product volume and weight, high cost, and signal integrity problems that are prone to occur in high-speed interface cascading.

[0005] The embodiment of the present application provides an airborne display system based on PSOC, the system comprising a PSOC chip, a first DDR3 memory module, a transceiver, a first optical module, an Ethernet PHY, a second DDR3 memory module and a second optical module, the PSOC chip comprising a PS part and a PL part communicating with each other, the PS part being connected to the first DDR3 memory module, the transceiver and the Ethernet PHY, the PL part being connected to the second DDR3 memory module and the second optical module, and the first optical module being connected to the Ethernet PHY;

[0006] The transceiver is used to receive drawing parameters and video switching instructions of airborne emergency graphics sent by an external communication bus; the PS part is used to draw airborne emergency graphics and compress the display screen; the Ethernet PHY and the first optical module are used to output compressed display screen video streams through the optical fiber network port; the first DDR3 memory module is used for video caching of the PS part; the second optical module is used to receive external avionics bus video data and convert optical signals into electrical signals; the PL part is used to decode avionics bus video data, perform video switching, and output video encoding; the second DDR3 memory module is used for video caching of the PL part.

[0007] According to a specific implementation of the embodiment of the present application, the PS part internally includes an APU application processor, a GPU graphics processor, a VPU video processor, a DDR memory controller and a GMAC controller, the first DDR3 memory module is connected to the DDR memory controller, the DDR memory controller is also respectively connected to the APU application processor, the GPU graphics processor, the VPU video processor and the GMAC controller, the GMAC controller is connected to the Ethernet PHY, and the APU application processor is connected to the transceiver;

[0008] The DDR storage controller is used to read and write control of the first DDR3 memory module; the APU application processor is used to receive the emergency graphics drawing parameters in the transceiver, drive the GPU graphics processor to draw airborne emergency graphics and receive video switching instructions to perform video switching display; the VPU video processor is used to compress display screen data; the GMAC controller is used to transmit the compressed video stream to the Ethernet PHY.

[0009] According to a specific implementation of the embodiment of the present application, the PL part internally includes a GTX high-speed serial transceiver, a decoding module, a VDMA module, an AXI interconnect module, a video switching module, a video encoding module and a MI G module, the GTX high-speed serial transceiver is connected to the second optical module, and the MI G module is connected to the second DDR3 memory module;

[0010] The GTX high-speed serial transceiver is used to receive the electrical signal of the second optical module, and convert the avionics bus video data into serial-to-parallel, and to send the video encoding module data and convert the display screen data into parallel-to-serial; the decoding module is used to parse the avionics video bus protocol, and cache the video data into the second DDR3 memory module through the VDMA module and the AXI interconnect module; the MI G module is used to read and write control the second DDR3 memory module; the video switching module is used to output the avionics bus video data and the airborne emergency graphic data in a selective manner; the video encoding module is used to encode the video data switched by the video switching module and transmit it to the LCD screen for display.

[0011] According to a specific implementation method of an embodiment of the present application, the VPU video processor compresses the display screen data using the H.265 standard.

[0012] According to a specific implementation of an embodiment of the present application, the avionics bus is set to ARI NC818 or HDMI.

[0013] According to a specific implementation of the embodiment of the present application, the communication bus is set to RS422, RS485 or ARINC429.

[0014] According to a specific implementation of an embodiment of the present application, the Ethernet PHY supports a Serdes serial interface and applies a 1000base-x protocol.

[0015] According to a specific implementation of an embodiment of the present application, the model of the PSOC chip is a fully programmable JFMQL100TAI900 chip.

[0016] Beneficial effects:

[0017] The PSOC-based airborne display system in the embodiment of the present application uses a single PSOC as the main chip, draws airborne emergency graphics through the CPU+GPU integrated inside the chip, and performs avionics bus video decoding and video switching, video encoding and display transmission through the integrated FPGA resources, and the integrated VPU performs H.265 compression on the display screen. The present invention improves the system integration, can reduce the weight and volume of the display product, and reduce costs. Through the data handling of the chip's internal bus DMA, the signal integrity problems that are prone to occur in the high-speed interface of discrete chips are avoided. Therefore, the airborne display system of the present application has a high degree of integration, which is conducive to reducing the weight and volume of the product and reducing costs; the data handling of the internal bus DMA is efficient and avoids the signal integrity problems caused by the cascading of the high-speed interface of discrete chips; the optical fiber data is transmitted over long distances, has strong anti-interference capabilities, and has no EMC problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A principle block diagram of an onboard display system based on PSOC according to an embodiment of the present invention;

[0020] Figure 2 FIG. 4 is an internal block diagram of a PSOC chip of an airborne display system based on PSOC according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0022] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0023] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0024] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0025] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0026] This embodiment provides an airborne display system based on PSOC, referring to Figure 1 , the system includes a PSOC chip, a first DDR3 memory module, a transceiver, a first optical module, an Ethernet PHY, a second DDR3 memory module and a second optical module, the PSOC chip includes a PS part and a PL part that communicate with each other, the PS part is connected to the first DDR3 memory module, the transceiver and the Ethernet PHY, the PL part is connected to the second DDR3 memory module and the second optical module, and the first optical module is connected to the Ethernet PHY;

[0027] The transceiver is used to receive drawing parameters and video switching instructions of airborne emergency graphics sent by an external communication bus; the PS part is used to draw airborne emergency graphics and compress the display screen; the Ethernet PHY and the first optical module are used to output compressed display screen video streams through the optical fiber network port; the first DDR3 memory module is used for video caching of the PS part; the second optical module is used to receive external avionics bus video data and convert optical signals into electrical signals; the PL part is used to decode avionics bus video data, perform video switching, and output video encoding; the second DDR3 memory module is used for video caching of the PL part.

[0028] This application uses a single PSOC as the main chip, draws airborne emergency graphics through the CPU+GPU integrated inside the chip, integrates FPGA resources for avionics bus video decoding and video switching, video encoding and display, and integrated VPU performs H.265 compression on the display screen. This embodiment improves the system integration, can reduce the weight and volume of the display product, and reduce costs. Through the data transfer of the chip internal bus DMA, the signal integrity problem that is easy to occur in the high-speed interface of discrete chips is avoided.

[0029] Further, see Figure 2 The PS part includes an APU application processor, a GPU graphics processor, a VPU video processor, a DDR memory controller and a GMAC controller, the first DDR3 memory module is connected to the DDR memory controller, the DDR memory controller is also connected to the APU application processor, the GPU graphics processor, the VPU video processor and the GMAC controller respectively, the GMAC controller is connected to the Ethernet PHY, and the APU application processor is connected to the transceiver;

[0030] The DDR storage controller is used to read and write control of the first DDR3 memory module; the APU application processor is used to receive the emergency graphics drawing parameters in the transceiver, drive the GPU graphics processor to draw airborne emergency graphics and receive video switching instructions to perform video switching display; the VPU video processor is used to compress display screen data; the GMAC controller is used to transmit the compressed video stream to the Ethernet PHY.

[0031] Furthermore, the PL part internally includes a GTX high-speed serial transceiver, a decoding module, a VDMA module, an AXI interconnect module, a video switching module, a video encoding module and a MI G module, the GTX high-speed serial transceiver is connected to the second optical module, and the MI G module is connected to the second DDR3 memory module;

[0032] The GTX high-speed serial transceiver is used to receive the electrical signal of the second optical module, and convert the avionics bus video data into serial-to-parallel, and to send the video encoding module data and convert the display screen data into parallel-to-serial; the decoding module is used to parse the avionics video bus protocol, and cache the video data into the second DDR3 memory module through the VDMA module and the AXI interconnect module; the MI G module is used to read and write control the second DDR3 memory module; the video switching module is used to output the avionics bus video data and the airborne emergency graphic data in a selective manner; the video encoding module is used to encode the video data switched by the video switching module and transmit it to the LCD screen for display.

[0033] Specifically, the second optical module receives the avionics bus video data of the external second optical fiber, realizes the conversion of optical fiber signal into electrical signal and sends it to the GTX serial transceiver of the PL part of the PSOC chip. The avionics bus can be any video bus, not limited to ARINC818, HDMI, etc.;

[0034] like Figure 2 As shown, inside the PSOC chip, the GTX serial transceiver completes the data serial-to-parallel conversion and sends the parallel avionics bus data to the decoding module. After protocol parsing, the 24-bit RGB video data is decoded and written into the second DDR3 memory module for caching through the VDMA module and the AXI interconnect module.

[0035] The transceiver receives emergency graphics drawing parameters and video switching instructions sent by an external communication bus. The communication bus can be RS422, RS485, ARI NC429 and other buses. The transceiver completes bus conversion and is connected to the PS part. The APU application processor receives the drawing parameters, drives the GPU graphics processor to draw the onboard emergency graphics, and writes the graphics to the first DDR3 memory module for caching.

[0036] According to the switching instruction, the APU application processor controls the video switching module through the AXI Lite bus inside the chip to read the video data cached in the first DDR3 memory module or the second DDR3 memory module through the VDMA module and send it to the video encoding module.

[0037] The video encoding module encodes RGB video data according to the LCD interface, not limited to encoding DP or HDMI protocol video, and sends it to the GTX serial transceiver to complete data parallel-to-serial conversion and send it to the LCD for display.

[0038] According to the switching instruction, the APU application processor calls the VPU video processor to read the cached RGB video data to be displayed in the DDR3 memory module, performs H.265 standard compression, and sends the video stream to the GMAC controller.

[0039] The Ethernet PHY is connected to the GMAC controller to complete the Ethernet Serdes serial output; the Ethernet PHY must support the Serdes serial interface and the 1000base-x protocol.

[0040] The first optical module converts electrical signals into optical fiber signals and sends the video stream to an external recorder.

[0041] In one embodiment, the VPU video processor compresses display picture data using the H.265 standard.

[0042] In one embodiment, the avionics bus is configured as ARI NC818 or HDMI.

[0043] In one embodiment, the communication bus is configured as RS422, RS485 or ARI NC429.

[0044] In one embodiment, the Ethernet PHY supports Serdes serial interface and applies 1000base-x protocol.

[0045] In one embodiment, the model of the Ethernet PHY is 88e1111.

[0046] In one embodiment, the model of the PSOC chip is a fully programmable JFMQL100TAI 900 chip.

[0047] In one embodiment, the model of the transceiver is max3490.

[0048] In specific implementation, the second optical module receives the video data of the external second optical fiber avionics bus, realizes the conversion of optical fiber signal into electrical signal and sends it to the GTX serial transceiver of the PL part of the PSOC chip. The avionics bus can be a single LANE ARI NC818 protocol, with an optical fiber rate of 4.25Gbps and a video resolution of 1080P@60Hz. Figure 2As shown in the figure, inside the PSOC chip, the GTX serial transceiver receives the ARINC818 data, converts it into 32-bit parallel avionics bus data and sends it to the decoding module, completes the ARI NC818 protocol parsing, decodes the 24-bit RGB effective video data, controls the routing channels of the VDMA module and the AXI Interconnect module through AXI Lite, and writes the video data into the second DDR3 memory module through the MI G controller for circular caching.

[0049] The transceiver implements two communication buses for receiving emergency graphics drawing parameters and video switching instructions sent by an external communication bus. The communication bus can be an RS422 bus. The transceiver completes the bus conversion to UART and connects to the UART function interface of the PS part. The APU application processor receives the drawing parameters, drives the GPU graphics processor to draw the onboard emergency graphics and fill in the parameters. The video resolution is 1080P@60Hz, and the emergency graphics RGB data is written into the first DDR3 memory module through the DDR storage controller for circular caching. The transceiver uses two MAXI M company max3490.

[0050] The APU application processor parses the UART protocol, receives the switching instruction, controls the video switching module through the AXI Lite bus inside the chip, reads the RGB video data cached in the first DDR3 memory module or the second DDR3 memory module through the routing channel of the VDMA module and the AXI Interconnect module, and sends it to the video encoding module.

[0051] The video encoding module encodes the input RGB video data, encodes it into DP protocol video, sends it to the GTX serial transceiver to complete the parallel-to-serial conversion of the video data, and sends it to the DP interface LCD screen for display.

[0052] According to the switching instruction, the APU application processor calls the VPU video processor to read the cached RGB video data to be displayed in the first DDR3 memory module or the second DDR3 memory module, performs H.265 standard compression, and sends the video stream to the GMAC controller.

[0053] The Ethernet PHY is connected to the GMAC controller to complete the Ethernet Serdes serial output of the video stream; the Ethernet PHY must support the Serdes serial interface and 1000base-x protocol, and MARVELL's 88e1111 is selected.

[0054] The first optical module converts the electrical signal into an optical fiber signal and sends the video stream to an external recorder.

[0055] The first DDR3 memory module and the second DDR3 memory module are composed of DDR3 particles, and can use Micron and Changxin storage memory particles.

[0056] The PSOC chip is Fudan Microelectronics' fully programmable JFMQL100TAI900 chip, which is based on 28nm and integrates a 4-core high-performance processor APU, a high-performance graphics processor GPU, a high-bandwidth video processor VPU, rich FPGA resources and an AI acceleration engine on a single chip.

[0057] The present invention uses a single PSOC as the main chip, draws airborne emergency graphics through the CPU+GPU integrated inside the chip, uses the integrated FPGA resources to perform avionics bus video decoding and video switching, video encoding and display, and the integrated VPU performs H.265 compression on the display screen. It has high integration, simple system architecture, is conducive to reducing product volume, weight and cost, and avoids the signal integrity problem caused by high-speed interface cascading.

[0058] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A PSOC-based airborne display system, characterized in that: The system includes a PSOC chip, a first DDR3 memory module, a transceiver, a first optical module, an Ethernet PHY, a second DDR3 memory module and a second optical module, wherein the PSOC chip includes a PS part and a PL part that communicate with each other, wherein the PS part is connected to the first DDR3 memory module, the transceiver and the Ethernet PHY, wherein the PL part is connected to the second DDR3 memory module and the second optical module, and wherein the first optical module is connected to the Ethernet PHY; The transceiver is used to receive drawing parameters and video switching instructions of airborne emergency graphics sent by an external communication bus; the PS part is used to draw airborne emergency graphics and compress the display screen; the Ethernet PHY and the first optical module are used to output the compressed display screen video stream through the optical fiber network port; the first DDR3 memory module is used for video caching of the PS part; The second optical module is used to receive external avionics bus video data and convert optical signals into electrical signals; the PL part is used to decode the avionics bus video data, perform video switching, and output the video encoding; the second DDR3 memory module is used for video caching of the PL part.

2. The PSOC-based airborne display system according to claim 1, characterized in that: The PS part internally includes an APU application processor, a GPU graphics processor, a VPU video processor, a DDR memory controller and a GMAC controller, the first DDR3 memory module is connected to the DDR memory controller, the DDR memory controller is also connected to the APU application processor, the GPU graphics processor, the VPU video processor and the GMAC controller respectively, the GMAC controller is connected to the Ethernet PHY, and the APU application processor is connected to the transceiver; The DDR storage controller is used to read and write control of the first DDR3 memory module; the APU application processor is used to receive the emergency graphics drawing parameters in the transceiver, drive the GPU graphics processor to draw airborne emergency graphics and receive video switching instructions to perform video switching display; the VPU video processor is used to compress display screen data; the GMAC controller is used to transmit the compressed video stream to the Ethernet PHY.

3. The PSOC-based airborne display system according to claim 2, characterized in that: The PL part internally includes a GTX high-speed serial transceiver, a decoding module, a VDMA module, an AXI interconnect module, a video switching module, a video encoding module and a MIG module, the GTX high-speed serial transceiver is connected to the second optical module, and the MIG module is connected to the second DDR3 memory module; The GTX high-speed serial transceiver is used to receive the electrical signal of the second optical module, and convert the avionics bus video data into serial-to-parallel, and to send the video encoding module data and convert the display screen data into parallel-to-serial; the decoding module is used to parse the avionics video bus protocol, and cache the video data into the second DDR3 memory module through the VDMA module and the AXI interconnect module; the MIG module is used to read and write control the second DDR3 memory module; the video switching module is used to output either the avionics bus video data or the airborne emergency graphic data; the video encoding module is used to encode the video data switched by the video switching module and transmit it to the LCD screen for display.

4. The PSOC-based airborne display system according to claim 2, characterized in that: The VPU video processor compresses the display picture data using the H.265 standard.

5. The PSOC-based airborne display system according to claim 1, characterized in that: The avionics bus is configured as ARINC818 or HDMI.

6. The PSOC-based airborne display system according to claim 1, characterized in that: The communication bus is set to RS422, RS485 or ARINC429.

7. The PSOC-based airborne display system according to claim 1, characterized in that: The Ethernet PHY supports Serdes serial interface and applies 1000base-x protocol.

8. The PSOC-based airborne display system according to claim 1, characterized in that: The model of the PSOC chip is a fully programmable JFMQL100TAI900 chip.

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