Pulse sequence type image sensor and electronic equipment

Abstract

The invention provides a pulse sequence type image sensor. The pulse sequence type image sensor comprises a pixel module and a reading module, the pixel module comprises more than two pixels, and the pixels are divided into a first group and a second group; the reading module comprises a first comparator, a second comparator and a mode switching sub-module, and is configured as follows: when the mode switching sub-module works in a first state, pixels in the pixel module are respectively connected with the first comparator and the second comparator; the reference signal of the first comparator is larger than that of the second comparator, and the reference signal of the second comparator is equal to the threshold value of the electric signal; and when the mode switching sub-module works in a second state, the pixels in the first group are connected with the first comparator, the pixels in the second group are connected with the second comparator, and the reference signals of the first comparator and the second comparator are equal to the threshold value of the electric signal. The invention further provides the electronic equipment. The pulse sequence type image sensor provided by the invention has a better signal to noise ratio.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a pulse sequence image sensor and electronic equipment. Background Art

[0002] During the operation of the image sensor, each pixel reset will bring random reset noise, and the transmission path of reading the pixel signal (i.e. the electrical signal formed by photoelectric conversion) from the pixel to the column circuit will also introduce certain noise. The existence of these noises directly affects the image quality of the image sensor.

[0003] In order to suppress these noises, the traditional 4T pixel (i.e., four-transistor pixel) will first retain the photogenerated charge generated by the exposure of the photodiode in the photodiode after the photodiode is exposed, reset the floating diffusion area, and sample the reset signal on the floating diffusion area and read it out to the column-level circuit; then, the photogenerated charge on the photodiode is transferred to the floating diffusion area by controlling the conduction of the transfer transistor, and the photosensitive signal on the floating diffusion area is sampled to the column-level circuit; finally, the two signals sampled to the column-level circuit are differentiated. Differentiating the above two signals can effectively eliminate the noise introduced in the pixel reset process and the pixel signal transmission path, so that the subsequent processing of the differential signal can form a good quality image.

[0004] Compared with traditional 4T pixels, traditional pulse sequence pixels lack floating diffusion areas and transfer transistors, so they cannot effectively suppress the noise introduced in the pixel reset process and the pixel signal transmission path, resulting in poor image quality of the pulse sequence image sensor formed based on traditional pulse sequence pixels. Summary of the invention

[0005] In order to overcome the above-mentioned defects in the prior art, the present invention provides a pulse sequence image sensor, which comprises:

[0006] A pixel module and a readout module connected to the pixel module;

[0007] The pixel module includes more than two pixels, the more than two pixels are divided into a first group and a second group, and the pixels are used to convert optical signals into electrical signals and output them;

[0008] The readout module includes a first comparator, a second comparator and a mode switching submodule, wherein the first comparator, the second comparator and the mode switching submodule are configured as follows:

[0009] When the mode switching submodule operates in the first state, each pixel in the pixel module is connected to the first comparator and the second comparator respectively, and the first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold value of the electrical signal;

[0010] When the mode switching submodule operates in the second state, each pixel in the first group is connected to the first comparator, each pixel in the second group is connected to the second comparator, and the first reference signal of the first comparator and the second reference signal of the second comparator are both equal to the threshold of the electrical signal.

[0011] According to one aspect of the present invention, in the pulse sequence image sensor, the pulse sequence image sensor includes a pixel array and a readout circuit; each column of pixels in the pixel array constitutes a pixel module; the readout circuit includes the same number of readout modules as the pixel modules and corresponding to each other, and each readout module is connected to the corresponding pixel module.

[0012] According to another aspect of the present invention, in the pulse sequence image sensor, the pixels located at odd-numbered row positions in each column of the pixels are divided into one of the first group and the second group, and the pixels located at even-numbered row positions are divided into the other of the first group and the second group.

[0013] According to another aspect of the present invention, in the pulse sequence image sensor, each of the pixels includes an input terminal for receiving a reset signal, and an output terminal for outputting the electrical signal; each pixel in the pixel module is respectively connected to the first comparator and the second comparator, including: the output terminal of each pixel in the pixel module is respectively connected to the negative input terminal of the first comparator and the negative input terminal of the second comparator, and the input terminal of each pixel in the pixel module is connected to the output terminal of the second comparator; each pixel in the first group is connected to the first comparator, and each pixel in the second group is connected to the second comparator, including: the output terminal of each pixel in the first group is connected to the negative input terminal of the first comparator, the input terminal of each pixel in the first group is connected to the output terminal of the first comparator, the output terminal of each pixel in the second group is connected to the negative input terminal of the second comparator, and the input terminal of each pixel in the second group is connected to the output terminal of the second comparator.

[0014] According to another aspect of the present invention, in the pulse sequence image sensor, each pixel includes a photoelectric conversion unit, a signal output unit and a reset unit; the photoelectric conversion unit is used to convert an optical signal into an electrical signal; the signal output unit is used to output the electrical signal, wherein a first end of the signal output unit is connected to the photoelectric conversion unit, and a second end of the signal output unit serves as an output end of the pixel; the reset unit is used to reset the photoelectric conversion unit according to the reset signal, wherein a first end of the reset unit is connected to the photoelectric conversion unit, and a second end of the reset unit serves as an input end of the pixel.

[0015] According to another aspect of the present invention, in the pulse sequence image sensor, the photoelectric conversion unit includes a photodiode, wherein the positive electrode of the photodiode is grounded, and the negative electrode of the photodiode is connected to the first end of the signal output unit and the first end of the reset unit; and the electrical signal is a negative electrode voltage signal of the photodiode.

[0016] According to another aspect of the present invention, in the pulse sequence image sensor, the signal output unit includes a source follower transistor and a pixel selection transistor; the first end of the source follower transistor is connected to a power supply, the second end of the source follower transistor is connected to the first end of the pixel selection transistor, and the third end of the source follower transistor is connected to the negative electrode of the photodiode as the first end of the signal output unit; the second end of the pixel selection transistor is connected to the corresponding readout module as the second end of the signal output unit, and the third end of the pixel selection transistor is used to receive a first control signal to control its conduction or disconnection; wherein, when the pixel selection transistor is turned on, the source follower transistor outputs the negative electrode voltage signal of the photodiode it reads to the corresponding readout module through the pixel selection transistor.

[0017] According to another aspect of the present invention, in the pulse sequence image sensor, the reset part includes a reset transistor and a reset selection transistor; the first end of the reset transistor is connected to a power supply, the second end of the reset transistor is connected to the negative electrode of the photodiode as the first end of the reset part, and the third end of the reset transistor is connected to the second end of the reset selection transistor; the first end of the reset selection transistor is connected to the corresponding readout module as the second end of the reset part, and the third end of the reset selection transistor is used to receive a second control signal for controlling its conduction or disconnection; wherein, when the first end of the reset selection transistor receives the reset signal and the reset transistor is turned on, the reset transistor resets the photodiode according to the reset signal.

[0018] According to another aspect of the present invention, in the pulse sequence image sensor, the mode switching submodule includes a first electrical signal output line, a second electrical signal output line, a first reset signal input line, a second reset signal input line, a first switch, a second switch and a third switch; the output end of the pixels in the first group is connected to the negative input end of the first comparator through the first electrical signal output line, the output end of the pixels in the second group is connected to the negative input end of the second comparator through the second electrical signal output line, and the first switch is arranged between the first electrical signal output line and the second electrical signal output line; the input end of the pixels in the first group is connected to the output end of the first comparator through the first reset signal input line, the input end of the pixels in the second group is connected to the output end of the second comparator through the second reset signal input line, the second switch is arranged between the first reset signal input line and the second reset signal input line, and the third switch is arranged on the first reset signal input line and between the second switch and the first comparator; wherein, when the first switch and the second switch are both turned on and the third switch is turned off, the mode switching submodule operates in the first state; when the first switch and the second switch are both turned off and the third switch is turned on, the mode switching submodule operates in the second state.

[0019] The present invention also provides a pulse sequence image sensor, the pulse sequence image sensor comprising:

[0020] A pixel module and a readout module connected to the pixel module;

[0021] The pixel module includes more than two pixels, and the pixels are used to convert optical signals into electrical signals and output them;

[0022] The readout module includes a first comparator, a second comparator and a signal line sub-module, wherein each pixel in the pixel module is connected to the first comparator and the second comparator through the signal line sub-module, and the first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold of the electrical signal.

[0023] The present invention also provides an electronic device, which comprises the aforementioned pulse sequence image sensor.

[0024] The pulse sequence image sensor provided by the present invention includes a pixel module and a readout module connected to the pixel module, the pixel module includes two groups of pixels, the readout module includes two comparators and a mode switching submodule, wherein the readout module is configured to enable the pulse sequence image sensor provided by the present invention to work in a first pulse sequence output mode and a second pulse sequence output mode. When the pulse sequence image sensor provided by the present invention works in the first pulse sequence output mode, the pixel signal of each pixel in the pixel module is transmitted to the two comparators respectively, and the reference signals of the two comparators are set to be unequal, and subsequently, only the pulse sequence output by the two comparators needs to be differentially operated to eliminate the pixel reset noise and the noise introduced in the pixel signal transmission path, thereby effectively improving the signal-to-noise ratio performance of the image sensor, and then improving the image quality of the image sensor. When the pulse sequence image sensor provided by the present invention works in the second pulse sequence output mode, the pixel signal of the first group of pixels in the pixel module is transmitted to the first comparator, and the pixel signal of the second group of pixels is transmitted to the second comparator, and the first comparator and the second comparator work in parallel so that the pixel signals of the two groups of pixels are read out in parallel. Compared with the prior art in which the pixel signals of each pixel in the pixel module can only be read out one by one, the implementation of the present invention is conducive to improving the readout efficiency of the pixel signal, thereby improving the frame rate of the pulse sequence image sensor. That is to say, in application scenarios with high requirements for the signal-to-noise ratio, the pulse sequence image sensor provided by the present invention can be operated in the first pulse sequence output mode, and in application scenarios with high requirements for the frame rate, the pulse sequence image sensor provided by the present invention can be operated in the second pulse sequence output mode. The electronic device formed based on the pulse sequence image sensor provided by the present invention also has better performance accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0026] Figure 1 is a circuit structure diagram of a column of pixels and a corresponding readout module in a pulse sequence image sensor according to a specific embodiment of the present invention;

[0027] Figure 2 is a circuit structure diagram of a column of pixels and a corresponding readout module in a pulse sequence image sensor according to another specific embodiment of the present invention;

[0028] Figure 3 yes Figure 2 The equivalent circuit diagram of the structure shown working in the first pulse sequence output mode;

[0029] Figure 4yes Figure 2 The equivalent circuit diagram of the structure shown in FIG. 1 working in the second pulse sequence output mode;

[0030] Figure 5 yes Figure 2 The working timing diagram of the structure shown in the first pulse sequence output mode;

[0031] Figure 6 yes Figure 2 The working timing diagram of the structure shown in the second pulse train output mode.

[0032] The same or similar reference numerals in the drawings represent the same or similar components. DETAILED DESCRIPTION

[0033] In order to better understand and illustrate the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0034] The present invention provides a pulse sequence image sensor, the pulse sequence image sensor comprising:

[0035] A pixel module and a readout module connected to the pixel module;

[0036] The pixel module includes more than two pixels, the more than two pixels are divided into a first group and a second group, and the pixels are used to convert optical signals into electrical signals and output them;

[0037] The readout module includes a first comparator, a second comparator and a mode switching submodule, wherein the first comparator, the second comparator and the mode switching submodule are configured as follows:

[0038] When the mode switching submodule operates in the first state, each pixel in the pixel module is connected to the first comparator and the second comparator respectively, and the first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold value of the electrical signal;

[0039] When the mode switching submodule operates in the second state, each pixel in the first group is connected to the first comparator, each pixel in the second group is connected to the second comparator, and the first reference signal of the first comparator and the second reference signal of the second comparator are both equal to the threshold of the electrical signal.

[0040] The various components of the above-mentioned pulse sequence image sensor will be described in detail below.

[0041] Specifically, the pulse sequence image sensor provided by the present invention includes a pixel module and a readout module connected to the pixel module. The pixel module includes more than two pixels, wherein the pixel is used to convert the light signal into a pixel signal (i.e., an electrical signal) and output the pixel signal. The readout module is used to read out the pixel signal of the pixel in the pixel module connected thereto.

[0042] In this embodiment, the number of pixel modules and readout modules in the pulse sequence image sensor provided by the present invention is N, where N is an integer and N≥1. The N pixel modules constitute the pixel array of the pulse sequence image sensor, and the N readout modules constitute the readout circuit of the pulse sequence image sensor. In this embodiment, the N pixel modules in the pixel array correspond to the N readout modules in the readout circuit, and the corresponding pixel modules and readout modules are connected. In addition, in this embodiment, each pixel includes an input end and an output end, wherein the input end is used to receive a reset signal of the pixel, and the output end is used to output a pixel signal of the pixel. It should be noted that (1) the present invention does not impose any restrictions on how to divide the pixel array to obtain pixel modules. In a preferred embodiment, the pixel array is divided into columns, and each column is regarded as a pixel module. In other embodiments, the pixel array can also be divided in other ways. Taking the pixel array including 4 rows×4 columns of pixels as an example, the pixel array can be divided into 4 pixel modules, and each pixel module includes 2 rows×2 columns of pixels. For the sake of simplicity, all the ways of dividing the pixel modules are not listed one by one here. (2) When the number of pixel modules is more than two, the number of pixels in each pixel module is preferably the same, but may be different, and the present invention does not impose any limitation on this. (3) The present invention does not impose any limitation on the specific structure of the pixel. Any photoelectric conversion structure having the above-mentioned input and output terminals and capable of being used in an image sensor is applicable to the pixel in the present invention. For the sake of simplicity, all possible structures of the pixel are not listed one by one here. All pixels in the pixel array preferably have the same structure, but may be different, and the present invention does not impose any limitation on this. The following will be explained by taking the example that all pixels in the pixel array have the same structure.

[0043] In this embodiment, the pixels in each pixel module are further divided into two groups, which are represented by the first group and the second group below. Preferably, the number of pixels in the first group and the second group is equal or as close as possible. Specifically, when the pixel module includes an even number of pixels, the number of pixels in the first group and the second group is the same; when the pixel module includes an odd number of pixels, the number of pixels in the first group and the second group differs by one. It can be understood by those skilled in the art that, according to actual design requirements, the number of pixels in the first group and the second group may also be different, and the present invention does not make any limitation on this. In addition, the present invention does not make any limitation on which pixels are specifically included in the first group and the second group. Take the case where each column of pixels is regarded as a pixel module and the number of pixels in the first group and the second group is equal or as close as possible as an example for explanation. In a specific embodiment, the pixels in each column of pixels located at odd-numbered row positions are divided into the first group, and the pixels in each column of pixels located at even-numbered row positions are divided into the second group; or the pixels in each column of pixels located at even-numbered row positions are divided into the first group, and the pixels in each column of pixels located at odd-numbered row positions are divided into the second group. In another specific embodiment, the pixels in the first half of each column are divided into a first group, and the pixels in the second half of each column are divided into a second group. For the sake of simplicity, all possibilities of the first group and the second group are not listed one by one.

[0044] In this embodiment, each readout module reads out the pixel signal of each pixel in the corresponding pixel module and outputs it in the form of a pulse sequence. The readout module includes a first comparator, a second comparator and a mode switching submodule, and the first comparator, the second comparator and the mode switching submodule are configured as follows:

[0045] When the mode switching submodule operates in the first state, each pixel in the pixel module corresponding to the readout module is respectively connected to the first comparator and the second comparator, and the reference signal of the first comparator (hereinafter referred to as the first reference signal) is set to be greater than the reference signal of the second comparator (hereinafter referred to as the second reference signal), and the second reference signal of the second comparator is set to be equal to the threshold value of the pixel signal. In a specific embodiment, each pixel in the pixel module corresponding to the readout module is respectively connected to the first comparator and the second comparator, including: the output end of each pixel in the pixel module is respectively connected to the negative input end of the first comparator and the negative input end of the second comparator, the input end of each pixel in the pixel module is connected to the output end of the second comparator, the first reference signal is input to the positive input end of the first comparator, and the second reference signal is input to the positive input end of the second comparator.

[0046] When the mode switching submodule operates in the second state, the first group of pixels in the pixel module corresponding to the readout module is connected to the first comparator, the second group of pixels in the pixel module corresponding to the readout module is connected to the second comparator, and the first reference signal of the first comparator and the second reference signal of the second comparator are both set to be equal to the threshold value of the pixel signal. In a specific embodiment, the first group of pixels in the pixel module corresponding to the readout module is connected to the first comparator, and the second group of pixels in the pixel module corresponding to the readout module is connected to the second comparator, including: the output end of each pixel in the first group is connected to the negative input end of the first comparator, the input end of each pixel in the first group is connected to the output end of the first comparator, the output end of each pixel in the second group is connected to the negative input end of the second comparator, the input end of each of the pixels in the second group is connected to the output end of the second comparator, the first reference signal is input to the positive input end of the first comparator, and the second reference signal is input to the positive input end of the second comparator.

[0047] It should be noted that (1) the present invention does not impose any restrictions on the specific structure of the first comparator and the second comparator. Any device or circuit that can realize the comparison function is applicable to the present invention. For the sake of simplicity, they are not listed one by one here. (2) In a specific embodiment, the mode switching submodule includes a signal line submodule and a switch submodule, wherein the signal line submodule includes a signal line for connecting each pixel in the pixel module with the comparator, and the switch submodule includes a switch element for controlling the on / off / short-circuit state of the signal line in the signal submodule. It can be understood by those skilled in the art that the above is only a preferred embodiment of the mode switching submodule, which should not be a limitation on the structure of the mode switching submodule. Any structure that can switch between the above two connection modes between the pixels in the pixel module and the corresponding comparator is applicable to the mode switching submodule in the present invention. For the sake of simplicity, all possible structures of the mode switching submodule are not listed one by one here. (3) When the pixel signal of a pixel reaches a certain value, the pixel needs to be reset, and the value is the threshold value of the pixel signal. Typically, the pixel signal of a pixel is a voltage signal formed by photoelectric conversion, and the threshold of the pixel signal is the threshold voltage. For a pixel, as the exposure time increases, the voltage signal formed by the pixel through photoelectric conversion gradually decreases until the voltage signal drops to the threshold voltage and the pixel is reset. The following document will take the example that the pixel signal of a pixel is a voltage signal formed by photoelectric conversion as an example.

[0048] For the pulse sequence image sensor provided by the present invention, when the mode switching submodules in all the readout modules are working in the first state, the working mode of the pulse sequence image sensor is expressed as the first pulse sequence output mode; when the mode switching submodules in all the readout modules are working in the second state, the working mode of the pulse sequence image sensor is expressed as the second pulse sequence output mode.

[0049] When the pulse sequence image sensor works in the first pulse sequence output mode, the readout module reads out the pixel signals of each pixel in the corresponding pixel module one by one in each frame. For each pixel, its pixel signal is usually close to the power supply voltage after reset. As the exposure time increases, the pixel signal will gradually decrease due to the accumulation of photogenerated charges. Since the first reference signal of the first comparator is greater than the second reference signal of the second comparator, the pixel signal of the pixel first decreases to the first reference signal and triggers the first comparator to output a high-level pulse signal. When the pixel signal of the pixel continues to decrease to the second reference signal (i.e., the threshold of the pixel signal), the second comparator is triggered to output a high-level pulse signal. The high-level pulse signal can be used to trigger the pixel to reset. After reset, the pixel continues to be exposed, and the cycle continues. When the pulse sequence output by the first comparator and the second comparator is subsequently processed, for each pixel, the time difference between the pixel signal triggering the first comparator to output a high-level pulse signal and the time difference triggering the second comparator to output a high-level pulse signal in each exposure is calculated (the length of the time difference can express the intensity of the light, wherein the shorter the time difference, the stronger the light intensity, and the longer the time difference, the weaker the light intensity), and an image is formed according to the time difference. Since the voltage difference between the first reference signal and the second reference signal is fixed, even if noise is introduced in the pixel reset and pixel signal transmission path, it will not affect the time for the pixel signal of the pixel to drop from the first reference signal to the second reference signal. In this way, the noise introduced in the pixel reset and pixel signal transmission path can be effectively eliminated, which is conducive to improving the signal-to-noise ratio performance of the pulse sequence image sensor.

[0050] When the pulse sequence image sensor operates in the second pulse sequence output mode, in each frame, the first comparator reads out the pixel signal of each pixel in the first group one by one, and the second comparator reads out the pixel signal of each pixel in the second group one by one. For each pixel in the first group, as the exposure time increases, when the pixel signal of the pixel drops to the first reference signal (i.e., the threshold of the pixel signal), the first comparator outputs a high-level pulse, which can be used to trigger the pixel to reset, and the pixel continues to be exposed after the reset, and so on. Similarly, for each pixel in the second group, as the exposure time increases, when the pixel signal of the pixel drops to the second reference signal (i.e., the threshold of the pixel signal), the second comparator outputs a high-level pulse, which can be used to trigger the pixel to reset, and the pixel continues to be exposed after the reset, and so on. Since the readout module can read the pixel signals of the pixels in the first group and the second group in parallel, the readout efficiency of the pixel signal can be effectively improved, thereby improving the frame rate of the pulse sequence image sensor.

[0051] From the above description, it can be seen that the pulse sequence image sensor provided by the present invention improves the signal-to-noise ratio performance when working in the first pulse sequence output mode, and can increase the frame rate when working in the second pulse sequence output mode. In this way, the working mode of the pulse sequence image sensor can be selected according to actual needs to meet different application scenarios.

[0052] It should also be noted that, in addition to the pixel array and the readout circuit, the pulse sequence image sensor generally also includes conventional components such as peripheral circuits. For the sake of simplicity, these conventional components are not listed one by one here.

[0053] The following will be combined Figure 1 The pulse sequence image sensor provided by the present invention is described with a specific embodiment. It should be noted that, for the sake of simplicity, Figure 1 The entire pixel array and readout circuit in the pulse sequence image sensor are not shown, but only one pixel module (specifically, a column of pixels in the pixel array) and the corresponding readout module are schematically drawn.

[0054] Specifically, as shown in the figure, the pixel module includes pixel 1, pixel 2, pixel 3, pixel 4, ..., wherein each pixel includes a photoelectric conversion unit 100, a signal output unit 110 and a reset unit 120. In the present embodiment, the photoelectric conversion unit 100 is used to convert an optical signal into an electrical signal; the signal output unit 110 is used to output the electrical signal formed by the photoelectric conversion unit 100 through photoelectric conversion, wherein the first end of the signal output unit 110 is connected to the photoelectric conversion unit 100, and the second end of the signal output unit 110 is connected to the readout module as the output end of the pixel; the reset unit 120 is used to reset the photoelectric conversion unit 100 according to the reset signal, wherein the first end of the reset unit 120 is connected to the photoelectric conversion unit 100, and the second end of the reset unit 120 is connected to the readout module as the input end of the pixel. In addition, in the present embodiment, the pixels located at odd-numbered rows in the pixel module (i.e., pixel 1, pixel 3, ...) are divided into the first group, and the pixels located at even-numbered rows (i.e., pixel 2, pixel 4, ...) are divided into the second group.

[0055] The readout module 200 includes a first comparator 2001, a second comparator 2002, and a mode switching submodule. The positive input terminal of the first comparator 2001 is connected to the first reference signal Vref_1, and the positive input terminal of the second comparator 2002 is connected to the second reference signal Vref_2; the mode switching submodule includes a first electrical signal output line 2010, a second electrical signal output line 2011, a first reset signal input line 2012, a second reset signal input line 2013, a first switch S1, a second switch S2, and a third switch S3. Among them, the output end of the first group of pixels (i.e., the second end of the signal output unit 110 in the first group of pixels) is connected to the negative input end of the first comparator 2001 through the first electrical signal output line 2010; the output end of the second group of pixels (i.e., the second end of the signal output unit 110 in the second group of pixels) is connected to the negative input end of the second comparator 2002 through the second electrical signal output line 2011; the first switch S1 is arranged between the first electrical signal output line 2010 and the second electrical signal output line 2011; the input end of the first group of pixels is connected to the output end of the first comparator 2001 through the first reset signal input line 2012; the input end of the second group of pixels is connected to the second comparator 2002 through the second reset signal line 2013; the second switch S2 is arranged between the first reset signal input line 2012 and the second reset signal line 2013; the third switch S3 is arranged on the first reset signal input line 2012, wherein one end of the third switch S3 is connected to the input end of the first group of pixels and the second switch S2, and the other end is connected to the output end of the first comparator 2001.

[0056] When the first switch S1 and the second switch S2 are both turned on and the third switch S3 is turned off, the mode switching submodule operates in the first state. Accordingly, the first electrical signal output line 2010 and the second electrical signal output line 2011 are short-circuited, so that the output end of each pixel in the first group and the second group is simultaneously connected to the negative input end of the first comparator 2001 and the negative input end of the second comparator 2002; the first reset signal input line 2012 and the second reset signal line 2013 are short-circuited, and at the same time, the first reset signal input line 2012 is disconnected from the output end of the first comparator 2001, so that the input end of each pixel in the first group and the second group is connected to the output end of the second comparator 2002.

[0057] When the first switch S1 and the second switch S2 are both disconnected and the third switch S3 is turned on, the mode switching submodule operates in the second mode. Accordingly, the output end of the first group of pixels is connected to the negative input end of the first comparator 2001, the input end of the first group of pixels is connected to the output end of the first comparator 2001, the output end of the second group of pixels is connected to the negative input end of the second comparator 2002, and the input end of the second group of pixels is connected to the output end of the second comparator 2002.

[0058] It should be noted that the first switch S1, the second switch S2 and the third switch S3 are preferably implemented by CMOS transistors, but those skilled in the art can understand that other types of switches suitable for image sensors also fall within the protection scope of the present invention. For the sake of simplicity, all possible switch types are not listed one by one here.

[0059] There are many ways to implement the photoelectric conversion unit, signal output unit and reset unit in the pixel. In a preferred embodiment, Figure 2As shown, the photoelectric conversion unit 100 is implemented by a light-emitting diode, the positive electrode of the light-emitting diode is grounded, and the negative electrode is connected to the signal output unit and the reset unit respectively. Correspondingly, the pixel signal of the pixel is the negative electrode voltage signal of the light-emitting diode. The signal output unit includes a source follower transistor 1101 and a pixel selection transistor 1102, wherein the first end of the source follower transistor 1101 is connected to the power supply, the second end of the source follower transistor 1101 is connected to the first end of the pixel selection transistor 1102, the third end of the source follower transistor 1101 is connected to the negative electrode of the photodiode as the first end of the signal output unit, the second end of the pixel selection transistor 1102 is connected to the corresponding readout module 200 as the second end of the signal output unit, and the third end of the pixel selection transistor 1102 is used to receive a first control signal for controlling its conduction or disconnection, wherein when the pixel selection transistor 1102 is turned on, the source follower transistor 1101 transmits the negative electrode voltage signal of the photodiode read by it to the readout module 200 through the pixel selection transistor 1102. The reset unit 120 includes a reset transistor 1201 and a reset selection transistor 1202, wherein the first end of the reset transistor 1201 is connected to a power supply, the second end of the reset transistor 1201 is connected to the negative electrode of the photodiode as the first end of the reset unit, the third end of the reset transistor 1201 is connected to the second end of the reset selection transistor 1202, the first end of the reset selection transistor 1202 is connected to the corresponding readout module 200 as the second end of the reset unit, and the third end of the reset selection transistor 1202 is used to receive a second control signal for controlling its on or off, wherein when the first end of the reset selection transistor 1202 receives the reset signal and the reset transistor 1202 is turned on, the reset transistor 1201 resets the photodiode according to the reset signal. It should be noted that the present invention does not impose any limitation on the specific types of the source follower transistor 1101, the pixel selection transistor 1102, the reset transistor 1201, and the reset selection transistor 1202, for example, they can be common PMOS transistors or NMOS transistors. If the source follower transistor 1101, the pixel selection transistor 1102, the reset transistor 1201, and the reset selection transistor 1202 are all implemented by PMOS transistors, the first ends of the source follower transistor 1101, the pixel selection transistor 1102, the reset transistor 1201, and the reset selection transistor 1202 are all drains, the second ends are all sources, and the third ends are all gates. If the source follower transistor 1101, the pixel selection transistor 1102, the reset transistor 1201, and the reset selection transistor 1202 are all implemented by NMOS transistors, the first ends of the source follower transistor 1101, the pixel selection transistor 1102, the reset transistor 1201, and the reset selection transistor 1202 are all sources, the second ends are all drains, and the third ends are all gates. Figure 3 yes Figure 2The equivalent circuit diagram of the structure shown in FIG. 1 working in the first pulse train output mode is as follows: Figure 4 yes Figure 2 The equivalent circuit diagram of the structure shown working in the second pulse train output mode.

[0060] The following will Figure 2 Taking the structure shown in FIG. 1 as an example, the working timing of the structure in the first pulse sequence output mode and the second pulse sequence output mode is described, wherein: Figure 5 yes Figure 2 The working timing diagram of the structure shown in the first pulse train output mode is: Figure 6 yes Figure 2 The structure shown in the figure is in the working timing diagram of the second pulse sequence output mode. It should be noted that (1) Figure 2 The source follower transistor 1101, the pixel selection transistor 1102, the reset transistor 1201 and the reset selection transistor 1202 are all implemented by PMOS transistors; (2) Only four frames are drawn in the working timing diagram for schematic illustration.

[0061] like Figure 5As shown, in each frame, the readout module sequentially reads out the pixel signals of each pixel in the pixel module. Taking the first frame as an example, firstly, the first control signal Row_sel_1 applied to the gate of the pixel selection transistor 1102 in pixel 1 and the second control signal Rst_sel_1 applied to the gate of the reset selection transistor 1202 are sequentially set to high level pulses. Among them, when the first control signal Row_sel_1 is a high level pulse, the pixel selection transistor 1102 in pixel 1 is turned on, and the cathode voltage signal of the light emitting diode 100 in pixel 1 is read out to the negative input terminal of the first comparator and the negative input terminal of the second comparator via the source follower transistor 1101 and the pixel selection transistor 1102. Based on the comparison result of the cathode voltage signal of the light emitting diode 100 with the first reference signal and the second reference signal, the output terminals of the first comparator and the second comparator output corresponding level signals. When the second control signal Rst_sel_1 is a high level pulse, the reset selection transistor 1202 in pixel 1 is turned on. During the period when the reset selection transistor 1202 is turned on, if the output terminal of the second comparator outputs a high level signal, the reset transistor 1201 is triggered to reset the light emitting diode 100. If the output terminal of the second comparator outputs a low level signal, the light emitting diode 100 continues to be exposed. Then, the first control signal Row_sel_2 applied to the gate of the pixel selection transistor 1102 in pixel 2 and the second control signal Rst_sel_2 applied to the gate of the reset selection transistor 1202 are sequentially set to high level pulses. Among them, when the first control signal Row_sel_2 is a high level pulse, the pixel selection transistor 1102 in pixel 2 is turned on, and the negative voltage signal of the light emitting diode 100 in pixel 2 is read out to the negative input terminal of the first comparator and the negative input terminal of the second comparator via the source follower transistor 1101 and the pixel selection transistor 1102. Based on the comparison result of the negative voltage signal of the light emitting diode 100 with the first reference signal and the second reference signal, the output terminals of the first comparator and the second comparator output corresponding level signals. When the second control signal Rst_sel_2 is a high level pulse, the reset selection transistor 1202 in pixel 2 is turned on. During the period when the reset selection transistor 1202 is turned on, if the output terminal of the second comparator outputs a high level signal, the reset transistor 1201 is triggered to reset the light emitting diode 100. If the output terminal of the second comparator outputs a low level signal, the light emitting diode 100 continues to be exposed. The same is true for pixel 3, pixel 4, etc., until the pixel signals of all pixels are read out and the first frame ends. Next, the image of the subsequent frame is read in the same way. Correspondingly, the level signal output by the first comparator constitutes the first pulse sequence Output_1, and the level signal output by the second comparator constitutes the second pulse sequence Output_2. Figure 5It can be seen from the first pulse sequence Output_1 and the second pulse sequence Output_2 that by the end of the fourth frame, the cathode voltage signals of the light emitting diodes 100 in pixels 1, 2 and 4 have not dropped to the first reference signal, so when reading the pixel signals of pixels 1, 2 and 4, the first comparator and the second comparator both output low-level signals. The cathode voltage signal of the light emitting diode 100 in pixel 3 drops to the first reference signal in the second frame, which triggers the first comparator to output a high-level signal. As the exposure time increases, the cathode voltage signal of the light emitting diode 100 in pixel 3 drops to the second reference signal in the fourth frame, which triggers the second comparator to output a high-level signal. The high-level signal reaches the reset transistor 1201 through the turned-on reset selection transistor 1202, and triggers it to reset the light emitting diode 100 in pixel 3. When the first pulse sequence Output_1 and the second pulse sequence Output_2 are subsequently processed, the time difference between the two high-level signals corresponding to the pixel 3 in the first pulse sequence Output_1 and the second pulse sequence Output_2 is obtained by differential operation, and the image of the pixel 3 is formed according to the time difference. Since the time when the cathode voltage signal of the light-emitting diode 100 in the pixel 3 drops from the first reference signal to the second reference signal (i.e., the time difference between the two high-level signals corresponding to the pixel 3 in the first pulse sequence Output_1 and the second pulse sequence Output_2) is not affected by the noise introduced in the pixel reset and the pixel signal transmission path, the noise introduced in the pixel reset and the pixel signal transmission path is suppressed, thereby effectively improving the signal-to-noise ratio performance of the image sensor, and further improving the image quality of the image sensor.

[0062] like Figure 6As shown, in each frame, the readout module reads out the pixel signals of the pixels in the first group and the second group in the pixel module in parallel. In this embodiment, the timing of pixel 1 and pixel 2 in each frame is the same, and the timing of pixel 3 and pixel 4 is the same, so that the pixel signals of the pixels in the first group and the second group can be read out at the same time. Taking the first frame as an example, firstly, the first control signal Row_sel_1 applied to the gate of the pixel selection transistor 1102 in pixel 1 and the second control signal Rst_sel_1 applied to the gate of the reset selection transistor 1202 are high level pulses in sequence. Among them, when the first control signal Row_sel_1 is a high level pulse, the pixel selection transistor 1102 in pixel 1 is turned on, and the negative voltage signal of the light emitting diode 100 in pixel 1 is read out to the negative input terminal of the first comparator via the source follower transistor 1101 and the pixel selection transistor 1102. Based on the comparison result of the negative voltage signal of the light emitting diode 100 and the first reference signal, the output terminal of the first comparator outputs a corresponding level signal. When the second control signal Rst_sel_1 is a high level pulse, the reset selection transistor 1202 in pixel 1 is turned on. During the period when the reset selection transistor 1202 is turned on, if the output terminal of the first comparator outputs a high level signal, the reset transistor 1201 is triggered to reset the light emitting diode 100. If the output terminal of the first comparator outputs a low level signal, the light emitting diode 100 continues to be exposed. Pixel 2 has the same timing as pixel 1, wherein when the first control signal Row_sel_2 applied to the gate of the pixel selection transistor 1102 in pixel 2 is a high level pulse, the pixel selection transistor 1102 in pixel 2 is turned on, and the negative voltage signal of the light emitting diode 100 in pixel 2 is read out to the negative input terminal of the second comparator via the source follower transistor 1101 and the pixel selection transistor 1102. Based on the comparison result of the negative voltage signal of the light emitting diode 100 and the second reference signal, the output terminal of the second comparator outputs a corresponding level signal. When the second control signal Rst_sel_2 applied to the gate of the reset selection transistor 1202 in pixel 2 is a high-level pulse, the reset selection transistor 1202 in pixel 2 is turned on. During the period when the reset selection transistor 1202 is turned on, if the output end of the second comparator outputs a high-level signal, the reset transistor 1201 is triggered to reset the light-emitting diode 100. If the output end of the second comparator outputs a low-level signal, the light-emitting diode 100 continues to be exposed. The same process is applied to pixel 3, pixel 4, and so on until the pixel signals of all pixels are read out and the first frame ends. Next, the images of subsequent frames are read in the same way. Accordingly, the level signal output by the first comparator constitutes the first pulse sequence Output_1, and the level signal output by the second comparator constitutes the second pulse sequence Output_2. According to Figure 6It can be seen from the first pulse sequence Output_1 and the second pulse sequence Output_2 that by the end of the fourth frame, the cathode voltage signals of the light emitting diodes 100 in pixels 2, 3 and 4 have not dropped to the first reference signal, so when reading the pixel signals of pixels 2, 3 and 4, the first comparator and the second comparator both output low-level signals. The cathode voltage signal of the light emitting diode 100 in pixel 1 drops to the first reference signal in the first frame, which correspondingly triggers the first comparator to output a high-level signal and resets the light emitting diode 100 in pixel 1 based on the high-level signal. After the reset, the light emitting diode 100 continues to be exposed. As the exposure time increases, the cathode voltage signal of the light emitting diode 100 in pixel 1 drops to the first reference signal in the third frame, which correspondingly triggers the first comparator to output a high-level signal again and resets the light emitting diode 100 in pixel 1 based on the high level. When the first pulse sequence Output_1 is subsequently processed, the image of pixel 1 is formed according to the time difference between the two high-level signals corresponding to pixel 1 in the first pulse sequence Output_1. Since the readout module can read out the pixel signals in the first group and the second group of pixels in parallel, the time required for each frame can be effectively reduced, thereby increasing the frame rate of the pulse sequence image sensor. In particular, when the number of pixels in the first group and the second group is the same, the time required for each frame can be halved and the frame rate can be doubled.

[0063] The present invention also provides a pulse sequence image sensor, the pulse sequence image sensor comprising:

[0064] A pixel module and a readout module connected to the pixel module;

[0065] The pixel module includes more than two pixels, and the pixels are used to convert optical signals into electrical signals and output them;

[0066] The readout module includes a first comparator, a second comparator and a signal line sub-module, wherein each pixel in the pixel module is connected to the first comparator and the second comparator through the signal line sub-module, and the first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold of the electrical signal.

[0067] The various components of the above-mentioned pulse sequence image sensor will be described in detail below.

[0068] Specifically, the pulse sequence image sensor provided by the present invention includes a pixel module and a readout module connected to the pixel module. The structure of the pixel module can refer to the relevant part of the content in the pulse sequence image sensor in the previous text, and for the sake of simplicity, it will not be repeated here. The readout module includes a first comparator, a second comparator and a signal line submodule. The structure of the first comparator and the second comparator can refer to the relevant part of the content in the pulse sequence image sensor in the previous text, and for the sake of simplicity, it will not be repeated here. The signal line submodule includes a signal line for connecting each pixel in the pixel module with the comparator. The present invention does not impose any restrictions on the specific number and layout of the signal line, as long as it can be realized that the output end of each pixel in the pixel module is connected to the negative input end of the first comparator and the negative input end of the second comparator, and the input end of each pixel in the pixel module is connected to the output end of the second comparator. When the pulse sequence image sensor provided by the present invention is working, the second reference signal of the second comparator is set to be equal to the threshold value of the pixel signal, and the first reference signal is set to be greater than the second reference signal. In addition, the working timing of the pulse sequence image sensor provided by the present invention can refer to the working timing of the pulse sequence image sensor working in the first pulse sequence output mode in the foregoing text, and for the sake of brevity, it will not be repeated here.

[0069] Accordingly, the present invention also provides an electronic device, which includes the aforementioned pulse sequence image sensor. The electronic device provided by the present invention can be a pulse camera, a high-speed camera, an audio / video player, a navigation device, a fixed position terminal, an entertainment unit, a smart phone, a communication device, a device in a motor vehicle, a camera, a sports or wearable camera, a detection device, a flight device, a medical device, a security device, etc. For the sake of simplicity, all possible types of electronic devices provided by the present invention are no longer listed one by one. Due to the use of the aforementioned pulse sequence image sensor, the electronic device provided by the present invention has better performance accordingly.

[0070] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any figure mark in the claims should not be regarded as limiting the claims involved. In addition, it is obvious that the word "comprising" does not exclude other components, units or steps, and the singular does not exclude the plural. Multiple components, units or devices stated in the system claim may also be implemented by one component, unit or device through software or hardware.

[0071] The above disclosures are only some preferred embodiments of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A pulse sequence image sensor, the pulse sequence image sensor comprising: A pixel module and a readout module connected to the pixel module; The pixel module includes more than two pixels, the more than two pixels are divided into a first group and a second group, and the pixels are used to convert optical signals into electrical signals and output them; The readout module includes a first comparator, a second comparator and a mode switching submodule, wherein the first comparator, the second comparator and the mode switching submodule are configured as follows: When the mode switching submodule operates in the first state, each pixel in the pixel module is connected to the first comparator and the second comparator respectively, and the first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold value of the electrical signal; When the mode switching submodule operates in the second state, each pixel in the first group is connected to the first comparator, each pixel in the second group is connected to the second comparator, and the first reference signal of the first comparator and the second reference signal of the second comparator are both equal to the threshold of the electrical signal.

2. The pulse sequence image sensor according to claim 1, wherein: The pulse sequence image sensor includes a pixel array and a readout circuit; Each column of pixels in the pixel array constitutes a pixel module; The readout circuit includes the readout modules, which are the same in number as the pixel modules and correspond one to one, and each of the readout modules is connected to the corresponding pixel module.

3. The pulse sequence image sensor according to claim 2, wherein: The pixels located at odd-numbered rows in each column of the pixels are divided into one of the first group and the second group, and the pixels located at even-numbered rows are divided into the other of the first group and the second group.

4. The pulse sequence image sensor according to any one of claims 1 to 3, wherein: Each of the pixels comprises an input terminal for receiving a reset signal, and an output terminal for outputting the electrical signal; Each pixel in the pixel module is connected to the first comparator and the second comparator respectively, including: the output end of each pixel in the pixel module is connected to the negative input end of the first comparator and the negative input end of the second comparator respectively, and the input end of each pixel in the pixel module is connected to the output end of the second comparator; Each pixel in the first group is connected to the first comparator, and each pixel in the second group is connected to the second comparator, including: the output end of each pixel in the first group is connected to the negative input end of the first comparator, the input end of each pixel in the first group is connected to the output end of the first comparator, the output end of each pixel in the second group is connected to the negative input end of the second comparator, and the input end of each pixel in the second group is connected to the output end of the second comparator.

5. The pulse sequence image sensor according to claim 4, wherein: Each of the pixels comprises a photoelectric conversion unit, a signal output unit and a reset unit; The photoelectric conversion unit is used to convert the optical signal into an electrical signal; The signal output unit is used to output the electrical signal, wherein a first end of the signal output unit is connected to the photoelectric conversion unit, and a second end of the signal output unit serves as an output end of the pixel; The reset unit is used to reset the photoelectric conversion unit according to the reset signal, wherein a first end of the reset unit is connected to the photoelectric conversion unit, and a second end of the reset unit serves as an input end of the pixel.

6. The pulse sequence image sensor according to claim 5, wherein: The photoelectric conversion unit includes a photodiode, wherein the anode of the photodiode is grounded, and the cathode of the photodiode is connected to the first end of the signal output unit and the first end of the reset unit; The electrical signal is a cathode voltage signal of the photodiode.

7. The pulse sequence image sensor according to claim 6, wherein: The signal output unit includes a source follower transistor and a pixel selection transistor; The first end of the source follower transistor is connected to a power supply, the second end of the source follower transistor is connected to the first end of the pixel selection transistor, and the third end of the source follower transistor is connected to the cathode of the photodiode as the first end of the signal output unit; The second end of the pixel selection transistor is connected to the corresponding readout module as the second end of the signal output unit, and the third end of the pixel selection transistor is used to receive a first control signal for controlling the pixel selection transistor to be turned on or off; When the pixel selection transistor is turned on, the source follower transistor outputs the cathode voltage signal of the photodiode read by it to the corresponding readout module through the pixel selection transistor.

8. The pulse sequence image sensor according to claim 6, wherein: The reset unit includes a reset transistor and a reset selection transistor; The first end of the reset transistor is connected to a power supply, the second end of the reset transistor is connected to the cathode of the photodiode as the first end of the reset unit, and the third end of the reset transistor is connected to the second end of the reset selection transistor; The first end of the reset selection transistor is connected to the corresponding readout module as the second end of the reset unit, and the third end of the reset selection transistor is used to receive a second control signal for controlling the on or off of the reset selection transistor; When the first end of the reset selection transistor receives the reset signal and the reset transistor is turned on, the reset transistor resets the photodiode according to the reset signal.

9. The pulse sequence image sensor according to claim 4, wherein: The mode switching submodule includes a first electrical signal output line, a second electrical signal output line, a first reset signal input line, a second reset signal input line, a first switch, a second switch and a third switch; The output terminals of the pixels in the first group are connected to the negative input terminal of the first comparator through the first electrical signal output line, the output terminals of the pixels in the second group are connected to the negative input terminal of the second comparator through the second electrical signal output line, and the first switch is arranged between the first electrical signal output line and the second electrical signal output line; The input terminals of the pixels in the first group are connected to the output terminals of the first comparator through the first reset signal input line, the input terminals of the pixels in the second group are connected to the output terminals of the second comparator through the second reset signal input line, the second switch is arranged between the first reset signal input line and the second reset signal input line, and the third switch is arranged on the first reset signal input line and between the second switch and the first comparator; Among them, when the first switch and the second switch are both turned on and the third switch is turned off, the mode switching submodule operates in the first state; when the first switch and the second switch are both turned off and the third switch is turned on, the mode switching submodule operates in the second state.

10. A pulse sequence image sensor, the pulse sequence image sensor comprising: A pixel module and a readout module connected to the pixel module; The pixel module includes more than two pixels, and the pixels are used to convert optical signals into electrical signals and output them; The readout module includes a first comparator, a second comparator and a signal line sub-module, wherein each pixel in the pixel module is connected to the first comparator and the second comparator through the signal line sub-module, and the first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold of the electrical signal.

11. An electronic device comprising the pulse sequence image sensor according to any one of claims 1 to 10.

Images