Decoding circuit, decoding method and passive internet-of-things tag

Abstract

The embodiment of the invention provides a decoding circuit, a decoding method and a passive internet of things tag, and the circuit comprises a frame synchronization module which is used for transmitting a downlink instruction, an effective frame signal and a symbol feature sequence to a symbol synchronization module; the symbol synchronization module is used for sending the symbol synchronization signal to the symbol decoding module; the convolution result is a convolution output value corresponding to each group of symbol feature sequences; and the symbol decoding module is used for reading convolution output values at two moments at each optimal judgment moment based on the symbol synchronization signal, comparing the convolution output values at the two moments based on a preset comparison rule, generating symbol judgment results, and combining the symbol judgment results to generate effective data. In the mode, effective data can be stably extracted in a complex communication environment, so that the decoding sensitivity and the anti-interference capability of the passive Internet of Things tag in the complex environment are improved, and the decoding precision and the stability of the passive Internet of Things tag are further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of passive Internet of Things, and in particular to a decoding circuit, a decoding method and a passive Internet of Things tag. Background Art

[0002] With the rapid development of the Internet of Things, passive IoT technology has become an important direction to meet the needs of low-power, large-scale, and long-distance communications. The 3GPP standards organization (International Telecommunication Standards Organization) is developing a cellular network IoT technology that defines passive tags that are powered by environmental energy (such as electromagnetic fields or light energy) and communicate with base stations through cellular networks. In order to meet the needs of wider coverage in business scenarios, passive IoT tags need to have higher receiving sensitivity and stronger anti-interference capabilities.

[0003] In the prior art, RFID tags usually use envelope detection as an analog demodulation circuit. Although its circuit is simple and low in cost, the envelope detector is a nonlinear device with weak anti-aliasing and anti-interference capabilities. When there is strong interference or poor channel conditions in the communication environment, the detection signal may have glitches or distortion, and the symbol period and duty cycle may change, resulting in failure of subsequent digital circuit demodulation and decoding. The receiving sensitivity of existing tags is generally only -22dBm to -24dBm, which is difficult to meet the needs of complex application scenarios. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a decoding circuit, a decoding method and a passive Internet of Things tag, which can improve the anti-interference ability and receiving sensitivity of the decoding circuit, and can stably extract valid data in a complex communication environment, thereby realizing reliable decoding of the passive Internet of Things tag in a low signal-to-noise ratio and high interference environment.

[0005] In the first aspect, an embodiment of the present invention provides a decoding circuit, which is applied to a passive Internet of Things tag; the decoding circuit includes: a frame synchronization module, a symbol synchronization module and a symbol decoding module connected in sequence; the frame synchronization module is used to identify and mark the valid frame processing range of the received downlink instruction, and generate a valid frame signal; based on the system clock signal, two groups of symbol feature sequences corresponding to the system clock signal are extracted and generated; noise in the downlink instruction is eliminated to obtain an updated downlink instruction; the downlink instruction, the valid frame signal and the symbol feature sequence are sent to the symbol synchronization module; the symbol synchronization module is used to perform a convolution operation on the downlink instruction and the symbol feature sequence based on the valid frame processing range in the valid frame signal to generate a convolution result; a symbol synchronization signal is generated based on the convolution result, and the symbol synchronization signal is sent to the symbol decoding module; the convolution result is the convolution output value corresponding to each group of symbol feature sequences; the symbol synchronization signal is used to characterize the optimal decision moment corresponding to each symbol; the symbol decoding module is used to read the convolution output values ​​at two moments at each optimal decision moment based on the symbol synchronization signal, compare the convolution output values ​​at the two moments based on a preset comparison rule, generate a symbol decision result, and merge the symbol decision results to generate valid data.

[0006] Furthermore, the frame synchronization module includes a noise detection unit; the noise detection unit is connected to the symbol synchronization module; the noise detection unit includes a connected edge detection subunit and a counter; the edge detection subunit is used to detect the edge in the downlink instruction; based on the system clock signal, the level length between every two edges is determined; whether the level length is within the preset level length range, if not, the signal that is not within the preset level length range is determined to be noise; the signal of the downlink instruction corresponding to the noise is marked as invalid, and an updated downlink instruction is obtained; the downlink instruction is sent to the symbol synchronization module; the counter is used to count the number of noises of the noise detected by the edge detection subunit.

[0007] Furthermore, the frame synchronization module also includes a locator detection unit; the locator detection unit is connected to the noise detection unit; the locator detection unit is used to receive the downlink instruction sent by the noise detection unit; detect and mark the falling edge position of the falling edge in the downlink instruction; based on the system clock signal, record the low level width after each falling edge; determine whether the low level width is within the preset delimiter width range, if so, based on the preset downlink instruction frame protocol, determine the falling edge position as a preamble or a postamble; determine the valid frame starting position based on the preamble; determine the valid frame ending position based on the postamble; generate a valid frame processing range based on the valid frame starting position and the valid frame ending position; generate a valid frame signal based on the valid frame processing range; the preset downlink instruction frame protocol includes the frame structure of the downlink instruction and its corresponding fixed length.

[0008] Furthermore, the frame structure includes a preamble, a calibration symbol, a payload and a post-amble; the frame synchronization module also includes a calibration symbol detection unit; the calibration symbol detection unit is respectively connected to the noise detection unit, the locator detection unit and the symbol synchronization module; the calibration symbol detection unit is used to determine the calibration symbol range of the calibration symbol based on the valid frame start position in the valid frame signal and the preset downlink instruction frame protocol; within the calibration symbol range, the downlink instruction is sampled based on the system clock signal, and the level value corresponding to each sampling point is recorded; the level value is symbol 1 or symbol 0; each symbol 1 is sampled to generate a symbol 1 characteristic waveform sequence; each symbol 0 is sampled to generate a symbol 0 waveform sequence; the symbol 1 characteristic waveform sequence is converted into a symbol 1 characteristic sequence, the symbol 0 waveform sequence is converted into a symbol 0 characteristic sequence, and the symbol 1 characteristic sequence and the symbol 0 characteristic sequence are sent to the symbol synchronization module.

[0009] Furthermore, the symbol synchronization module includes a first matched filter and a second matched filter; the first matched filter and the second matched filter are respectively connected to the frame synchronization module; the first matched filter is used to receive the symbol 0 feature sequence; based on a preset convolution formula, the matching degree between the downlink instruction and the symbol 0 feature sequence is calculated, and the first convolution result is output; the peak position of the first convolution result is determined to be the end position of symbol 0; the second matched filter is used to receive the symbol 1 feature sequence; based on a preset convolution formula, the matching degree between the downlink instruction and the symbol 1 feature sequence is calculated, and the second convolution result is output; the peak position of the second convolution result is determined to be the end position of symbol 1.

[0010] Furthermore, the symbol synchronization module includes a first peak detection unit and a second peak detection unit; the first peak detection unit is respectively connected to the first matched filter and the symbol decoding module; the second peak detection unit is respectively connected to the second matched filter and the symbol decoding module; the first peak detection unit is used to receive the first convolution result, and based on a preset peak calculation method, determine the first peak position of the first convolution result as the end position of symbol 0 in the downlink instruction; send the first convolution result to the symbol decoding module; the second peak detection unit is used to receive the second convolution result, and based on a preset peak calculation method, determine the second peak position of the second convolution result as the end position of symbol 1 in the downlink instruction; send the second convolution result to the symbol decoding module.

[0011] Furthermore, the symbol synchronization module also includes a clock recovery unit; the clock recovery unit is respectively connected to the first peak detection unit, the second peak detection unit and the symbol decoding module; the clock recovery unit is used to obtain the first peak position, the second peak position and the valid frame signal; based on the first peak position and the second peak position, a peak sequence is merged to generate; based on the effective peak recognition method and the effective frame processing range, the effective peak in the peak sequence is screened out; based on the effective peak, the optimal decision time for the downlink instruction is determined; at each optimal judgment, a synchronization pulse signal is generated, each synchronization pulse signal is merged to generate a symbol synchronization signal; the symbol synchronization signal is sent to the symbol decoding module.

[0012] Furthermore, the symbol decoding module is also used to obtain, at each optimal decision moment, a convolution output value at the first moment corresponding to the first convolution result and a convolution output value at the second moment corresponding to the second convolution result; compare the convolution output value at the first moment and the convolution output value at the second moment; if the convolution output value at the first moment is greater than the convolution output value at the second moment, determine that the symbol decision result corresponding to the current symbol is 0; if the convolution output value at the first moment is less than the convolution output value at the second moment, determine that the symbol decision result corresponding to the current symbol is 1; based on the valid frame processing range and the preset downlink instruction frame protocol, merge the symbol decision results corresponding to the payload to generate valid data.

[0013] In a second aspect, an embodiment of the present invention provides a decoding method, which is applied to the above-mentioned decoding circuit; the decoding method includes: identifying and marking the valid frame processing range of the received downlink instruction through a frame synchronization module to generate a valid frame signal; extracting and generating two groups of symbol feature sequences corresponding to the system clock signal based on the system clock signal; removing noise in the downlink instruction to obtain an updated downlink instruction; sending the downlink instruction, the valid frame signal and the symbol feature sequence to the symbol synchronization module; through the symbol synchronization module, based on the valid frame processing range in the valid frame signal, the downlink instruction and the symbol feature sequence perform a convolution operation to generate a convolution result; based on the convolution result, a symbol synchronization signal is generated, and the symbol synchronization signal is sent to the symbol decoding module; the convolution result is the convolution output value corresponding to each group of symbol feature sequences; the symbol synchronization signal is used to characterize the optimal decision moment corresponding to each symbol; through the symbol decoding module, based on the symbol synchronization signal, reads the convolution output values ​​at two moments at each optimal decision moment, compares the convolution output values ​​at the two moments based on a preset comparison rule, generates a symbol decision result, and merges the symbol decision results to generate valid data.

[0014] In a third aspect, an embodiment of the present invention provides a passive Internet of Things tag, including a passive Internet of Things tag body; and also including the above-mentioned decoding circuit; the decoding circuit is arranged in the passive Internet of Things tag body.

[0015] The embodiment of the present invention provides a decoding circuit, a decoding method and a passive Internet of Things tag. The decoding circuit includes: a frame synchronization module, a symbol synchronization module and a symbol decoding module connected in sequence; the frame synchronization module is used to identify and mark the effective frame processing range of the received downlink instruction and generate a valid frame signal; based on the system clock signal, two groups of symbol feature sequences corresponding to the system clock signal are extracted and generated; noise in the downlink instruction is eliminated to obtain an updated downlink instruction; the downlink instruction, the effective frame signal and the symbol feature sequence are sent to the symbol synchronization module; the symbol synchronization module is used to perform a convolution operation on the downlink instruction and the symbol feature sequence based on the effective frame processing range in the effective frame signal to generate a convolution result; a symbol synchronization signal is generated based on the convolution result, and the symbol synchronization signal is sent to the symbol decoding module; the convolution result is the convolution output value corresponding to each group of symbol feature sequences; the symbol synchronization signal is used to characterize the optimal decision moment corresponding to each symbol; the symbol decoding module is used to read the convolution output values ​​at two moments at each optimal decision moment based on the symbol synchronization signal, compare the convolution output values ​​at the two moments based on a preset comparison rule, generate a symbol decision result, and merge the symbol decision results to generate valid data. In this method, the frame synchronization module can identify and mark the effective frame processing range of the received downlink instruction, remove the clutter signal, and provide a clean and effective signal input for the subsequent symbol synchronization and symbol decoding; through the matching filter and peak detection unit of the symbol synchronization module, the convolution result of the demodulated signal and the symbol feature sequence is accurately calculated, the end position of each symbol is located, and then the synchronization signal is generated and the best decision moment is ensured; finally, the symbol decoding module performs symbol decision based on the convolution output value to generate high-precision valid data. The receiving sensitivity of passive IoT tags can be improved, and the anti-interference ability can be enhanced, so as to realize reliable decoding of long-distance and weak signals; at the same time, by optimizing the filter structure and dynamically configuring the tap order, the power consumption and complexity of the circuit implementation can be reduced, meeting the requirements of low cost, low power consumption and high reliability in large-scale IoT applications.

[0016] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of a decoding circuit provided by an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of another decoding circuit provided by an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of a related receiver circuit provided by an embodiment of the present invention;

[0022] Figure 4 A simulation waveform diagram of a clock recovery unit provided by an embodiment of the present invention;

[0023] Figure 5 A simulation waveform diagram of a symbol decoding module provided by an embodiment of the present invention;

[0024] Figure 6 A flowchart of a decoding method provided by an embodiment of the present invention;

[0025] Figure 7 Schematic diagram of a passive IoT tag provided in an embodiment of the present invention.

[0026] Icons: 11-frame synchronization module; 12-symbol synchronization module; 13-symbol decoding module; 21-noise detection unit; 22-edge detection subunit; 23-counter; 24-locator detection unit; 25-calibrator detection unit; 26-first matched filter; 27-second matched filter; 28-first peak detection unit; 29-second peak detection unit; 210-clock recovery unit; 31-passive IoT tag body; 32-decoding circuit. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Traditional wireless communication services are becoming saturated, but the IoT market still has huge potential. Existing IoT technologies still face challenges in terms of connection scale, application cost, energy supply and low carbon environment. In large-scale deployment applications, traditional power supply methods are unable to meet the needs due to restrictions in terms of environment, cost, energy conservation and environmental protection, and passive IoT has become an effective solution.

[0029] Currently, the mature passive IoT representative technology RFID has limitations in communication distance and networking mode. The communication distance is limited by the energy supply mode and energy conversion efficiency. RFID needs to obtain energy from the radio frequency field. Due to the energy conversion efficiency, it is impossible to obtain enough energy from the radio frequency field of the reader at a long distance. The communication distance is generally more than 20 meters.

[0030] RFID tags need to be designed with low power consumption, and usually use envelope detection as an analog demodulation circuit. Since the envelope detector is a nonlinear device, it has weak anti-aliasing and anti-interference capabilities. When there is strong interference in the communication environment or the channel is poor and the signal-to-noise ratio is low, the signal output by the detection circuit may have glitches or distortion, and the symbol period and duty cycle may also change.

[0031] The decoding circuit provided in the present application can stably extract valid data in a complex communication environment, thereby realizing reliable decoding of passive IoT tags in a low signal-to-noise ratio and high interference environment.

[0032] To facilitate understanding of this embodiment, the embodiment of the present invention is described in detail below.

[0033] Embodiment 1:

[0034] Figure 1 A schematic diagram of a decoding circuit provided by an embodiment of the present invention.

[0035] The decoding circuit is applied to passive IoT tags.

[0036] The 5G+ base station sends downlink signaling to the tag to control the functions of the passive IoT tag and send instructions.

[0037] Passive IoT tags do not have independent power sources. They can obtain energy from the environment (electromagnetic fields, light energy, etc.) and use cellular networks to communicate with base stations.

[0038] Reference Figure 1 The decoding circuit includes: a frame synchronization module 11, a symbol synchronization module 12 and a symbol decoding module 13 which are connected in sequence.

[0039] The frame synchronization module 11 is used to identify and mark the valid frame processing range of the received downlink instruction and generate a valid frame signal; extract and generate two sets of symbol feature sequences corresponding to the system clock signal based on the system clock signal; eliminate noise in the downlink instruction to obtain an updated downlink instruction; and send the downlink instruction, the valid frame signal and the symbol feature sequence to the symbol synchronization module 12.

[0040] Here, the frame synchronization module 11 identifies the valid frame start position and valid frame end position in the downlink instruction by detecting the preamble and postamble in the downlink instruction. Use the downlink instruction frame protocol (including the frame structure and the corresponding fixed length) to verify whether the preamble and postamble meet the standard to ensure the accuracy of frame synchronization. Mark the frame processing range according to the detected preamble and postamble, and generate a valid frame signal (for marking the range of payload data). The downlink instruction frame structure includes a preamble, a calibration symbol, a payload, and a postamble.

[0041] Among them, the preamble is a synchronization signal, which is used for frame start identification and preliminary synchronization. The calibration mark is located between the preamble and the payload, providing a symbol feature sequence for the convolution operation of the matching filter. The calibration mark is usually a fixed waveform, containing the characteristic information of symbol 0 and symbol 1. The payload is the main content of the frame, containing valid data to be transmitted. The post-amble is a synchronization signal, which is used for frame end identification and frame integrity detection. The preamble and post-amble are fixed sequence waveforms, and the preamble sequence is the post-amble sequence when it is reversed. Passive IoT tags can determine whether there is a signaling sent by detecting the preamble, and can also determine the starting position of the valid signaling data. In addition, detecting the post-amble of the signaling can determine the end of the downlink signaling.

[0042] The system clock signal provides a sampling reference for downlink instructions. In the frame synchronization module 11, the waveform characteristics of symbol 0 and symbol 1 are extracted by sampling the symbol waveform in the calibration symbol, and these waveforms are converted into two sets of symbol feature sequences (symbol 0 feature sequence and symbol 1 feature sequence). The symbol feature sequence is used for the convolution operation of the symbol synchronization module 12 to ensure that the subsequent symbol synchronization module 12 can correctly identify the end position of the symbol.

[0043] The downlink instruction after removing the clutter (ie the updated downlink instruction) is used for processing in the subsequent symbol synchronization module 12 to reduce the influence of noise and interference on the decoding process and improve the signal quality.

[0044] The frame synchronization module 11 sends the updated downlink instruction after removing the clutter, the marked valid frame signal and two sets of symbol feature sequences to the symbol synchronization module 12, ensuring that the symbol synchronization module 12 receives the processed high-quality signal to improve the accuracy of subsequent processing.

[0045] In one embodiment, referring to Figure 2 The frame synchronization module 11 includes a clutter detection unit 21 ; the clutter detection unit 21 is connected to the symbol synchronization module 12 ; the clutter detection unit 21 includes a connected edge detection subunit 22 and a counter 23 .

[0046] Here, the edge detection subunit 22 is used to detect the edge in the downlink instruction. The counter 23 is used to count the number of clutter detected by the edge detection subunit 22.

[0047] The edge detection subunit 22 is used to detect the edge in the downlink instruction; determine the level length between every two edges based on the system clock signal; judge whether the level length is within the preset level length range, and if not, determine that the signal that is not within the preset level length range is noise; mark the signal of the noise corresponding to the downlink instruction as invalid, and obtain an updated downlink instruction; send the downlink instruction to the symbol synchronization module 12.

[0048] Here, the edge detection subunit 22 receives the input signal of the downlink instruction and performs real-time sampling based on the system clock signal. The level change of the detection signal is detected, and each edge position (rising edge and falling edge) of the downlink instruction is marked by identifying the transition position from high level to low level or from low level to high level.

[0049] The edge detection subunit 22 records the time interval between two consecutive edges and calculates the corresponding level length (in units of system clock cycles). By measuring the level length, the periodic characteristics of the signal can be reflected and the normal range of the signal can be determined.

[0050] Based on presetting a normal level length range according to the waveform characteristics defined in the downlink signaling frame protocol, each measured level length is compared with the preset level length range.

[0051] If the level length is within the range, it is considered a normal signal. If the level length exceeds the range, it is considered to be noise.

[0052] Each signal determined to be clutter is marked as invalid so that these abnormal signals can be ignored in subsequent processing. By removing clutter to obtain updated downlink instructions, it is ensured that the downlink instructions transmitted to the symbol synchronization module 12 do not contain interference signals, thereby improving the anti-interference ability of the overall system.

[0053] The counter 23 is used to count the number of clutter detected by the edge detection subunit 22 .

[0054] Here, each time the edge detection subunit 22 identifies a clutter, the count value of the counter 23 is increased by 1, and the statistical result can record the intensity of the clutter in the current channel in real time.

[0055] In one embodiment, referring to Figure 2 The frame synchronization module 11 further includes a locator detection unit 24 ; the locator detection unit 24 is connected to the clutter detection unit 21 .

[0056] Here, the core function of the locator detection unit 24 is to determine the valid frame range of the downlink instruction by detecting and marking the position of the delimiters (preamble and postamble) in the downlink instruction.

[0057] The locator detection unit 24 is used to receive the downlink instruction sent by the noise detection unit 21; detect and mark the falling edge position of the falling edge in the downlink instruction; based on the system clock signal, record the low-level width after each falling edge; determine whether the low-level width is within the preset delimiter width range, and if so, determine the falling edge position as a preamble or a postamble based on the preset downlink instruction frame protocol; determine the valid frame starting position based on the preamble; determine the valid frame ending position based on the postamble; generate a valid frame processing range based on the valid frame starting position and the valid frame ending position; generate a valid frame signal based on the valid frame processing range; the preset downlink instruction frame protocol includes the frame structure of the downlink instruction and its corresponding fixed length.

[0058] Here, the locator detection unit 24 receives the downlink instruction processed by the clutter detection unit 21, and identifies the waveform of the downlink instruction based on the system clock signal. The falling edge of the signal (the transition position from high level to low level) is identified, and the position of the falling edge is marked. The time point of each falling edge will be used as the starting point of the subsequent low level width count.

[0059] The length of time the low level lasts after each falling edge is recorded. The calculation of the low level width is based on the system clock cycle, and the number of clock cycles the low level lasts is determined by continuously sampling the level value.

[0060] Based on the downlink command frame protocol, a delimiter width range is preset, and each low-level width recorded is compared with the range.

[0061] If the width is within the range, the falling edge is considered to be a valid delimiter. If the width is not within the range, the position is excluded and is not used as a delimiter.

[0062] If the low level width is within the range, by further matching the waveform features of the preamble and postamble in the preset frame protocol, it is determined that the falling edge position belongs to the preamble or postamble.

[0063] At the falling edge of the marked leading code, record its time point as the starting position of the valid frame. At the falling edge of the marked trailing code, record its time point as the ending position of the valid frame.

[0064] The valid frame processing range is generated by combining the positions of the preamble and the postamble. The valid frame processing range includes the payload portion of the frame.

[0065] A valid frame signal is generated within the valid frame processing range, and the data within the valid frame processing range is valid data.

[0066] In one embodiment, referring to Figure 2 The frame synchronization module 11 further includes a calibration symbol detection unit 25; the calibration symbol detection unit 25 is connected to the clutter detection unit 21, the locator detection unit 24 and the symbol synchronization module 12 respectively.

[0067] Here, the calibration symbol detection unit 25 extracts the characteristic waveform sequences of symbol 0 and symbol 1 from the calibration symbol interval of the downlink instruction, and converts them into the local correlation sequence of the matched filter.

[0068] The calibration symbol detection unit 25 is used to determine the calibration symbol range of the calibration symbol based on the valid frame start position in the valid frame signal and the preset downlink instruction frame protocol; within the calibration symbol range, the downlink instruction is sampled based on the system clock signal, and the level value corresponding to each sampling point is recorded; the level value is symbol 1 or symbol 0; each symbol 1 is sampled to generate a symbol 1 characteristic waveform sequence; each symbol 0 is sampled to generate a symbol 0 waveform sequence; the symbol 1 characteristic waveform sequence is converted into a symbol 1 characteristic sequence, the symbol 0 waveform sequence is converted into a symbol 0 characteristic sequence, and the symbol 1 characteristic sequence and the symbol 0 characteristic sequence are sent to the symbol synchronization module 12.

[0069] Here, the calibration mark detection unit 25 receives the valid frame signal generated by the locator detection unit 24, and determines the specific range of the calibration mark in the downlink instruction according to the valid frame start position in the valid frame signal and the preset downlink instruction frame protocol. The calibration mark is a part of the frame structure immediately following the preamble.

[0070] Within the calibration symbol range, the downlink instruction is sampled based on the system clock signal, and the level value of each sampling point is recorded. The system clock signal has a fixed period, and the integrity of the waveform information is ensured through continuous sampling. The sampling result is a high level or a low level, corresponding to the symbol 1 or the symbol 0.

[0071] The level value of each sampling point within the calibration symbol range is recorded, and symbol 0 and symbol 1 are distinguished according to the level state. The level values ​​are stored in a sequence to form the complete waveform data of the calibration symbol.

[0072] The feature extraction is performed on the part of the sampling point marked as symbol 1, and the waveform change of symbol 1 is recorded. The feature extraction is performed on the part of the sampling point marked as symbol 0, and the waveform change of symbol 0 is recorded.

[0073] The symbol 1 feature waveform sequence is compressed and simplified, redundant information is removed, the core features of symbol 1 are extracted, and a concise and efficient symbol 1 feature sequence is generated. The symbol 0 feature waveform sequence is compressed and simplified, redundant information is removed, the core features of symbol 0 are extracted, and a concise and efficient symbol 0 feature sequence is generated.

[0074] The symbol 1 feature sequence and the symbol 0 feature sequence are sent to the symbol synchronization module 12 respectively.

[0075] The symbol synchronization module 12 is used to perform convolution operation based on the valid frame processing range in the valid frame signal, the downlink instruction and the symbol feature sequence to generate a convolution result; generate a symbol synchronization signal based on the convolution result, and send the symbol synchronization signal to the symbol decoding module 13; the convolution result is the convolution output value corresponding to each group of symbol feature sequences; the symbol synchronization signal is used to characterize the optimal decision time corresponding to each symbol.

[0076] Here, the symbol synchronization module 12 includes two matched filters. The symbol synchronization module 12 performs convolution operations on the updated downlink instruction and the symbol 0 feature sequence and the symbol 1 feature sequence through the matched filters, extracts the matching degree of each symbol in the downlink instruction, and finds the best decision time for each symbol.

[0077] The symbol synchronization module 12 uses a peak detection method to find the peak position of the matching degree from the convolution result. The peak position corresponds to the end time of the symbol, and generates a symbol synchronization signal (clk_recovery).

[0078] The symbol synchronization signal is used to characterize the optimal decision moment corresponding to each symbol, ensuring that the symbol decoding module 13 can make a decision on the symbol at the optimal moment, thereby improving the accuracy of decoding.

[0079] In one embodiment, referring to Figure 2 The symbol synchronization module 12 includes a first matched filter 26 and a second matched filter 27 ; the first matched filter 26 and the second matched filter 27 are connected to the frame synchronization module 11 respectively.

[0080] The first matched filter 26 is used to receive the symbol 0 feature sequence; based on a preset convolution formula, calculate the matching degree between the downlink instruction and the symbol 0 feature sequence, and output the first convolution result; determine the peak position of the first convolution result as the end position of symbol 0.

[0081] Here, the first matched filter 26 receives the symbol 0 characteristic sequence from the calibration symbol detection unit 25. A convolution calculation is performed on the downlink instruction signal and the symbol 0 characteristic sequence using a preset convolution formula.

[0082] The convolution formula is shown in the following formula (1):

[0083]

[0084] Among them, R[n] is the convolution result, x[n] is the downlink instruction signal, h[k] is the symbol feature sequence, when k=0, it is the symbol 0 feature sequence, when k=1, it is the symbol 1 feature sequence, and L is the length of the symbol feature sequence.

[0085] The calculated result is the first convolution result, which reflects the matching degree between the downlink instruction and the symbol 0 feature sequence.

[0086] The first convolution result is processed, and the end position of the marking symbol 0 in the downlink instruction is marked by finding the peak position of the convolution value.

[0087] The second matched filter 27 is used to receive the symbol 1 feature sequence; based on a preset convolution formula, calculate the matching degree between the downlink instruction and the symbol 1 feature sequence, and output a second convolution result; determine the peak position of the second convolution result as the end position of symbol 1.

[0088] Here, the processing process of the second matched filter 27 is the same as the processing process of the first matched filter 26, and will not be repeated here.

[0089] In one embodiment, a related receiver circuit is provided in the matched filter, and the related receiver circuit is as follows: Figure 3 As shown. The related receiver circuit is based on the FIR filter (Finite Impulse Response, non-recursive filter) circuit. The main function is to perform convolution operation on the input signal (Input_signal, i.e. demod signal) and the local symbol feature sequence, and output the matching degree result (Output_signal) to support the subsequent modules to perform symbol judgment and synchronization.

[0090] The FIR filter core consists of a tapped delay line, an XOR gate (replaced by a multiplier), an adder, and a shift register. The number of taps (order) of the filter can be adjusted dynamically. The relevant receiver circuit in this embodiment can use a counter and an enable signal to dynamically configure the number of taps of the filter to adapt to different symbol feature lengths. The counter reads the current count value at the falling edge of the enable signal to select the filter order result corresponding to the output of the multiplexer (MUX). The waveform features of symbol 0 and symbol 1 are extracted in the calibration symbol interval and loaded into the filter delay line respectively as a local correlation sequence. In this embodiment, an XOR gate is used to replace the multiplier to simplify the circuit complexity, and the filter order is dynamically configured to improve resource utilization efficiency and reduce power consumption.

[0091] Reference Figure 3, the relevant receiver circuit includes an input signal (Input_signal) and a delay line, where Input_signal represents the demodulated signal transmitted from the previous stage. Delay line: composed of multiple shift registers, used to delay the input signal step by step to generate multiple tap outputs.

[0092] The local correlation sequence represents the local feature sequence of symbol 0 and symbol 1 generated in the symbol feature extraction process. It is used as a reference template of the filter and performs point-by-point matching operation with the delay line output.

[0093] XOR gates (multiplier replacement) match the output of the delay line with the local correlation sequence point by point. XOR gates are used instead of traditional multipliers to perform "match / mismatch" calculations and output matching results.

[0094] The adder adds the matching results of the XOR gates in sequence to generate the intermediate result of the convolution operation.

[0095] The counter records the cycle length of the current symbol feature extraction, which is used to configure the number of taps of the filter. Through the counter and the enable signal, the dynamic configuration of the filter is realized to improve adaptability and resource efficiency.

[0096] The multiplexer (MUX) selects the corresponding filter order according to the output of the counter and dynamically adjusts the output result.

[0097] The final convolution operation result of the output signal (Output_signal) indicates the matching degree between the input signal and the symbol feature sequence, which is used for subsequent peak detection and synchronization operations.

[0098] Figure 3 The relevant receiver circuit in the invention provides a matched filter structure with strong anti-interference ability to meet the signal processing requirements in complex communication environments.

[0099] In one embodiment, referring to Figure 2 The symbol synchronization module 12 includes a first peak detection unit 28 and a second peak detection unit 29; the first peak detection unit 28 is connected to the first matched filter 26 and the symbol decoding module 13 respectively; the second peak detection unit 29 is connected to the second matched filter 27 and the symbol decoding module 13 respectively.

[0100] Here, the peak detection unit locates the end position of each symbol in the downlink instruction by detecting the peak value of the convolution result, and generates a symbol synchronization signal.

[0101] The first peak detection unit 28 is used to receive the first convolution result, determine the first peak position of the first convolution result as the end position of symbol 0 in the downlink instruction based on a preset peak calculation method, and send the first convolution result to the symbol decoding module 13.

[0102] Here, the first peak detection unit 28 receives the first convolution result from the first matched filter 26 .

[0103] Based on the derivation and monotonicity detection, peak detection is performed on the first convolution result, specifically including:

[0104] Calculate the first-order difference for each point of the first convolution result, that is, subtract the current data point from the data point of the previous clock cycle to obtain the derivative. When the derivative is positive, it means that the data point is in a monotonically increasing state. When the derivative is negative, it means that the data point is in a monotonically decreasing state. According to the positive or negative of the derivative, a monotonicity indication signal is generated through combinational logic. A high level indicates monotonically increasing, and a low level indicates monotonically decreasing.

[0105] The edge detection subunit 22 locates the falling edge position of the monotonicity indication signal from high level to low level, which is the peak position of the first convolution result. The peak position is marked as the end position of symbol 0, indicating that the convolution result at this time has the highest matching degree with the characteristic sequence of symbol 0.

[0106] The first peak detection unit 28 sends the first convolution result and the detected first peak position to the symbol decoding module 13 .

[0107] The second peak detection unit 29 is used to receive the second convolution result, determine the second peak position of the second convolution result as the end position of symbol 1 in the downlink instruction based on a preset peak calculation method, and send the second convolution result to the symbol decoding module 13.

[0108] Here, the processing process of the second peak detection unit 29 is the same as that of the first peak detection unit 28, and will not be repeated here.

[0109] In one embodiment, referring to Figure 2 The symbol synchronization module 12 further includes a clock recovery unit 210; the clock recovery unit 210 is connected to the first peak detection unit 28, the second peak detection unit 29 and the symbol decoding module 13 respectively.

[0110] The clock recovery unit 210 is used to obtain the first peak position, the second peak position and the valid frame signal; based on the first peak position and the second peak position, merge to generate a peak sequence; based on the effective peak recognition method and the effective frame processing range, filter out the effective peak in the peak sequence; based on the effective peak, determine the best decision time for the downlink instruction; generate a synchronization pulse signal at each best decision, merge each synchronization pulse signal, and generate a symbol synchronization signal; send the symbol synchronization signal to the symbol decoding module 13.

[0111] Here, the first peak position associated with the end position of symbol 0 is obtained from the first peak detection unit 28. The second peak position associated with the end position of symbol 1 is obtained from the second peak detection unit 29.

[0112] A valid frame signal is obtained from the frame synchronization module 11 to indicate the start and end positions of the effective load.

[0113] The peak position output by the first peak detection unit 28 and the peak position output by the second peak detection unit 29 are combined and arranged in time order to generate a peak sequence. The peak sequence contains all time points related to symbol synchronization, whether symbol 0 or symbol 1.

[0114] Use the valid frame signal as the screening condition to retain only the peaks in the peak sequence that fall within the valid frame range. The screening method is as follows:

[0115] Select the first peak from the peak sequence as the anchor value, calculate the distance between each peak and the anchor value, form a distance array, find the element with the smallest distance in the distance array, determine its corresponding peak as the valid peak, use the current valid peak as the new anchor value, and repeat the above process until all valid peaks are screened out.

[0116] The position of each effective peak is the best decision moment for the corresponding symbol in the downlink instruction. According to the position of the effective peak, a set of time points corresponding to the end position of the symbol is generated to form a sequence of best decision moments.

[0117] At each optimal decision moment, a high-level synchronization pulse signal lasting for one clock cycle is generated, wherein the synchronization pulse signal is a discrete pulse sequence corresponding to the end moment of each symbol.

[0118] Each synchronization pulse signal is combined to generate a complete symbol synchronization signal, and the symbol synchronization signal is sent to the symbol decoding module 13. The symbol synchronization signal is a continuous time series, covering all symbols within the valid frame range.

[0119] Figure 4 is a simulation waveform diagram of the clock recovery unit 210. Figure 4 , Figure 4 It includes 7 simulation signals: clk is the simulation clock, demod is the downlink signaling used for simulation, payload_valid signal indicates the effective start and end time of the payload, peak_cnt records the clock cycle length of the current symbol, symbol_zero_flag indicates the peak sequence output by the first matched filter 26, symbol_one_flag indicates the peak sequence output by the second matched filter 27, and clk_recovery indicates the symbol optimal decision time sequence.

[0120] The clock recovery unit 210 receives the symbol_zero_flag, symbol_one_flag and payload_valid signals. The peak values ​​in the symbol_zero_flag and symbol_one_flag signals are merged and arranged in chronological order to form a complete peak sequence. The peak values ​​falling within the payload range are screened out based on the payload_valid signal. For the screened out valid peak values, the end position of each symbol is determined to generate a sequence of optimal judgment moments. At each optimal judgment moment, a synchronization pulse signal with a high level lasting for one clock cycle is generated. All synchronization pulse signals are merged to form a complete clk_recovery signal, which is sent to the symbol decoding module 13.

[0121] Depend on Figure 4 It can be seen that the high level pulse of clk_recovery is only generated within the time range when payload_valid is high, ensuring that the synchronization signal only covers valid payload data. Each clk_recovery pulse corresponds to the effective peak of symbol_zero_flag or symbol_one_flag, marking the end of the symbol. peak_cnt is reset after each peak detection to ensure that the time interval of the peak meets the requirements of the symbol period.

[0122] Depend on Figure 4 It can be seen that the clock recovery unit 210 can generate an accurate synchronization signal clk_recovery according to symbol_zero_flag and symbol_one_flag, and clk_recovery only covers the payload range. The clk_recovery signal is consistent with the payload_valid range, proving that the clock recovery unit 210 successfully implements the symbol synchronization function. Each pulse of clk_recovery matches the valid peak value in symbol_zero_flag and symbol_one_flag to ensure the accuracy of the symbol decision moment.

[0123] The symbol decoding module 13 is used to read the convolution output values ​​of two moments at each optimal decision moment based on the symbol synchronization signal, compare the convolution output values ​​of the two moments based on a preset comparison rule, generate a symbol decision result, and combine the symbol decision results to generate valid data.

[0124] Here, the symbol decoding module 13 extracts the convolution output values ​​of the corresponding two moments from the convolution result according to the optimal decision moment marked by the symbol synchronization signal. The symbol decision result is generated based on the preset comparison rule, and the decision result of each symbol is merged in sequence to form a complete symbol sequence. Based on the valid frame signal, only the symbol decision results within the valid frame range are merged to generate the final valid data, and the decoded valid data is output to complete the decoding process of the downlink instruction.

[0125] In one embodiment, the symbol decoding module 13 is also used to obtain, at each optimal decision moment, a convolution output value at a first moment corresponding to the first convolution result and a convolution output value at a second moment corresponding to the second convolution result; compare the convolution output value at the first moment and the convolution output value at the second moment; if the convolution output value at the first moment is greater than the convolution output value at the second moment, determine that the symbol decision result corresponding to the current symbol is 0; if the convolution output value at the first moment is less than the convolution output value at the second moment, determine that the symbol decision result corresponding to the current symbol is 1; based on the valid frame processing range and the preset downlink instruction frame protocol, merge the symbol decision results corresponding to the payload to generate valid data.

[0126] Here, a symbol synchronization signal (clk_recovery) is received from the symbol synchronization module 12, and each synchronization signal corresponds to the best decision time of a symbol.

[0127] At each optimal decision moment, the corresponding output values ​​are read from the convolution results of the first matched filter 26 and the second matched filter 27 respectively. The convolution output value at the first moment represents the matching degree of symbol 0, and the convolution output value at the second moment represents the matching degree of symbol 1.

[0128] If the convolution output value at the first moment is greater than the convolution output value at the second moment, the current symbol is determined to be 0. If the convolution output value at the first moment is less than the convolution output value at the second moment, the current symbol is determined to be 1.

[0129] Collect all symbol decision results (i.e. 0 or 1) within the payload range and merge them into complete valid data in symbol order. Specifically include:

[0130] The start and end positions of the valid frame are determined according to the payload_valid signal, and the judgment results of all symbols in the valid range are read and combined, the preamble and postamble are ignored, and only the payload data is retained.

[0131] The combined symbol decision results form valid data and serve as the final output of the decoding circuit. The valid data is a binary sequence that represents the valid information part of the decoded downlink signaling.

[0132] Figure 5 It is a simulation waveform diagram of the symbol decoding module 13. Figure 5It includes seven simulation signals: clk is the simulation clock, demod is the downlink signaling used for simulation, payload_valid signal indicates the effective start and end time of the payload, clk_recovery indicates the symbol optimal decision time sequence, corr_one indicates the output of the second matched filter 27, that is, the convolution result of symbol 1, corr_zero indicates the output of the first matched filter 26, that is, the convolution result of symbol 0, and data_recovery indicates the symbol decoding result of the payload in the current downlink signaling.

[0133] Depend on Figure 5 It can be seen that when the payload_valid signal is high, it indicates that the current frame is a valid frame. The high-level pulse of the clk_recovery signal only appears when payload_valid is high, marking the best decision moment for each symbol. The amplitudes of corr_one and corr_zero are read at the best decision moment indicated by the clk_recovery signal for symbol decision. The generation process of data_recovery is: at each high-level moment of clk_recovery, compare the amplitudes of corr_one and corr_zero; if the amplitude of corr_one is greater than corr_zero, the current symbol is judged to be 1; if the amplitude of corr_zero is greater than corr_one, the current symbol is judged to be 0; the judgment results are combined to generate data_recovery, which indicates the decoding result of the current valid frame.

[0134] Depend on Figure 5 It can be seen that the pulse of clk_recovery in the symbol decoding module 13 is consistent with the high level range of payload_valid, ensuring that the decoding process is limited to valid frames, and the generation of the symbol decision result data_recovery is consistent with the valid frame range. Each clk_recovery pulse corresponds to a symbol decision, and the decision result complies with the amplitude comparison rule of corr_one and corr_zero. The output of the data_recovery signal is consistent with the symbol information of the Payload part in the demod signal, indicating that the decoding process is completed correctly.

[0135] The embodiment of the present invention provides a decoding circuit, which is applied to a passive Internet of Things tag; the decoding circuit includes: a frame synchronization module, a symbol synchronization module and a symbol decoding module connected in sequence; the frame synchronization module is used to identify and mark the effective frame processing range of the received downlink instruction, and generate a valid frame signal; based on the system clock signal, two groups of symbol feature sequences corresponding to the system clock signal are extracted and generated; noise in the downlink instruction is eliminated to obtain an updated downlink instruction; the downlink instruction, the effective frame signal and the symbol feature sequence are sent to the symbol synchronization module; the symbol synchronization module is used to perform a convolution operation on the downlink instruction and the symbol feature sequence based on the effective frame processing range in the effective frame signal to generate a convolution result; a symbol synchronization signal is generated based on the convolution result, and the symbol synchronization signal is sent to the symbol decoding module; the convolution result is the convolution output value corresponding to each group of symbol feature sequences; the symbol synchronization signal is used to characterize the optimal decision moment corresponding to each symbol; the symbol decoding module is used to read the convolution output values ​​at two moments at each optimal decision moment based on the symbol synchronization signal, compare the convolution output values ​​at the two moments based on a preset comparison rule, generate a symbol decision result, and merge the symbol decision results to generate valid data. In this method, the frame synchronization module can identify and mark the effective frame processing range of the received downlink instruction, eliminate the clutter signal, and provide a clean and effective signal input for the subsequent symbol synchronization and symbol decoding; through the matching filter and peak detection unit of the symbol synchronization module, the convolution result of the demodulated signal and the symbol feature sequence is accurately calculated, the end position of each symbol is located, and then the synchronization signal is generated and the best decision moment is ensured; finally, the symbol decoding module performs symbol decision based on the convolution output value to generate high-precision valid data. The decoding circuit designed by the frame structure characteristics of the downlink signaling can achieve a sensitivity of -36dBm for the passive IoT tag, and has stronger anti-interference ability. When the SNR (signal-to-noise ratio) is ≥8dB, it can be correctly decoded. At the same time, by optimizing the filter structure and dynamically configuring the tap order, the power consumption and complexity of the circuit implementation are reduced, meeting the requirements of low cost, low power consumption and high reliability in large-scale IoT applications.

[0136] Embodiment 2:

[0137] Figure 6 A flowchart of a decoding method provided by an embodiment of the present invention.

[0138] The decoding method is applied to the decoding circuit in the above embodiment. The decoding method includes:

[0139] Step S101, identify and mark the valid frame processing range of the received downlink instruction through the frame synchronization module to generate a valid frame signal; extract and generate two sets of symbol feature sequences corresponding to the system clock signal based on the system clock signal; eliminate the noise in the downlink instruction to obtain the updated downlink instruction; send the downlink instruction, the valid frame signal and the symbol feature sequence to the symbol synchronization module.

[0140] Step S102, a symbol synchronization module performs convolution operation on a valid frame processing range in a valid frame signal, a downlink instruction and a symbol feature sequence to generate a convolution result; a symbol synchronization signal is generated based on the convolution result, and the symbol synchronization signal is sent to a symbol decoding module; the convolution result is a convolution output value corresponding to each group of symbol feature sequences; the symbol synchronization signal is used to characterize the optimal decision moment corresponding to each symbol.

[0141] Step S103, based on the symbol synchronization signal, the symbol decoding module reads the convolution output values ​​at two moments at each optimal decision moment, compares the convolution output values ​​at two moments based on a preset comparison rule, generates a symbol decision result, and combines the symbol decision results to generate valid data.

[0142] The embodiment of the present invention provides a decoding method that can effectively combat interference and noise in a communication environment, solve the problems of low decoding sensitivity and poor anti-interference ability of traditional passive IoT tags in complex environments, and improve the decoding accuracy and stability of the system.

[0143] Embodiment three:

[0144] Figure 7 Schematic diagram of a passive IoT tag provided in an embodiment of the present invention.

[0145] Reference Figure 7 The passive IoT tag includes a passive IoT tag body 31 ; and also includes a decoding circuit 32 in the above embodiment; the decoding circuit 32 is arranged in the passive IoT tag body 31 .

[0146] The embodiment of the present invention provides a passive IoT tag, which solves the problem of low receiving sensitivity of traditional passive IoT tags, improves the receiving sensitivity to -36dBm, and significantly enhances the long-distance communication capability. It can still decode correctly when SNR ≥ 8dB, which improves the robustness of the decoding circuit. It has the characteristics of high sensitivity, strong anti-interference ability, low power consumption and high decoding accuracy, can adapt to complex communication scenarios, extend the communication distance, and improve the reliability and cost-effectiveness in large-scale IoT applications. It can enhance the practical application value of RFID technology in IoT scenarios.

[0147] The computer program product provided in the embodiment of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can be found in the method embodiment and will not be repeated here.

[0148] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0149] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0150] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0151] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0152] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A decoding circuit, characterized in that: Applied to passive IoT tags; the decoding circuit comprises: a frame synchronization module, a symbol synchronization module and a symbol decoding module connected in sequence; The frame synchronization module is used to identify and mark the valid frame processing range of the received downlink instruction and generate a valid frame signal; extract and generate two sets of symbol feature sequences corresponding to the system clock signal based on the system clock signal; remove the noise in the downlink instruction to obtain the updated downlink instruction; send the downlink instruction, the valid frame signal and the symbol feature sequence to the symbol synchronization module; The symbol synchronization module is used to perform a convolution operation on the downlink instruction and the symbol feature sequence based on the valid frame processing range in the valid frame signal to generate a convolution result; generate a symbol synchronization signal based on the convolution result, and send the symbol synchronization signal to the symbol decoding module; the convolution result is the convolution output value corresponding to each group of the symbol feature sequence; the symbol synchronization signal is used to characterize the optimal decision time corresponding to each symbol; The symbol decoding module is used to read the convolution output values ​​of two moments at each optimal decision moment based on the symbol synchronization signal, compare the convolution output values ​​of the two moments based on a preset comparison rule, generate a symbol decision result, and merge the symbol decision results to generate valid data.

2. The decoding circuit according to claim 1, characterized in that: The frame synchronization module includes a clutter detection unit; the clutter detection unit is connected to the symbol synchronization module; the clutter detection unit includes a connected edge detection subunit and a counter; The edge detection subunit is used to detect the edge in the downlink instruction; Determine the level length between each two edges based on the system clock signal; judge whether the level length is within a preset level length range, and if not, determine that the signal not within the preset level length range is the noise; mark the signal of the downlink instruction corresponding to the noise as invalid, and obtain an updated downlink instruction; send the downlink instruction to the symbol synchronization module; The counter is used to count the number of clutter detected by the edge detection subunit.

3. The decoding circuit according to claim 2, characterized in that: The frame synchronization module further includes a locator detection unit; the locator detection unit is connected to the clutter detection unit; The locator detection unit is used to receive the downlink instruction sent by the clutter detection unit; detect and mark the falling edge position of the falling edge in the downlink instruction; Based on the system clock signal, record the low level width after each falling edge; determine whether the low level width is within a preset delimiter width range, and if so, determine whether the falling edge position is a preamble or a postamble based on a preset downlink instruction frame protocol; Determine a valid frame starting position based on the preamble; Determine the valid frame end position based on the post-amble; The valid frame processing range is generated based on the valid frame starting position and the valid frame ending position; the valid frame signal is generated based on the valid frame processing range; the preset downlink instruction frame protocol includes the frame structure of the downlink instruction and its corresponding fixed length.

4. The decoding circuit according to claim 3, characterized in that: The frame structure includes the preamble, the calibration symbol, the payload and the postamble; The frame synchronization module further includes a calibration symbol detection unit; the calibration symbol detection unit is respectively connected to the clutter detection unit, the locator detection unit and the symbol synchronization module; The calibration character detection unit is used to determine the calibration character range of the calibration character based on the valid frame start position in the valid frame signal and the preset downlink instruction frame protocol; Within the calibration symbol range, sampling the downlink instruction based on the system clock signal, and recording the level value corresponding to each sampling point; The level value is symbol 1 or symbol 0; each symbol 1 is sampled to generate a symbol 1 characteristic waveform sequence; Each symbol 0 is sampled to generate a symbol 0 waveform sequence; the symbol 1 characteristic waveform sequence is converted into a symbol 1 characteristic sequence, the symbol 0 waveform sequence is converted into a symbol 0 characteristic sequence, and the symbol 1 characteristic sequence and the symbol 0 characteristic sequence are sent to the symbol synchronization module.

5. The decoding circuit according to claim 4, characterized in that: The symbol synchronization module includes a first matched filter and a second matched filter; the first matched filter and the second matched filter are respectively connected to the frame synchronization module; The first matched filter is used to receive the symbol 0 feature sequence; calculate the matching degree between the downlink instruction and the symbol 0 feature sequence based on a preset convolution formula, and output a first convolution result; determine the peak position of the first convolution result as the end position of the symbol 0; The second matched filter is used to receive the symbol 1 feature sequence; based on the preset convolution formula, calculate the matching degree between the downlink instruction and the symbol 1 feature sequence, and output a second convolution result; determine the peak position of the second convolution result as the end position of the symbol 1.

6. The decoding circuit according to claim 5, characterized in that: The symbol synchronization module includes a first peak detection unit and a second peak detection unit; the first peak detection unit is connected to the first matched filter and the symbol decoding module respectively; the second peak detection unit is connected to the second matched filter and the symbol decoding module respectively; The first peak detection unit is used to receive the first convolution result, and determine, based on a preset peak calculation method, that a first peak position of the first convolution result is an end position of symbol 0 in the downlink instruction; Sending the first convolution result to the symbol decoding module; The second peak detection unit is used to receive the second convolution result, and determine, based on the preset peak calculation method, that the second peak position of the second convolution result is the end position of symbol 1 in the downlink instruction; The second convolution result is sent to the symbol decoding module.

7. The decoding circuit according to claim 6, characterized in that: The symbol synchronization module further includes a clock recovery unit; the clock recovery unit is respectively connected to the first peak detection unit, the second peak detection unit and the symbol decoding module; The clock recovery unit is used to obtain the first peak position, the second peak position and the valid frame signal; Based on the first peak position and the second peak position, a peak sequence is generated by merging; based on the effective peak recognition method and the effective frame processing range, effective peaks in the peak sequence are screened out; Based on the effective peak value, determine the optimal decision moment of the downlink instruction; generate a synchronization pulse signal at each optimal decision time, combine each synchronization pulse signal, and generate the symbol synchronization signal; The symbol synchronization signal is sent to the symbol decoding module.

8. The decoding circuit according to claim 7, characterized in that: The symbol decoding module is further used to obtain, at each optimal decision moment, a convolution output value at a first moment corresponding to the first convolution result and a convolution output value at a second moment corresponding to the second convolution result; and compare the convolution output value at the first moment with the convolution output value at the second moment; If the convolution output value at the first moment is greater than the convolution output value at the second moment, it is determined that the symbol decision result corresponding to the current symbol is 0; if the convolution output value at the first moment is less than the convolution output value at the second moment, it is determined that the symbol decision result corresponding to the current symbol is 1; based on the valid frame processing range and the preset downlink instruction frame protocol, the symbol decision results corresponding to the payload are merged to generate the valid data.

9. A decoding method, characterized in that: The decoding circuit according to any one of claims 1 to 8; the decoding method comprises: Identify and mark the valid frame processing range of the received downlink instruction through the frame synchronization module to generate a valid frame signal; extract and generate two sets of symbol feature sequences corresponding to the system clock signal based on the system clock signal; remove the noise in the downlink instruction to obtain an updated downlink instruction; send the downlink instruction, the valid frame signal and the symbol feature sequence to the symbol synchronization module; The symbol synchronization module performs convolution operation on the downlink instruction and the symbol feature sequence based on the valid frame processing range in the valid frame signal to generate a convolution result; a symbol synchronization signal is generated based on the convolution result, and the symbol synchronization signal is sent to the symbol decoding module; the convolution result is the convolution output value corresponding to each group of the symbol feature sequence; the symbol synchronization signal is used to characterize the optimal decision time corresponding to each symbol; Based on the symbol synchronization signal, the symbol decoding module reads the convolution output values ​​of two moments at each optimal decision moment, compares the convolution output values ​​of the two moments based on a preset comparison rule, generates a symbol decision result, and combines the symbol decision results to generate valid data.

10. A passive IoT tag, characterized in that: It includes a passive Internet of Things tag body; and also includes a decoding circuit as described in any one of claims 1 to 8 above; the decoding circuit is arranged in the passive Internet of Things tag body.

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