Wiring board and manufacturing method thereof
By forming grooves on the surface of the insulating layer and forming a seed layer and a main pattern layer therein, combined with electroplating technology, the problem of insufficient thickness uniformity of the existing buried circuit layer is solved, and an embedded circuit layer with a thickness difference of less than or equal to 1 micron is realized, supporting the development of thin circuits.
Patent Information
- Application Number
- CN202311382965.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-24
- Publication Date
- 2025-04-25
AI Technical Summary
The thickness uniformity of the existing embedded circuit layer is insufficient, resulting in a thickness difference of more than 2 microns, limiting the application of circuit boards in the development of thin circuits.
By forming a plurality of grooves on the surface of the insulating layer and forming a seed layer and a body pattern layer in the groove, a metal layer is formed in the seed layer and groove using electroplating technology, and finally the unnecessary metal layer and seed layer are removed to form an embedded circuit layer.
The thickness uniformity of the embedded circuit layer is achieved, with a thickness difference of less than or equal to 1 micron, supporting the application of circuit boards in the development of thin circuits.
Smart Images
Figure CN119893820A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a circuit board and a manufacturing method thereof, and more particularly to a circuit board including an embedded wiring layer and a manufacturing method thereof. Background Art
[0002] At present, there are circuit boards with embedded circuit layers, and the manufacturing method of such circuit boards generally includes the following steps. First, a circuit layer is formed, which is generally formed by a semi-additive process, wherein the step of forming the circuit layer includes an electroplating process. Afterwards, an insulating layer is pressed on the circuit layer so that the circuit layer is buried and embedded in the insulating layer, thereby forming an embedded circuit layer. However, due to the limitations of the electroplating process, it is difficult to further improve the thickness uniformity of the above-mentioned circuit layer, so that the thickness difference of the existing embedded circuit layer, that is, the difference between the maximum thickness and the minimum thickness, will be greater than 2 microns, which is not conducive to the development of fine circuits of current circuit boards. Summary of the invention
[0003] At least one embodiment of the present invention provides a circuit board including an embedded circuit layer. Compared with the existing embedded circuit layer, the embedded circuit layer of at least one embodiment of the present invention has better thickness uniformity.
[0004] At least one embodiment of the present invention provides a method for manufacturing the above-mentioned circuit board.
[0005] The circuit board proposed in at least one embodiment of the present invention includes an insulating layer and an embedded circuit layer. The insulating layer has a surface and a plurality of grooves formed on the surface. The embedded circuit layer is buried in these grooves and includes a plurality of seed layers and a main pattern layer. These seed layers are respectively arranged in these grooves and directly contact the insulating layer. The main pattern layer has a first surface, a second surface opposite to the first surface, and a plurality of side surfaces located between the first surface and the second surface. The seed layer covers the first surface and these side surfaces, but does not cover the second surface. The main pattern layer does not contact the insulating layer.
[0006] In at least one embodiment of the present invention, the thickness difference of the embedded circuit layer is less than or equal to 1 micron.
[0007] In at least one embodiment of the present invention, the embedded circuit layer includes a plurality of wirings and a plurality of pads, and the wirings and the pads are exposed on the surface of the insulating layer.
[0008] In at least one embodiment of the present invention, the second surface of the main pattern layer is flush with the surface of the insulating layer.
[0009] The manufacturing method of the circuit board proposed in at least one embodiment of the present invention includes forming a relief pattern layer on a carrier substrate. Then, an insulating layer is laminated on the carrier substrate, wherein the insulating layer covers the relief pattern layer, and the relief pattern layer is buried in the insulating layer. After laminating the insulating layer, the carrier substrate is removed to expose the relief pattern layer, wherein the relief pattern layer is exposed on the surface of the above-mentioned insulating layer. After removing the carrier substrate, the relief pattern layer is removed, and the insulating layer is retained to form a plurality of grooves on the surface of the insulating layer. Then, an initial seed layer is formed on the insulating layer, wherein the initial seed layer covers the surface of the aforementioned insulating layer and these grooves, but does not fill each of these grooves. Then, the initial seed layer is electroplated to form a metal layer on the aforementioned surface and in these grooves, wherein the metal layer and the initial seed layer fill these grooves. Then, part of the metal layer and part of the initial seed layer located outside these grooves are removed to expose the surface of the above-mentioned insulating layer.
[0010] In at least one embodiment of the present invention, the step of forming the relief pattern layer on the carrier substrate includes exposure and development.
[0011] In at least one embodiment of the present invention, the relief pattern layer is removed by using a photoresist.
[0012] In at least one embodiment of the present invention, the carrier substrate includes a main substrate and a metal foil formed on the main substrate, and the metal foil is bonded to the insulating layer. The step of removing the carrier substrate includes separating the metal foil from the main substrate to remove the main substrate. After removing the main substrate, the metal foil is etched.
[0013] In at least one embodiment of the present invention, the method of removing the portion of the metal layer and the portion of the initial seed layer outside the grooves comprises etching or grinding.
[0014] In at least one embodiment of the present invention, the step of laminating the insulating layer on the carrier substrate includes laminating a resin sheet on the carrier substrate.
[0015] Based on the above, compared with the circuit layer formed by the existing electroplating process, the buried circuit layer disclosed in at least one embodiment of the present invention has better thickness uniformity, so that the circuit board disclosed in at least one embodiment of the present invention is conducive to the development of fine circuits. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a cross-sectional schematic diagram of a circuit board according to at least one embodiment of the present invention.
[0017] Figures 2A to 2G yes Figure 1 Schematic diagram of the process cross section of the circuit board in. DETAILED DESCRIPTION
[0018] In the following text, in order to clearly present the technical features of the present invention, the dimensions (such as length, width, thickness and depth) of the elements (such as layers, films, substrates and regions, etc.) in the drawings will be enlarged in unequal proportions. Therefore, the description and explanation of the embodiments below are not limited to the dimensions and shapes presented by the elements in the drawings, but should cover the dimensions, shapes and deviations thereof caused by actual processes and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, while the acute angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the claims of the present invention.
[0019] Secondly, the words "about", "approximately" or "substantially" that appear in the content of this case not only cover the numerical values and numerical ranges that are clearly recorded, but also cover the permissible deviation range that can be understood by those with ordinary knowledge in the technical field to which the invention belongs, wherein the deviation range can be determined by the error generated during measurement, and the error is caused by the limitations of the measurement system or process conditions. For example, two objects (such as the planes or traces of the substrate) are "substantially parallel" or "substantially perpendicular", wherein "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects may include non-parallelism and non-perpendicularity caused by the permissible deviation range.
[0020] In addition, "approximately" may mean within one or more standard deviations of the above values, such as ±30%, ±20%, ±10% or ±5%. In this text, the words "approximately", "approximately" or "substantially" may be used to select acceptable deviation ranges or standard deviations according to optical properties, etching properties, mechanical properties or other properties, rather than applying a single standard deviation to all properties such as the above optical properties, etching properties, mechanical properties and other properties.
[0021] Figure 1 is a cross-sectional schematic diagram of a circuit board according to at least one embodiment of the present invention. Figure 1 The circuit board 100 includes an insulating layer 110 and an embedded circuit layer 120, wherein the embedded circuit layer 120 is embedded in the insulating layer 110, and the insulating layer 110 exposes a portion of the embedded circuit layer 120. Figure 1 For example, the insulating layer 110 has a surface 111 and a plurality of grooves R11 formed on the surface 111, wherein the surface 111 may be the lower surface of the insulating layer 110. The embedded circuit layer 120 is embedded in the grooves R11 and exposed on the surface 111 of the insulating layer 110.
[0022] The embedded circuit layer 120 includes a main pattern layer 121 and a plurality of seed layers 122, wherein the seed layers 122 are respectively disposed in the grooves R11 and directly contact the insulating layer 110. The seed layers 122 cover all surfaces of the grooves R11. In other words, the seed layers 122 cover the bottom surface and the sidewalls of the grooves R11. Although the seed layers 122 are disposed in the grooves R11, each seed layer 122 does not fill up any groove R11. Therefore, each seed layer 122 only occupies a portion of the space of one of the grooves R11, and the main pattern layer 121 fills up the remaining space of the groove R11 not occupied by the seed layer 122.
[0023] In other words, the main pattern layer 121 and the seed layers 122 will fill the grooves R11, wherein the seed layers 122 can conformally cover all surfaces of the grooves R11. In other words, each seed layer 122 can extend along the surface of the groove R11 and form a groove (not shown) with a shape similar to the groove R11, so as to be accommodated and filled by the main pattern layer 121, such as Figure 1 shown.
[0024] The main pattern layer 121 can be a metal pattern layer, and can be made of a metal material with good conductivity such as copper, silver, gold, aluminum or aluminum-copper alloy. The main pattern layer 121 has a first surface 121a, a second surface 121b opposite to the first surface 121a, and a plurality of side surfaces 121c located between the first surface 121a and the second surface 121b. The main pattern layer 121 can be a discontinuous film layer, so the first surface 121a and the second surface 121b can also be discontinuous surfaces. Specifically, the embedded circuit layer 120 includes a plurality of traces T12 and a plurality of pads P12, wherein these traces T12 and these pads P12 are exposed on the surface 111 of the insulating layer 110. At least two of these traces T12 and these pads P12 are completely not in contact with each other, so that the first surface 121a and the second surface 121b are discontinuous surfaces.
[0025] Since the seed layer 122 covers all surfaces of the groove R11, namely the bottom surface and the sidewall of the groove R11, the seed layers 122 cover the first surface 121a and the side surfaces 121c of the main pattern layer 121, so that the main pattern layer 121 does not contact the insulating layer 110. In other words, the seed layers 122 separate the main pattern layer 121 from the insulating layer 110. In addition, although the seed layer 122 covers the first surface 121a and the side surfaces 121c, it does not cover the second surface 121b, so the second surface 121b is exposed to the surface 111 of the insulating layer 110, wherein the second surface 121b of the main pattern layer 121 can be cut flush with the surface 111 of the insulating layer 110.
[0026] Figures 2A to 2G yes Figure 1 See the schematic diagram of the process section of the circuit board in Figure 2A and Figure 2B , a relief pattern layer MP2 is formed on the carrier substrate 20, wherein the relief pattern layer MP2 is depicted on Figure 2B For more information, see Figure 2A First, a carrier substrate 20 is provided, wherein the carrier substrate 20 includes a main substrate 21 and a metal foil 22 formed on the main substrate 21, and the metal foil 22 can be an aluminum foil or a copper foil. Then, a photoresist layer PS2 is formed on the carrier substrate 20, wherein the photoresist layer PS2 can be a dry film or a wet film.
[0027] The main substrate 21 includes a film layer 212 and a support layer 211, wherein the film layer 212 is arranged and fixed on the support layer 211, and the support layer 211 may be an insulating layer, which may include resin and glass fiber, so that the support layer 211 can adhere to the film layer 212. In addition, the support layer 211 may also be a ceramic plate or a glass plate. The film layer 212 may be a metal layer, such as a copper metal layer or an aluminum metal layer, so that the film layer 212 and the metal foil 22 can be made of the same metal material (such as copper or aluminum). The metal foil 22 is arranged on the film layer 212, and the film layer 212 is located between the metal foil 22 and the support layer 211, wherein the metal foil 22 can be temporarily fixed on the film layer 212, and can be peeled off from the film layer 212 to separate the metal foil 22 from the main substrate 21.
[0028] See also Figure 2A and Figure 2B , then, the photoresist layer PS2 is patterned, that is, the photoresist layer PS2 is exposed and developed to form a relief pattern layer MP2 on the metal foil 22 of the carrier substrate 20. Therefore, the step of forming the relief pattern layer MP2 on the carrier substrate 20 includes exposure and development. The relief pattern layer MP2 can directly contact the metal foil 22 and partially cover the metal foil 22, so that the relief pattern layer MP2 has a plurality of openings H2 partially exposing the metal foil 22, wherein at least one opening H2 can be a trench.
[0029] See also Figure 2C, and then, an insulating layer 110 is laminated on the carrier substrate 20, wherein the insulating layer 110 covers the metal foil 22 and the relief pattern layer MP2. The step of laminating the insulating layer 110 on the carrier substrate 20 may include laminating a resin sheet (prepreg) on the carrier substrate 20. In other words, the insulating layer 110 may be formed by a resin sheet and may directly contact the metal foil 22 and the relief pattern layer MP2, so the insulating layer 110 will adhere to the metal foil 22 and the relief pattern layer MP2, that is, the metal foil 22 is adhered to the insulating layer 110. Except for the surface of the relief pattern layer MP2 that contacts the metal foil 22 and is not covered by the insulating layer 110, the other surfaces of the relief pattern layer MP2 are all covered by the insulating layer 110. Secondly, the insulating layer 110 will fill the openings H2. Therefore, the relief pattern layer MP2 will be buried in the insulating layer 110.
[0030] See also Figure 2C and Figure 2D After laminating the insulating layer 110, the carrier substrate 20 is removed to expose the relief pattern layer MP2, wherein the relief pattern layer MP2 is exposed on the surface 111 of the insulating layer 110. The method for removing the carrier substrate 20 may include the following steps. The metal foil 22 and the main substrate 21 are separated to remove the main substrate 21. Since the metal foil 22 can be peeled off from the film layer 212 of the main substrate 21, the metal foil 22 and the main substrate 21 can be separated by peeling to remove the main substrate 21. After removing the main substrate 21, the metal foil 22 is etched. Since the metal foil 22 is bonded to the insulating layer 110, the metal foil 22 is suitable for removal by etching.
[0031] See also Figure 2D and Figure 2E After removing the carrier substrate 20, the relief pattern layer MP2 is removed, and the insulating layer 110 is retained to form a plurality of grooves R11 on the surface 111 of the insulating layer 110. Since the relief pattern layer MP2 is formed by the photoresist layer PS2 after exposure and development, the relief pattern layer MP2 can be removed by removing the photoresist. Figure 2D and Figure 2E From this perspective, the thickness PT2 of the relief pattern layer MP2 is equivalent to the depth of the grooves R11 , and thus the depth of the grooves R11 can be determined by the thickness PT2 of the relief pattern layer MP2 .
[0032] See also Figure 2FThen, an initial seed layer 122i is formed on the insulating layer 110, wherein the initial seed layer 122i covers the surface 111 of the insulating layer 110 and the grooves R11, but does not fill each groove R11. The initial seed layer 122i may be a metal layer and may be formed by deposition. For example, the initial seed layer 122i may be formed by electroless plating or physical vapor deposition (PVD), and may be a copper metal layer.
[0033] See also Figure 2G Then, the initial seed layer 122i is electroplated to form a metal layer 121i on the surface 111 of the insulating layer 110 and in the grooves R11, so that the metal layer 121i and the initial seed layer 122i fill the grooves R11. Figure 2G In addition, the metal layer 121i may be a copper metal layer, so the initial seed layer 122i and the metal layer 121i may be made of the same metal material.
[0034] See also Figure 1 and Figure 2G After that, the portion of the metal layer 121i and the portion of the initial seed layer 122i outside the grooves R11 are removed to expose the surface 111 of the insulating layer 110, and the remaining initial seed layer 122i and the remaining metal layer 121i in the grooves are retained to form a plurality of seed layers 122 and a main pattern layer 121, respectively. Figure 1 As shown. At this point, the circuit board 100 including the embedded circuit layer 120 is basically completed. The method of removing the portion of the metal layer 121i and the portion of the initial seed layer 122i outside the grooves R11 may include etching or grinding. When grinding is used to remove the portion of the metal layer 121i and the portion of the initial seed layer 122i, the second surface 121b of the main pattern layer 121 can be flush with the surface 111 of the insulating layer 110.
[0035] from Figure 1 and Figure 2G From the perspective of FIG. 1 , the thickness of the embedded circuit layer 120 is equivalent to the depth of the groove R11, and the depth of the groove R11 can be determined by the thickness PT2 of the convex pattern layer MP2 (please refer to Figure 2D). Therefore, the thickness of the embedded circuit layer 120 can be determined by the thickness PT2 of the convex pattern layer MP2. Since the convex pattern layer MP2 is formed by exposing and developing the photoresist layer PS2 (such as a dry film or a wet film), the convex pattern layer MP2 has better thickness uniformity than the circuit layer formed by the electroplating process, so that the thickness difference of the embedded circuit layer 120 can be less than 2 microns. The convex pattern layer MP2 formed by the dry film has better thickness uniformity, so that the thickness difference of the embedded circuit layer 120 can be less than or equal to 1 micron. It should be noted that the aforementioned "thickness difference" refers to the difference between the maximum and minimum values of the thickness 120t of the embedded circuit layer 120.
[0036] In summary, compared to the circuit layer formed by the existing electroplating process, the embedded circuit layer disclosed in at least one embodiment of the present invention has better thickness uniformity, so that the circuit board disclosed in at least one embodiment of the present invention is conducive to the development of fine circuits, thereby meeting the development trend of existing electronic devices, such as mobile phones, tablets and computers, towards small size and thinness.
[0037] Although the present invention has been disclosed as above by way of embodiments, they are not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.
[0038]
Explanation of symbols
[0039] 20: Carrier substrate
[0040] 21: Main substrate
[0041] 22: Metal foil
[0042] 100: Circuit board
[0043] 110: Insulation layer
[0044] 111: Surface
[0045] 120: Embedded circuit layer
[0046] 120t, PT2: thickness
[0047] 121: Main pattern layer
[0048] 121a: First surface
[0049] 121b: Second surface
[0050] 121c: Side surface
[0051] 121i: Metal layer
[0052] 122: Seed layer
[0053] 211: Support layer
[0054] 212: Film layer
[0055] H2: Opening
[0056] MP2: relief pattern layer
[0057] R11: Groove
[0058] T12: Routing
[0059] P12: pad
[0060] PS2: Photoresist layer.
Claims
1. A circuit board, characterized in that: include: An insulating layer having a surface and a plurality of grooves formed on the surface; as well as The embedded circuit layer is embedded in the groove and includes: A plurality of seed layers are respectively disposed in the plurality of grooves and directly contact the insulating layer; as well as The main pattern layer has a first surface, a second surface opposite to the first surface, and multiple side surfaces located between the first surface and the second surface, wherein the seed layer covers the first surface and the multiple side surfaces but does not cover the second surface, and the main pattern layer does not contact the insulating layer.
2. The circuit board according to claim 1, characterized in that: The thickness difference of the embedded circuit layer is less than or equal to 1 micron.
3. The circuit board according to claim 1, characterized in that: The embedded circuit layer includes a plurality of wirings and a plurality of pads, and the wirings and the pads are exposed on the surface of the insulating layer.
4. The circuit board according to claim 1, characterized in that: The second surface of the main pattern layer is flush with the surface of the insulating layer.
5. A method for manufacturing a circuit board, characterized in that: include: forming a relief pattern layer on a carrier substrate; Laminating an insulating layer on the carrier substrate, wherein the insulating layer covers the convex pattern layer, and the convex pattern layer is buried in the insulating layer; After laminating the insulating layer, removing the carrier substrate to expose the embossed pattern layer, wherein the embossed pattern layer is exposed on the surface of the insulating layer; After removing the carrier substrate, removing the convex pattern layer and retaining the insulating layer to form a plurality of grooves on the surface of the insulating layer; forming an initial seed layer on the insulating layer, wherein the initial seed layer covers the surface and the plurality of grooves but does not fill each of the plurality of grooves; Electroplating the initial seed layer to form a metal layer on the surface and in the plurality of grooves, wherein the metal layer and the initial seed layer fill the plurality of grooves; as well as A portion of the metal layer and a portion of the initial seed layer outside the groove are removed to expose the surface of the insulating layer.
6. The method for manufacturing a circuit board according to claim 5, characterized in that: The step of forming the relief pattern layer on the carrier substrate includes exposure and development.
7. The method for manufacturing a circuit board according to claim 6, characterized in that: The relief pattern layer is removed by using a photoresist.
8. The method for manufacturing a circuit board according to claim 5, characterized in that: The carrier substrate includes a main substrate and a metal foil formed on the main substrate, and the metal foil is bonded to the insulating layer. The step of removing the carrier substrate includes: separating the metal foil and the main substrate to remove the main substrate; and After removing the host substrate, the metal foil is etched.
9. The method for manufacturing a circuit board according to claim 5, characterized in that: The method of removing the portion of the metal layer and the portion of the initial seed layer outside the groove includes etching or grinding.
10. The method for manufacturing a circuit board according to claim 5, characterized in that: The step of laminating the insulating layer on the carrier substrate includes laminating a resin sheet on the carrier substrate.