Method of manufacturing a circuit board, circuit board and circuit board assembly
By combining etching and electroplating, grooved pads are formed, which solves the problems of poor quality and difficult processing caused by the reduction of pad size and spacing, and achieves high-density wiring and improved reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO LTD
- Filing Date
- 2023-10-23
- Publication Date
- 2026-05-22
AI Technical Summary
When increasing the packaging density of circuit boards, existing technologies reduce the size and spacing of solder pads, leading to an increased risk of quality defects. Increased wiring density also increases the difficulty of processing, and traditional etching processes encounter bottlenecks.
After forming conductive parts by etching, the first electroplating layer is formed by electroplating. Combined with the shielding of the insulating layer, a grooved pad is formed. During the electroplating process, a spacer layer is used to control the line spacing and reduce the risk of bridging short circuits.
The etching factor was improved, the wiring density was increased, the possibility of short circuits was reduced, and the reliability and processing efficiency of the circuit board were improved.
Smart Images
Figure CN119893858B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit board technology, and in particular to a method for manufacturing a circuit board, a circuit board, and a circuit board assembly. Background Technology
[0002] With the miniaturization of terminal devices, the packaging density of circuit boards in these devices is gradually increasing. This can be achieved by reducing pad size, spacing between pads, and increasing wiring density. However, reducing pad size and spacing increases the risk of quality defects (such as short circuits); increasing wiring density makes circuit board manufacturing processes more difficult, and traditional etching processes encounter bottlenecks. Summary of the Invention
[0003] This application provides a method for manufacturing a circuit board, comprising the following steps: providing a circuit board substrate, including a dielectric layer, a conductive portion, and a first insulating layer, wherein the conductive portion is located on the surface of the dielectric layer, and the first insulating layer covers the conductive portion away from the surface of the dielectric layer; electroplating the circuit board substrate to form a first electroplated layer on the surface of the conductive portion, wherein the first electroplated layer also covers a portion of the surface of the first insulating layer to form a groove; removing the first insulating layer; and forming a solder resist layer, wherein the solder resist layer covers a portion of the first electroplated layer, and the groove is exposed to the solder resist layer.
[0004] In some embodiments of this application, the circuit board includes a plurality of conductive portions. Before electroplating the circuit board, the manufacturing method further includes: forming a spacer layer between adjacent conductive portions, wherein the spacer layer is disposed at a distance from the conductive portions; and removing the spacer layer after electroplating the circuit board.
[0005] In some embodiments of this application, the method for manufacturing a circuit board includes the following steps: covering a first dry film on a substrate, the substrate including a dielectric layer and a first copper layer located on the surface of the dielectric layer, the first dry film covering the first copper layer; exposing and developing the first dry film to form a first insulating layer; etching the first copper layer to form a conductive portion, the first copper layer covered by the first insulating layer being etched to form a conductive portion.
[0006] In some embodiments of this application, the circuit board further includes conductive leads, which are spaced apart from the conductive portion; the method of manufacturing the circuit board further includes: before the step of covering the surface of the substrate with a first dry film, covering the substrate with adhesive tape, which covers a portion of the surface of the first copper layer; when covering the first dry film, the first dry film covers the first copper layer and exposes it to the surface of the adhesive tape; after exposing and developing the first dry film to form a first insulating layer, the first insulating layer is spaced apart from the adhesive tape; and after etching the first copper layer, removing the adhesive tape, the first copper layer covered by the adhesive tape is etched to form conductive leads.
[0007] In some embodiments of this application, when the circuit board includes conductive leads, a spacer layer is also formed between the conductive leads and the conductive portion, and the spacer layer is spaced apart from the conductive leads and the conductive portion.
[0008] In some embodiments of this application, the circuit board further includes conductive leads, which are spaced apart from conductive portions. The method for manufacturing the circuit board further includes: covering a substrate with a second dry film, the substrate including a dielectric layer and a first copper layer located on the surface of the dielectric layer, the second dry film covering the first copper layer; exposing and developing the second dry film to form a second insulating layer, a portion of the surface of the first copper layer being exposed to the second insulating layer; forming a masking layer on the surface of the first copper layer exposed to the second insulating layer; removing the second insulating layer; laminating a third dry film, the third dry film covering the first copper layer exposed to the masking layer; exposing and developing the third dry film to form a first insulating layer, the first insulating layer and the masking layer being spaced apart; and etching a portion of the first copper layer and the masking layer to form conductive portions and conductive leads, the first copper layer covered by the masking layer being etched to form conductive leads.
[0009] In some embodiments of this application, when electroplating the circuit board, a second electroplating layer is also formed on the surface of the conductive leads.
[0010] A circuit board includes a dielectric layer and pads; the pads are located on the surface of the dielectric layer, and each pad includes a conductive portion and a first electroplated layer. The conductive portion is located on the surface of the dielectric layer, and the first electroplated layer covers a portion of the surface of the conductive portion. A groove is formed on the surface of the first electroplated layer away from the dielectric layer, and the surface of the conductive portion away from the dielectric layer is exposed in the groove.
[0011] In some embodiments of this application, the circuit board further includes conductive leads located on the surface of the dielectric layer where pads are provided, with the conductive leads and pads spaced apart.
[0012] A circuit board assembly includes a circuit board, conductive paste, and electronic components. The conductive paste is contained in a recess; the electronic components are connected to the conductive paste.
[0013] The circuit board manufacturing method provided in this application first forms conductive parts by etching, and then forms a first electroplating layer by electroplating, thereby forming pads. This is beneficial for improving the etching factor, forming lines with smaller spacing, and increasing wiring density. In addition, by shielding with a first insulating layer, it is easier to form pads with grooves during the electroplating process. During the process of mounting electronic components on the circuit board, conductive paste is placed in the grooves and then reflow soldering is performed. After the conductive paste melts, due to the barrier effect of the grooves, the molten conductive paste is located in the corresponding grooves, reducing or avoiding the possibility of bridging short circuits. Attached Figure Description
[0014] Figure 1This is a top view of the circuit board provided in an embodiment of this application.
[0015] Figure 2 for Figure 1 The diagram shows a cross-sectional view of the circuit board along the AA direction.
[0016] Figure 3 In order to be in Figure 2 The diagram shows a cross-section of the circuit board after the fourth dry film has been applied.
[0017] Figure 4 For exposure and development Figure 3 The diagram shows a cross-section of the fourth dry film after it forms a spacer layer.
[0018] Figure 5 To Figure 4 The diagram shows a cross-sectional view of the circuit board after electroplating to form the first and second electroplating layers.
[0019] Figure 6 To remove Figure 5 The diagram shows a cross-section behind the spacer layer.
[0020] Figure 7 In order to be in Figure 6 The diagram shows a cross-sectional view of the first and second electroplated layers after the formation of a solder resist layer.
[0021] Figure 8 In order to be in Figure 7 The diagram shows a cross-sectional view of the circuit board obtained after a surface treatment layer is formed on the surface of the first electroplated layer.
[0022] Figure 9 This is a cross-sectional flowchart illustrating the fabrication process of a circuit board according to some embodiments of this application.
[0023] Figure 10 This is a cross-sectional flow diagram of the fabrication process of a circuit board provided for other embodiments of this application.
[0024] Figure 11 This is a cross-sectional schematic diagram of a circuit board assembly provided in an embodiment of this application.
[0025] Explanation of main component symbols
[0026]
[0027] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation
[0028] To better understand the above-mentioned objectives, features, and advantages of this application, the application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Many specific details are set forth in the following description to provide a thorough understanding of this application; the described embodiments are merely some, not all, of the embodiments described in this application.
[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.
[0030] In the various embodiments of this application, for ease of description and not limitation, the term "connection" used in the patent application specification and claims is not limited to physical or mechanical connections, whether direct or indirect. Terms such as "upper," "lower," "above," "below," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.
[0031] Please see Figures 1 to 10 This application provides a method for manufacturing a circuit board 100, which may include the following steps:
[0032] Step S1: Please refer to Figure 1 and Figure 2 A circuit board 10 is provided. The circuit board 10 includes a dielectric layer 11, a conductive portion 132, a conductive lead 134, and a first insulating layer 136. The conductive portion 132 and the conductive lead 134 are located on the surface of the dielectric layer 11. The first insulating layer 136 covers the upper surface of the conductive portion 132 away from the dielectric layer 11. The conductive portion 132 also includes a side surface, which connects the upper surface and the dielectric layer 11.
[0033] The circuit board 10 includes a conductive layer 13 located on the surface of the dielectric layer 11. The conductive layer 13 is formed by etching, and its cross-section is approximately trapezoidal, with a narrower width on the side away from the dielectric layer 11 and a wider width on the side closer to the dielectric layer 11. The conductive layer 13 includes conductive portions 132, and conductive portions 132 and conductive leads 134 are located on the same surface of the dielectric layer 11. The conductive portions 132 and conductive leads 134 are spaced apart, and the conductive layer 13 connects to the conductive leads 134. The number of conductive portions 132 can be one or more, and the number of conductive leads 134 is at least two. In this embodiment, the number of conductive portions 132 and conductive leads 134 are both two. The conductive leads 134 are distributed on both sides of the conductive portions 132, with adjacent conductive portions 132 spaced apart. The conductive leads 134 can be used for electroplating in subsequent processes.
[0034] The first insulating layer 136 covers the surface of the conductive part 132 away from the dielectric layer 11, and is used to shield the surface of the conductive part 132 away from the dielectric layer 11.
[0035] The number of dielectric layers 11 is not limited to one. The material of the dielectric layer 11 can be selected from one of the following materials: polyimide (PI), liquid crystal polymer (LCP), modified polyimide (MPI), polypropylene (PP), polyethylene naphthalate dicarboxylate (PEN), glass fiber, and polytetrafluoroethylene (PTFE).
[0036] Step S2: Please refer to Figure 3 and Figure 4 A spacer layer 20 is formed between adjacent conductive portions 132 and / or between conductive portions 132 and conductive leads 134, and the spacer layer 20 is spaced apart from the conductive portions 132 and / or conductive leads 134.
[0037] The spacer layer 20 can be made of photosensitive resin, ink, dry film, wet film, etc. In some embodiments, the step of forming the spacer layer 20 may include:
[0038] Step S21: Please refer to Figure 3 A fourth dry film 21 is applied to the circuit board 10, covering the surface of the conductive part 132, the conductive lead 134, the first insulating layer 136, and the dielectric layer 11.
[0039] Step S22: Please refer to Figure 4The fourth dry film 21 is exposed and developed to form a spacer layer 20 between adjacent conductive portions 132 and between conductive portions 132 and conductive leads 134.
[0040] Along the direction in which the circuit board 10 is stacked, the height of the spacer layer 20 is higher than the height of the conductive portion 132, so that the spacer layer 20 can act as a barrier during the subsequent electroplating process. Increasing the height of the spacer layer 20 allows for a corresponding increase in the height of the subsequently formed electroplated layer.
[0041] Along the direction perpendicular to the stacking arrangement, the width of the spacer layer 20 can be minimized as much as possible. The width of the spacer layer 20 determines the distance between adjacent electroplated layers formed subsequently. In some embodiments, the width of the spacer layer 20 can be less than 20 μm.
[0042] Step S3: Please refer to Figure 5 Electroplating is performed on the circuit board 10 to form a first electroplating layer 31 on the side of the conductive part 132 and a second electroplating layer 41 on the surface of the conductive lead 134. The first electroplating layer 31 also covers part of the surface of the first insulating layer 136 to form a groove 312.
[0043] During the electroplating process, a clamp (not shown) can be used to hold the conductive lead 134 at the clamp point 138 (see Figure 138). Figure 1 The electrode serves as the cathode to electroplate the circuit board 10, forming an electroplated layer (not shown, including a first electroplated layer 31 and a second electroplated layer 41). The electroplated layer is formed on the surface of the conductive layer 13 to form circuits together with the conductive layer 13 (not shown). Each conductive portion 132 forms a pad 30 with the corresponding first electroplated layer 31. The first electroplated layer 31 forms a groove 312 facing away from the surface of the dielectric layer 11, and the first electroplated layer 31 covers the conductive portion 132 exposed to the surfaces of the dielectric layer 11 and the first insulating layer 136. After the spacer layer 20 is provided and the electroplated layer is formed through the electroplating step, the distance between adjacent lines is reduced, which can increase the wiring density of the circuit board 100, that is, the increase in wiring density is not limited by etching capability.
[0044] The sides of both the first electroplated layer 31 and the second electroplated layer 41 are connected to the spacer layer 20. By controlling the electroplating conditions, the height of the first electroplated layer 31 can be increased, thereby increasing the recess depth of the groove 312.
[0045] The distance between adjacent pads 30 and the distance between adjacent pads 30 and the second electroplated layer 41 can be controlled by the width of the spacer layer 20. For example, the width of the spacer layer 20 can be reduced, and the wiring density of the circuit board 100 can be increased.
[0046] The surface flatness of the spacer layer 20 determines the flatness of the first electroplated layer 31 and the second electroplated layer 41. If the surface flatness of the spacer layer 20 is good, then the surface flatness of the first electroplated layer 31 and the second electroplated layer 41 will also be good.
[0047] In other embodiments, the step of forming the spacer layer 20 may also be omitted. The deposition rate of the electroplated layer can be adjusted by modifying the electroplating conditions and the solution formulation. For example, reducing the Cu content in the electroplating solution... 2+ and H + The proportion of [a specific substance] can reduce the deposition rate of electroplating; or adding an appropriate amount of leveling agent, such as an organic compound containing a quaternary amine structure, can reduce the deposition rate of the N-position due to the strong positive charge of this molecule. + It will be adsorbed onto the high current region of the cathode surface, and react with Cu. 2+ Competing for high current density regions significantly reduces Cu 2+ The deposition rate can be reduced by electrostatic adsorption onto the surface, thereby decreasing the current density of the conductive part 132 near the dielectric layer 11 and thus reducing the deposition rate. Compared to etching, the electroplating of conductive leads 134 in this embodiment of the application is beneficial to improving the etching factor and reducing the line spacing, which is suitable for high-density wiring.
[0048] Leveling agents (such as organic compounds containing thiol structures) can also be added to the solution, which is beneficial for Cu 2+ This forms a complex, thereby accelerating the nucleation rate of copper.
[0049] Step S4: Please refer to Figure 6 Remove the first insulating layer 136 and the spacer layer 20.
[0050] In some embodiments, the entire first insulating layer 136 and the entire spacer layer 20 may be removed, exposing the dielectric layer 11 to the surfaces of the pads 30 and the second electroplated layer 41.
[0051] In other embodiments, only the portion of the spacer layer 20 protruding from the pad 30 and the second electroplated layer 41 may be removed, and the remaining spacer layer 20 may serve as an insulating layer for the spacer pad 30 and / or the second electroplated layer 41.
[0052] Step S5: Please refer to Figure 7 A solder resist layer 50 is formed, which covers a portion of the first electroplated layer 31 and the second electroplated layer 41, with the groove 312 exposed to the solder resist layer 50.
[0053] A portion of the first electroplated layer 31 and the surface of the conductive portion 132 covered by the first insulating layer 136 are exposed to the solder resist layer 50. Since the surface of the conductive portion 132 covered by the first insulating layer 136 has not been etched, the surface smoothness is good, which helps to increase the reliability of the electrical connection.
[0054] Step S6: Please refer to Figure 8 A surface treatment layer 55 is formed on the surface of the first electroplated layer 31 and the conductive part 132 exposed to the solder resist layer 50.
[0055] The surface treatment layer 55 can increase the conductivity of the solder pad 30 and prevent the first electroplated layer 31 and the conductive part 132 from being oxidized on the surface of the solder resist layer 50. The surface treatment layer 55 can be a gold layer.
[0056] Please see Figure 9 In some embodiments, the method for manufacturing the circuit board 10 may include the following steps:
[0057] Step S111: Cover the substrate 60 with tape 63. The substrate 60 includes a dielectric layer 11 and a first copper layer 61 located on the surface of the dielectric layer 11. The tape 63 covers a portion of the surface of the first copper layer 61.
[0058] The substrate 60 can be a copper-clad laminate or a circuit board. In this embodiment, the substrate 60 is a single-sided copper-clad laminate.
[0059] The number of tapes 63 is the same as the number of conductive leads 134 subsequently formed. Tape 63 includes a substrate layer (not shown) and an adhesive layer (not shown), the adhesive layer being located between the substrate layer and the first copper layer 61, and the adhesive layer serving an adhesive function.
[0060] The substrate layer can be made of polyvinyl chloride (PVC), polyethylene (PE), polypropylene, or polyethylene glycol terephthalate (PET). The adhesive layer can be an acrylic pressure-sensitive adhesive.
[0061] The adhesive tape 63 has an adhesive strength greater than 2 N / cm at room temperature (e.g., 10℃-20℃), but its adhesive strength decreases significantly after heating (e.g., 60℃-80℃), for example, to less than 0.2 N / cm.
[0062] Step S112: Cover the surface of the first copper layer 61 exposed to the tape 63 with a first dry film 65.
[0063] The first dry film 65 can also cover the tape 63.
[0064] Step S113: Expose and develop the first dry film 65 to form the first insulating layer 136.
[0065] The number of first insulating layers 136 is the same as the number of subsequently formed pads 30. The first insulating layers 136 are spaced apart from the tape 63. The first insulating layers 136 cover the surface of the first copper layer 61. In subsequent processes, the surface of the first copper layer 61 covered by the first insulating layers 136 is not etched, which helps to improve the surface flatness of the subsequently formed pads 30.
[0066] Step S114: Etch the first copper layer 61 to form the conductive part 132 and the conductive lead 134. The first copper layer 61 covered by the first insulating layer 136 is etched to form the conductive part 132, and the first copper layer 61 covered by the tape 63 is etched to form the conductive lead 134.
[0067] Step S115: Remove tape 63 to obtain circuit board 10 (see [link]). Figure 2 ).
[0068] The adhesive strength of the tape 63 can be reduced by heating it in a drying oven, and then the tape 63 can be removed without affecting the quality of the surface of the first copper layer 61 in the bonding area.
[0069] Please see Figure 10 In other embodiments, a method for manufacturing a circuit board 10 is also provided, which may include the following steps:
[0070] Step S121: Cover the substrate 60 with a second dry film 70. The substrate 60 includes a dielectric layer 11 and a first copper layer 61 located on the surface of the dielectric layer 11. The second dry film 70 covers the first copper layer 61.
[0071] Step S122: Expose and develop the second dry film 70 to form the second insulating layer 71, and a portion of the surface of the first copper layer 61 is exposed to the second insulating layer 71.
[0072] Step S123: Form a shielding layer 73 on the surface of the first copper layer 61 exposed to the second insulating layer 71.
[0073] Step S124: Remove the second insulating layer 71, and press the third dry film 80 to cover the first copper layer 61 exposed to the shielding layer 73.
[0074] The third dry film 80 can also cover the shielding layer 73.
[0075] Step S125: Expose and develop the third dry film 80 to form the first insulating layer 136, the first insulating layer 136 and the masking layer 73 are spaced apart.
[0076] Step S126: Etch a portion of the first copper layer 61 and the masking layer 73 to form the conductive portion 132 and the conductive lead 134, and remove the first insulating layer 136 to obtain the circuit board 10 (see [link]). Figure 2The first copper layer 61 covered by the first insulating layer 136 is etched to form a conductive part 132, and the first copper layer 61 covered by the shielding layer 73 is etched to form a conductive lead 134.
[0077] Please refer to it again. Figure 8 This application embodiment also provides a circuit board 100, which may include a dielectric layer 11, a plurality of pads 30 and conductive leads 134, wherein the pads 30 and conductive leads 134 are located on the same surface of the dielectric layer 11.
[0078] Adjacent pads 30 are spaced apart. Each pad 30 includes a conductive portion 132 and a first electroplated layer 31. The conductive portion 132 is located on the surface of the dielectric layer 11. The first electroplated layer 31 covers the conductive portion 132 away from the upper surface of the dielectric layer 11 and is connected to the dielectric layer 11. The conductive portion 132 also includes a side surface, which connects to the upper surface and the dielectric layer 11. The first electroplated layer 31 covers the side surface. A groove 312 is formed on the surface of the first electroplated layer 31 away from the dielectric layer 11, and the conductive portion 132 is exposed in the groove 312 away from the upper surface of the dielectric layer 11.
[0079] The conductive lead 134 is spaced apart from the pad 30.
[0080] In some embodiments, the circuit board 100 further includes a second electroplating layer 41, which covers the conductive leads 134 and is connected to the dielectric layer 11.
[0081] The circuit board 100 also includes a solder resist layer 50 that covers a portion of the first electroplated layer 31, the groove 312 is exposed to the solder resist layer 50, and the solder resist layer 50 also fills the spaces between adjacent solder pads 30.
[0082] Please see Figure 11 This application embodiment also provides a circuit board assembly 200, which includes a circuit board 100, electronic components 210 and conductive paste 220. The conductive paste 220 is housed in a groove 312 and connected to the upper surface and the electronic components 210 so that the electronic components 210 are electrically connected to the circuit board 100.
[0083] The method for manufacturing the circuit board 100 provided in this application embodiment first forms a conductive portion 132 by etching, and then forms a first electroplating layer 31 by electroplating, thereby forming a pad 30. This method is beneficial for improving the etching factor, forming lines with smaller spacing, and increasing wiring density. In addition, by shielding with the first insulating layer 136, it is easier to form the pad 30 with grooves 312 during the electroplating process. During the process of mounting the electronic component 210 onto the circuit board 100, the conductive paste 220 is placed in the grooves 312 and then reflow soldered. After the conductive paste 220 melts, due to the blocking effect of the grooves 312, the molten conductive paste 220 is located in the corresponding grooves 312, reducing or avoiding the possibility of bridging short circuits.
[0084] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.
Claims
1. A method for manufacturing a circuit board, characterized in that, Includes the following steps: A circuit board is provided, including a dielectric layer, a plurality of conductive portions and a first insulating layer, wherein the conductive portions are located on the surface of the dielectric layer, the first insulating layer covers the conductive portions away from the upper surface of the dielectric layer, and the conductive portions further include side sides, the side sides being connected to the upper surface and the dielectric layer; A spacer layer is formed between adjacent conductive portions, the spacer layer being spaced apart from the conductive portions; Electroplating is performed on the circuit board to form a first electroplating layer on the side surface. The first electroplating layer covers the side surface and a portion of the surface of the first insulating layer to form a groove. Remove the first insulating layer and the spacer layer; as well as A solder resist layer is formed, which covers a portion of the first electroplated layer, and the groove is exposed to the solder resist layer.
2. The method for manufacturing a circuit board according to claim 1, characterized in that, The method for manufacturing the circuit board includes the following steps: A first dry film is coated on a substrate, the substrate including the dielectric layer and a first copper layer located on the surface of the dielectric layer, the first dry film covering the first copper layer; The first dry film is exposed and developed to form the first insulating layer; The first copper layer is etched to form the conductive portion, and the first copper layer covered by the first insulating layer is etched to form the conductive portion.
3. The method for manufacturing a circuit board according to claim 2, characterized in that, The circuit board also includes conductive leads, which are spaced apart from the conductive portion; The method for manufacturing the circuit board further includes: Prior to the step of covering the surface of the substrate with the first dry film, adhesive tape is applied to the substrate, the tape covering a portion of the surface of the first copper layer; When the first dry film is applied, the first dry film covers the first copper layer exposed on the surface of the tape; After the first dry film is exposed and developed to form the first insulating layer, the first insulating layer is spaced apart from the tape; and After etching the first copper layer, the tape is removed, and the first copper layer covered by the tape is etched to form the conductive lead.
4. The method for manufacturing a circuit board according to claim 3, characterized in that, When the circuit board includes the conductive lead, the spacer layer is also formed between the conductive lead and the conductive portion, and the spacer layer is spaced apart from the conductive lead and the conductive portion.
5. The method for manufacturing a circuit board according to claim 1, characterized in that, The circuit board also includes conductive leads, which are spaced apart from the conductive portion; The method for manufacturing the circuit board further includes: A second dry film is coated on a substrate, the substrate including the dielectric layer and a first copper layer located on the surface of the dielectric layer, the second dry film covering the first copper layer; The second dry film is exposed and developed to form a second insulating layer, with a portion of the surface of the first copper layer exposed to the second insulating layer. A shielding layer is formed on the surface of the first copper layer exposed to the second insulating layer; Remove the second insulating layer and press a third dry film, the third dry film covering the first copper layer exposed to the shielding layer; The third dry film is exposed and developed to form the first insulating layer, the first insulating layer being spaced apart from the masking layer; and A portion of the first copper layer and the shielding layer are etched to form the conductive portion and the conductive lead, wherein the first copper layer covered by the shielding layer is etched to form the conductive lead.
6. The method for manufacturing a circuit board according to claim 5, characterized in that, During the electroplating of the circuit board, a second electroplating layer is also formed on the surface of the conductive leads.
7. A circuit board assembly, characterized in that, include: Dielectric layer; Multiple pads are located on the surface of the dielectric layer, and adjacent pads are spaced apart. Each pad includes a conductive portion and a first electroplated layer. The conductive portion is located on the surface of the dielectric layer and includes an upper surface and a side surface. The side surface connects the upper surface and the dielectric layer. The first electroplated layer covers the side surface. The surface of the first electroplated layer facing away from the dielectric layer has a groove, and the upper surface is exposed to the groove. The conductive paste is contained in the groove and connected to the upper surface; Electronic components are connected to the conductive paste; as well as A solder resist layer covers a portion of the first electroplated layer, the grooves are exposed in the solder resist layer, and the solder resist layer also fills the spaces between adjacent solder pads.
8. The circuit board assembly according to claim 7, characterized in that, The circuit board also includes conductive leads, which are located on the surface of the dielectric layer where the pads are disposed, and the conductive leads are spaced apart from the pads.