Storage unit, memory and access method thereof, and electronic equipment

Abstract

A memory cell, a memory and an access method thereof, and an electronic device, the memory comprising: a plurality of layers of memory arrays stacked along a direction perpendicular to a substrate, and a plurality of first word lines in one-to-one correspondence with the plurality of layers of memory arrays, the memory arrays comprising a plurality of memory cells distributed along the array, and a plurality of second word lines corresponding to rows of the plurality of layers of memory arrays, each memory cell comprises a transistor, the transistor comprises a first gate electrode and a second gate electrode, the first gate electrodes of the memory cells in the same layer are connected to the first word line corresponding to the layer, and the second gate electrodes of the memory cells in the same row in different layers are connected to the second word line corresponding to the row. According to the scheme provided by the embodiment, one row of storage units can be selected through the first word line and the second word line, the number of word line drivers is reduced, meanwhile, a gating transistor for word line gating does not need to be arranged, the process step of manufacturing the gating transistor does not need to be increased, the process is simplified, the cost is reduced, and the control logic is simple.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a storage unit, a memory and an access method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical size of devices is getting smaller and smaller, and the types and number of devices contained in a single chip are increasing, so that any slight difference in process production may affect the performance of the device. In order to reduce the cost of the product as much as possible, people hope to minimize the number of devices used on the basis of achieving the required functions. In a conventional 1T1C memory, each storage cell includes an access transistor and a capacitor. The access transistor is connected to a word line and a bit line, the word line is connected to a word line driver, and the bit line is connected to a sense amplifier. The access transistor is selected through the word line, and data is read and written through the bit line. If each word line is connected to an independent word line driver, when the number of storage cells included in the memory is large, the number of word line drivers is huge, the process is complex, the cost is high, and the device size is too large. Therefore, due to considerations such as device size, cost, and process difficulty, it is necessary to reduce the number of word line drivers. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present application provide a storage unit, a memory and an access method thereof, and an electronic device, which reduce the number of word line drivers.

[0005] An embodiment of the present disclosure provides a storage unit, including a transistor and a capacitor connected to the transistor, wherein the transistor includes a first gate electrode and a second gate electrode, and the first gate electrode is connected to a first word line, and the second gate electrode is connected to a second word line, and the first word line and the second word line are connected to different signal terminals.

[0006] An embodiment of the present disclosure provides a memory, comprising: a multi-layer memory array stacked along a third direction perpendicular to a substrate, and a plurality of first word lines corresponding one to one with the multi-layer memory array, wherein the memory array comprises a plurality of memory cells distributed in an array along a first direction parallel to the substrate and along a second direction parallel to the substrate, the memory further comprising a plurality of second word lines corresponding to rows of the multi-layer memory array, each second word line corresponding to the same row of the multi-layer memory array, the memory cell comprising a transistor, the transistor comprising a first gate electrode and a second gate electrode, the first gate electrode of the memory cells in the same layer being connected to the first word line corresponding to the layer, and the second gate electrodes of the memory cells in the same layer distributed along the first direction in different layers being connected to the second word line corresponding to the row.

[0007] In some embodiments, each layer of the storage array also includes multiple first sub-word lines extending along the second direction, the first gate electrodes of the storage cells in the same layer and the same column are connected to a first sub-word line, the first gate electrodes of the storage cells in different columns of the same layer are connected to different first sub-word lines, and multiple first sub-word lines in the same layer are connected to form one first word line.

[0008] In some embodiments, each layer of the storage array also includes multiple first sub-word lines extending along the first direction, the first gate electrodes of the storage cells in the same layer and the same row are connected to a first sub-word line, the first gate electrodes of the storage cells in different rows of the same layer are connected to different first sub-word lines, and multiple first sub-word lines in the same layer are connected to form one first word line.

[0009] In some embodiments, each layer of the storage array also includes multiple second sub-word lines extending along the first direction, the second gate electrodes of the storage cells in the same layer and the same row are connected to a second sub-word line, the second gate electrodes of the storage cells in different rows of the same layer are connected to different second sub-word lines, and multiple second sub-word lines in the same layer are connected to form one second word line.

[0010] In some embodiments, the memory further includes: a plurality of bit lines extending along the third direction and a plurality of common bit lines extending along the second direction, a bit line connecting storage cells at the same position of a multi-layer storage array, bit lines in the same column distributed along the second direction are connected to the same common bit line, and bit lines in different columns are connected to different common bit lines.

[0011] In some embodiments, each of the bit lines is connected to the common bit line via a gating subcircuit, the gating subcircuit is also connected to a gating control line, and a plurality of first gating subcircuits respectively connected to a plurality of bit lines distributed along a first direction are connected to the same gating control line, and the gating subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the gating control line.

[0012] In some embodiments, the gating control line connected to the plurality of gating subcircuits respectively connected to the plurality of bit lines in the i-th row is connected to the second word line corresponding to the memory cells in the i-th row.

[0013] The present disclosure provides a method for accessing the above memory, including:

[0014] During the data reading and writing stage, according to the target layer and target row where the storage unit to be operated is located, an activation signal is loaded on the first word line corresponding to the target layer, and a deactivation signal is loaded on the first word line not corresponding to the target layer; an activation signal is loaded on the second word line corresponding to the target row, and a deactivation signal is loaded on the second word line not corresponding to the target row.

[0015] In some embodiments, the method further includes, during the data reading and writing phase, loading an on-level signal on a gate control line connected to the bit line of the target row, and loading an off-level signal on a gate control line connected to the bit line of a non-target row.

[0016] In some embodiments, the activation signal loaded on the second word line corresponding to the target row and the turn-on level signal loaded on the enable control line connected to the bit line of the target row are the same signal, and the inactivation signal loaded on the second word line corresponding to the non-target row and the turn-off level signal loaded on the enable control line connected to the bit line of the non-target row are the same signal.

[0017] In some embodiments, the method further includes, in a precharge phase, for each memory cell, loading a non-activation signal on at least one of the first word line and the second word line connected to the memory cell, and loading an on-level signal on all the selection control lines.

[0018] An embodiment of the present disclosure provides an electronic device, comprising the memory described in any of the above embodiments.

[0019] In some embodiments, the electronic device further includes a control circuit, and the control circuit is configured to access the memory according to the access method described in any of the above embodiments.

[0020] The disclosed embodiment provides a storage unit, a memory and an access method thereof, and an electronic device, wherein the memory comprises: a multi-layer storage array stacked along a third direction perpendicular to a substrate, and a plurality of first word lines corresponding to the multi-layer storage array one by one, wherein the storage array comprises a plurality of storage cells arranged in an array along a first direction and a second direction parallel to the substrate, and the storage also comprises a plurality of second word lines corresponding to rows of the multi-layer storage array, each second word line corresponding to the same row of the multi-layer storage array, and the storage unit comprises a transistor, and the transistor comprises a first gate electrode and a second gate electrode, wherein the first gate electrode of the storage unit in the same layer is connected to the first word line corresponding to the layer, and the second gate electrode of the storage unit in the same row of different layers is connected to the second word line corresponding to the row. The scheme provided by the embodiment can select a row of storage units through the first word line and the second word line, and while reducing the number of word line drivers, it is not necessary to set a gate transistor for word line selection, and it is not necessary to increase the process steps for manufacturing the gate transistor, thereby simplifying the process, reducing the cost, and having simple control logic.

[0021] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings.

[0022] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0024] Figure 1 An equivalent circuit diagram of a memory cell provided for an exemplary embodiment;

[0025] Figure 2 An equivalent circuit diagram of a memory provided for an exemplary embodiment;

[0026] Figure 3 An equivalent circuit diagram of a memory is provided for another exemplary embodiment. DETAILED DESCRIPTION

[0027] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0028] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0029] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0030] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0031] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0032] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0033] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0034] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0035] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0036] One way to reduce word line drivers is to set a gate transistor to enable word line gating to reduce word line drivers. However, the manufacturing of the gate transistor needs to be performed in addition to the manufacturing of the memory array, which increases the process steps and increases the cost.

[0037] In the embodiment of the present disclosure, a dual-gate transistor is used in the memory cell, and the two gate electrodes of the transistor are respectively connected to different word lines, the first gate electrodes of the memory cells in the same layer are connected to the same first word line, and the second gate electrodes of the memory cells in the same layer and the same row are connected to the same second word line. A row of memory cells is selected by the first word line and the second word line, and the purpose of selecting a row of memory cells and reducing the number of word line drivers can be achieved without the need for selecting transistors.

[0038] Figure 1 FIG. 1 is a schematic diagram of an equivalent circuit of a storage unit provided by an exemplary embodiment. Figure 1 As shown, the memory cell provided in this embodiment includes a transistor (also called an access transistor) and a capacitor Cs, wherein the transistor includes a first gate electrode G1, a second gate electrode G2, a first electrode E1 and a second electrode E2, wherein the first gate electrode G1 is connected to a first word line WL1, the second gate electrode G2 is connected to a second word line WL2, the first electrode E1 is connected to a bit line BL, the second electrode E2 is connected to a first end of the capacitor Cs, the second end of the capacitor Cs is connected to a preset voltage end Vs, and the first end of the capacitor Cs serves as a storage node SN. The first word line WL1 and the second word line WL2 are connected to different signal ends, that is, the first word line WL1 and the second word line WL2 are independently controlled. The memory cell can be applied to a 3D stacked 1T1C memory, so that a row of memory cells can be gated by the first word line WL1 and the second word line WL2 without the need for a gate transistor. Compared with a single-gate 1T1C memory cell, the solution provided in this embodiment provides support for implementing a 3D stacked 1T1C memory with a simpler process.

[0039] In some embodiments, the transistor may be an N-type transistor or a P-type transistor.

[0040] In some embodiments, the transistor is an N-type transistor, and when the first word line WL1 and the second word line WL2 are both loaded with high-level signals, the transistor is turned on, and when at least one of the first word line WL1 and the second word line WL2 is loaded with a low-level signal, the transistor is turned off; or, the transistor is a P-type transistor, and when the first word line WL1 and the second word line WL2 are both loaded with low-level signals, the transistor is turned on, and when at least one of the first word line WL1 and the second word line WL2 is loaded with a high-level signal, the transistor is turned off.

[0041] Figure 2 FIG. 1 is a schematic diagram of a memory equivalent circuit provided by an exemplary embodiment. Figure 2As shown, the memory may include: a multi-layer stacked memory array (k layers, memory array L1 to memory array Lk), the multi-layer memory array is stacked along a third direction z. Each layer of the memory array includes a plurality of memory cells 100 arrayed along a first direction x and a second direction y, respectively, and a plurality of first sub-word lines Sub_WL1 extending along the second direction Y, and a plurality of second sub-word lines Sub_WL2 extending along the first direction X. The structure of the memory cell 100 is referred to as Figure 1 , no further details are given. The multiple first sub-word lines Sub_WL1 of each layer are spaced apart along the first direction x, and the multiple second sub-word lines Sub_WL2 of each layer are spaced apart along the second direction y. The memory further includes multiple bit lines BL extending along the third direction z, and the multiple bit lines BL are arrayed along the first direction x and the second direction y. Each layer of the memory array includes n rows and m columns of memory cells 100, and includes m first sub-word lines Sub_WL1, n second sub-word lines Sub_WL2, wherein the first sub-word line of the r-th layer and the j-th column is Sub_WL1_Cj_r, j is 1 to m, and r is 1 to k; the second sub-word line of the r-th layer and the i-th row is Sub_WL2_Ri_r, i is 1 to n, and r is 1 to k. The memory includes n rows and m columns of bit lines BL, and the bit line of the i-th row and the j-th column is the bit line BL_i_j, i is 1 to n, and j is 1 to m. The first gate electrode G1 of the memory cell C_i_j_r in the rth layer, the ith row, and the jth column is connected to the first sub-word line Sub_WL1_Cj_r, the second gate electrode G2 is connected to the second sub-word line Sub_WL2_Ri_r, and the first electrode E1 is connected to the bit line BL_i_j. The first direction x and the second direction y are parallel to the substrate ( Figure 2 The substrate is not shown in the figure), and the third direction z is perpendicular to the substrate. The first direction x and the second direction y may intersect. In some embodiments, the first direction x and the second direction y may be perpendicular. The first direction x is also called the row direction, and the second direction y is also called the column direction. The preset voltage terminal Vs may be, for example, a ground terminal.

[0042] In some embodiments, a plurality of first sub-word lines Sub_WL1 of the same layer are connected to form a first word line, and each layer of memory cells corresponds to a first word line, that is, m first sub-word lines Sub_WL1_C1_r to Sub_WL1_Cm_r of the rth layer are connected to form the rth first word line WL1_r, where r is 1 to k. For example, m first sub-word lines Sub_WL1_C1_1 to Sub_WL1_Cm_1 of the 1st layer are connected to form the 1st first word line WL1_1, and m first sub-word lines Sub_WL1C1_k to Sub_WL1Cm_k of the kth layer are connected to form the kth first word line WL1_k. Each first word line WL1_r is connected to a first word line driver. Different first word lines WL1_r are connected to different first word line drivers.

[0043] In some embodiments, the plurality of first word line drivers connected to the plurality of first word lines WL1_r may be disposed on the same side of the memory array, but the embodiments of the present disclosure are not limited thereto and may be disposed on different sides as required.

[0044] In some embodiments, the first sub-word lines Sub_WL1 in the same layer may be connected by one or two connection lines disposed at the periphery of the memory array and extending along the first direction X. However, the embodiments of the present disclosure are not limited thereto, and the first sub-word lines Sub_WL1 in the same layer may be connected by other methods.

[0045] In some embodiments, a plurality of second sub-word lines Sub_WL2 in the same row of different layers are connected to form one second word line, and the same row of different layers corresponds to one second word line, that is, k second sub-word lines Sub_WL2_Ri_1 to Sub_WL2_Ri_k in the i-th row of the 1st to k-th layers are connected to form the i-th second word line WL2_i, where i is 1 to n. k second sub-word lines Sub_WL2_R1_1 to Sub_WL2_R1_k in the 1st row of the 1st to k-th layers are connected to form the 1st second word line WL2_1, and k second sub-word lines Sub_WL2_Rn_1 to Sub_WL2_Rn_k in the n-th row of the 1st to k-th layers are connected to form the n-th second word line WL2_n, where i is 1 to n. Each second word line WL2_i is connected to a second word line driver.

[0046] In some embodiments, the second word line WL2_i may be connected to the second word line driver at the side of the memory array facing the substrate, but the disclosed embodiments are not limited thereto. The second word line WL2_i may be connected to the second word line driver at the side of the memory array facing away from the substrate.

[0047] In some embodiments, multiple second sub-word lines Sub_WL2 in the same row on different layers may be connected by one or two connecting lines extending along a third direction Z arranged at the periphery of the memory array, but the embodiments of the present disclosure are not limited thereto, and multiple second sub-word lines Sub_WL2 in the same row on different layers may be connected by other means.

[0048] The memory provided in this embodiment can select a row of storage cells by activating a first word line and a second word line. For example, when the target layer is the pth layer and the target row is the qth row, an activation signal can be loaded on the second word line WL2_q and the first word line WL1_p, thereby selecting m storage cells in the i-th row of the rth layer. The solution provided in this embodiment can select a row of storage cells without setting a gate transistor for the word line. Compared with the solution of setting a gate transistor for the word line, there is no need to increase the process steps for the manufacture of the gate transistor, and the number of word line drivers is not large, the number of first word line drivers is k, the number of second word line drivers is n, and as the number of stacked layers increases, the number of additional words is also small (one word line driver for each layer). In addition, the circuit control logic is simple.

[0049] In some embodiments, the memory may further include a plurality of common bit lines CBL, a plurality of bit lines BL in the same column distributed along the second direction y may be connected to the same common bit line CBL, and bit lines BL in different columns may be connected to different common bit lines CBL, for example, the first column bit line BL is connected to the first common bit line CBL1, the second column bit line BL is connected to the second common bit line CBL2, and the mth column bit line BL is connected to the mth common bit line CBLm. A common bit line CBL is connected to a sense amplifier SA. Compared with the solution in which each bit line BL is connected to a sense amplifier SA, the solution provided in this embodiment can greatly reduce the number of sense amplifiers SA by using a common bit line CBL. Adjacent memory arrays may share the same SA.

[0050] In some embodiments, the common bit line CBL may be disposed on a side of the memory array away from the substrate, such as Figure 2 As shown, or, the memory array faces the substrate. When the memory includes a plurality of stacked memory arrays, the common bit line CBL may be disposed on the side of the stacked memory array facing the substrate, or away from the substrate.

[0051] In some embodiments, each bit line BL can be connected to the common bit line CBL through a gating subcircuit 10. The gating subcircuit 10 can also be connected to a gating control line, and the gating subcircuit 10 is configured to connect or disconnect the bit line BL and the common bit line CBL under the control of the gating control line (that is, the bit line BL and the common bit line CBL are electrically connected, or disconnected). That is, the signal of the common bit line CBL is loaded or not loaded on the bit line BL under the control of the gating control line. The scheme provided in this embodiment sets a gating subcircuit, which can only gating the target bit line to be read and shutting off the non-target bit line, thereby reducing the capacitance of the CBL, reducing power consumption, and improving the reading speed. However, the disclosed embodiment is not limited to this. In another exemplary embodiment, the gating subcircuit 10 may not be set.

[0052] In some embodiments, the gating subcircuit 10 may be disposed on the side of the memory array away from the substrate, between the bit line BL and the common bit line CBL. However, the disclosed embodiments are not limited thereto, and the gating subcircuit 10 may be disposed on the side of the memory array facing the substrate.

[0053] In some embodiments, the gating sub-circuits 10 connected to the bit lines BL in the same row distributed along the first direction x can be connected to the same gating control line, and the gating sub-circuits of the bit lines BL in different rows are connected to different gating control lines, and n rows of bit lines BL are respectively connected to n different gating control lines. Figure 2 As shown, the gating sub-circuits 10 connected to the bit lines BL of the first row are all connected to the first gating control line S_1, the gating sub-circuits 10 connected to the bit lines BL of the second row are all connected to the second gating control line S_2, and so on, the gating sub-circuits 10 connected to the bit lines BL of the nth row are all connected to the nth gating control line S_n. Thus, a bit line BL can be selected through the common bit line CBL and the gating control line. For example, the jth common bit line CBLj is loaded with an activation signal (the other common bit lines are loaded with an inactive signal), the ith gating control line S_i selects the corresponding gating sub-circuit 10 (the other gating control lines do not select the corresponding gating sub-circuit 10), and the bit line BL_i_j of the ith row and the jth column is loaded with an activation signal.

[0054] In some embodiments, only one bit line BL is enabled at a time, which can reduce the capacitive load of the SA and the capacitance of the memory cell.

[0055] In some embodiments, the gating subcircuit 10 may include a first transistor T1, a gate electrode of the first transistor T1 is connected to the gating control line, a first electrode is connected to the bit line BL, and a second electrode is connected to the common bit line CBL. The structure of the gating subcircuit 10 described in this embodiment is only an example, and may be other circuits that can implement gating.

[0056] In some embodiments, the first transistor T1 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto, and the first transistor T1 may be a P-type transistor.

[0057] In some embodiments, when the second word line WL2_i corresponding to the i-th row is loaded with an activation signal, the gating control line S_i connected to the gating sub-circuit 10 connected to the bit line BL of the i-th row is loaded with a turn-on level signal to turn on the gating sub-circuit 10 connected to the bit line BL of the i-th row. When the first word line WL1_r corresponding to the r-th layer is loaded with an activation signal, at this time, the storage cell of the i-th row of the r-th layer is gated, and the storage cell of the i-th row of the r-th layer can be accessed (read or written) through the BL of the i-th row.

[0058] In some embodiments, the second word line WL2_i can be connected to the gating control line S_i connected to the gating subcircuit 10 connected to the bit line BL of the i-th row, i is 1 to n, that is, the same signal driver can be used to load the same signal to the second word line WL2_i and the gating control line S_i, that is, the activation signal and the start-level signal of the gating subcircuit use the same signal. The solution provided in this embodiment can reduce the number of control lines, as well as reduce the control circuit that generates the control signal, reduce the device occupied area, and simplify the control logic. At this time, the gating subcircuit 10 can be set on the side of the storage array facing the substrate. The disclosed embodiment is not limited to this, the gating subcircuit 10 can be set on the side of the storage array away from the substrate, and the second word line WL2_i can be connected to the second word line driver on the side of the storage array away from the substrate.

[0059] Figure 3 A memory schematic diagram is provided for another exemplary embodiment. Figure 3 As shown, in the memory provided by this embodiment, the extension direction of the first sub-word line Sub_WL1 is consistent with the extension direction of the second sub-word line Sub_WL2, that is, in this embodiment, the memory includes a plurality of first sub-word lines Sub_WL1 extending along the first direction X, and the plurality of first sub-word lines Sub_WL1 of each layer are spaced along the second direction Y. The first sub-word line of the i-th row of the r-th layer is Sub_WL1_Ri_r, i is 1 to n, and r is 1 to k. The storage cell C_i_j_r of the i-th row and j-th column of the r-th layer is connected to the first sub-word line Sub_WL1_Ri_r. The plurality of first word line drivers connected to the plurality of first word lines WL1_r can be arranged on the same side of the memory. The plurality of first sub-word lines Sub_WL1 of the same layer can be connected by two connecting lines extending along the second direction Y arranged at the periphery of the memory array. Figure 3 The description of the storage unit, the first word line, etc. in the embodiment is referred to the previous embodiment and will not be repeated here. Figure 2The solution in which the first sub-word line and the second sub-word line extend in different directions is easier to manufacture.

[0060] In some embodiments, a plurality of first sub-word lines Sub_WL1 of the same layer are connected to form a first word line, and each layer corresponds to a first word line, that is, n first sub-word lines Sub_WL1_R1_r to Sub_WL1_Rn_r of the rth layer are connected to form the rth first word line WL1_r, where r is 1 to k. n first sub-word lines Sub_WL1_R1_1 to Sub_WL1_Rn_1 of the 1st layer are connected to form the 1st first word line WL1_1, and n first sub-word lines Sub_WL1_R1_k to Sub_WL1_Rn_k of the kth layer are connected to form the kth first word line WL1_k. Each first word line WL1_r is connected to a first word line driver.

[0061] An embodiment of the present disclosure provides a method for accessing a memory, which is applied to the memory described in any of the above embodiments. The access method may include:

[0062] In the data reading and writing stage, according to the target layer and target row where the storage unit to be operated is located, an activation signal is loaded on the first word line corresponding to the target layer, and a non-activation signal is loaded on the first word line corresponding to the non-target layer; an activation signal is loaded on the second word line corresponding to the target row, and a non-activation signal is loaded on the second word line corresponding to the non-target row (at this time, only the first gate electrode and the second gate electrode of the transistor of the storage unit of the target row of the target layer are loaded with the activation signal, so that the transistor of the storage unit of the target row of the target layer can be turned on); a turn-on level signal is loaded on the enable control line connected to the bit line of the target row (so that the enable subcircuit connected to the bit line of the target row is in a connected state), and a turn-off level signal is loaded on the enable control line connected to the bit line of the non-target row (so that the enable subcircuit connected to the bit line of the non-target row is in an off state).

[0063] This embodiment provides a method for accessing a memory, which can access a row of memory cells through a first word line, a second word line and a gate control line, and the control logic is simple.

[0064] The on-level signal is a signal that can make the corresponding gating subcircuit in a connected state, and the off-level signal is a signal that can make the corresponding gating subcircuit in a closed state. The data reading and writing phase may include a data reading phase and a data writing phase.

[0065] In some embodiments, it may also include:

[0066] In the precharge phase, for each memory cell, a non-activation signal is applied to at least one of the first word line and the second word line connected to the memory cell, and an on-level signal is applied to all the gating control lines, so that all access transistors can be turned off, all gating subcircuits can be connected, and the bit lines can be precharged.

[0067] In some embodiments, the activation signal loaded on the second word line corresponding to the target row and the turn-on level signal loaded on the enable control line connected to the bit line of the target row are the same signal, and the inactivation signal loaded on the second word line corresponding to the non-target row and the turn-off level signal loaded on the enable control line connected to the bit line of the non-target row are the same signal.

[0068] That is, the gating control line connected to the bit line of the same row and the corresponding second word line can be controlled by the same signal, which reduces the control signal, makes the control simpler, and reduces the signal driver, which is conducive to reducing the cost and reducing the device area. At this time, the gating control line S_i connected to the gating subcircuit 10 connected to the second word line WL2_i and the bit line BL of the i-th row can be connected together, where i is 1 to n, and n is the number of rows of storage cells contained in each layer of the storage array.

[0069] The following describes the working process of the memory by using an embodiment. Figure 2 Taking the memory shown as an example, in this embodiment, the memory cell 100 is a 1T1C structure, the access transistor is an N-type MOS tube, the first transistor T1 is an N-type MOS tube, the selection control line S_i is connected to the second word line WL2_i, i is 1 to n, and the common bit line CBL can also be connected to the pre-charging sub-circuit. The working phase of the memory may include a pre-charging phase, a data reading phase, and a data write-back phase, wherein:

[0070] In the pre-charging stage, the first word lines WL1_1 to WL1_k are all loaded with low-level signals, which are loaded onto the first sub-word line Sub_WL1, and the second word lines WL2_1 to WL2_n are all loaded with high-level signals (i.e., the selection control line S_i is loaded with a high-level signal). At this time, the selection sub-circuit is turned on, the access transistors of all storage cells are turned off, the pre-charging sub-circuit is turned on, and a pre-charging voltage of 1 / 2VDD is loaded on each common bit line CBL. Each common bit line CBL loads the pre-charging voltage to a column of bit lines BL connected thereto.

[0071] In the data reading stage, the pre-charging sub-circuit is turned off; taking the data of the storage cell 100 of the p-th layer and the q-th row as an example, among the first word lines WL1_1 to WL1_k, the first word line WL1_p corresponding to the p-th layer is loaded with a high-level signal, and the other first word lines WL1_r (where r is 1 to k and r≠p) are loaded with a low-level signal, and among the second word lines WL2_1 to WL2_n, the second word line WL2_q corresponding to the q-th row is loaded with a high-level signal, and the other WL2_i (where i is 1 to n and i≠q) are loaded with a low-level signal, Thus, the access transistor of the memory cell 100 in the p-th layer and the q-th row is turned on, and the access transistors of the other memory cells 100 are turned off, the selection subcircuit 10 connected to the bit line of the q-th row is turned on, and the common bit lines CBL1 to CBLm are respectively connected to the m bit lines of the q-th row, and charge is shared with the storage nodes of the m memory cells 100 in the p-th layer and the q-th row, respectively, and the sense amplifiers respectively connected to CBL1 to CBLm sense the voltages of CBL1 to CBLm to determine the data stored in the memory cell 100 in the p-th layer and the q-th row.

[0072] In the data write back stage, among the first word lines WL1_1 to WL1_k, WL1_p is loaded with a high level signal, and the remaining WL1_r (where r is 1 to k and r≠p) are loaded with a low level signal, and among the second word lines WL2_1 to WL2_n, WL2_q is loaded with a high level signal, and the remaining WL2_i (where i is 1 to n and i≠q) are loaded with a low level signal, and the common bit lines CBL1 to CBLm are respectively connected to the m bit lines in the qth row, and charge is shared with the storage nodes of the m storage cells 100 in the pth layer and the qth row, respectively, to realize data write back.

[0073] The solution provided in this embodiment does not need to use a selection transistor to select the storage cell. A row of storage cells can be selected using the first word line and the second word line. It has a simple structure and simple control logic. The same control signal is used to control the selection control line and the second word line of the same row, which reduces the number of control signal lines, reduces the required control circuit, and makes the control logic simpler.

[0074] The present disclosure also provides an electronic device, including the memory of the above-mentioned embodiment. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0075] In some embodiments, the electronic device may further include a control circuit, the control circuit being configured to access the memory according to any of the access methods described above. The control circuit may include a driver that generates a control signal to the first word line, the second word line, a gate control line, etc. The control circuit and the SA together implement access to the memory.

[0076] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A storage unit, characterized in that: The invention comprises a transistor and a capacitor connected to the transistor, wherein the transistor comprises a first gate electrode and a second gate electrode, wherein the first gate electrode is connected to a first word line, the second gate electrode is connected to a second word line, and the first word line and the second word line are connected to different signal terminals.

2. A memory, characterized in that: include: A multi-layer memory array stacked along a third direction perpendicular to a substrate, and a plurality of first word lines corresponding to the multi-layer memory array one by one, wherein the memory array includes a plurality of memory cells distributed in an array along a first direction parallel to the substrate and along a second direction parallel to the substrate, the memory also includes a plurality of second word lines corresponding to rows of the multi-layer memory array, each second word line corresponds to the same row of the multi-layer memory array, the memory cell includes a transistor, the transistor includes a first gate electrode and a second gate electrode, the first gate electrode of the memory cell in the same layer is connected to the first word line corresponding to the layer, and the second gate electrode of the memory cell in the same row distributed along the first direction in different layers is connected to the second word line corresponding to the row.

3. The memory according to claim 2, characterized in that: Each layer of the storage array also includes multiple first sub-word lines extending along the second direction, the first gate electrodes of the storage cells in the same layer and the same column are connected to a first sub-word line, the first gate electrodes of the storage cells in different columns of the same layer are connected to different first sub-word lines, and multiple first sub-word lines in the same layer are connected to form one first word line.

4. The memory according to claim 2, characterized in that: Each layer of the storage array also includes multiple first sub-word lines extending along the first direction, the first gate electrodes of the storage cells in the same layer and the same row are connected to a first sub-word line, the first gate electrodes of the storage cells in different rows of the same layer are connected to different first sub-word lines, and multiple first sub-word lines in the same layer are connected to form one first word line.

5. The memory according to claim 2, characterized in that: Each layer of the storage array also includes multiple second sub-word lines extending along the first direction, the second gate electrodes of the storage cells in the same layer and the same row are connected to a second sub-word line, the second gate electrodes of the storage cells in different rows of the same layer are connected to different second sub-word lines, and multiple second sub-word lines in the same layer are connected to form one second word line.

6. The memory according to claim 5, characterized in that: The memory also includes: a plurality of bit lines extending along the third direction and a plurality of common bit lines extending along the second direction, one bit line connects storage cells at the same position of a multi-layer storage array, bit lines in the same column distributed along the second direction are connected to the same common bit line, and bit lines in different columns are connected to different common bit lines.

7. The memory according to claim 6, characterized in that: Each of the bit lines is connected to the common bit line via a gating subcircuit, the gating subcircuit is also connected to a gating control line, and a plurality of first gating subcircuits respectively connected to a plurality of bit lines distributed along the first direction are connected to the same gating control line, and the gating subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the gating control line.

8. The memory according to claim 7, characterized in that: The gating control line connected to the plurality of gating subcircuits respectively connected to the plurality of bit lines in the i-th row is connected to the second word line corresponding to the memory cell in the i-th row.

9. A method for accessing a memory as claimed in any one of claims 2 to 8, characterized in that: include: During the data reading and writing stage, according to the target layer and target row where the storage unit to be operated is located, an activation signal is loaded on the first word line corresponding to the target layer, and a deactivation signal is loaded on the first word line not corresponding to the target layer; an activation signal is loaded on the second word line corresponding to the target row, and a deactivation signal is loaded on the second word line not corresponding to the target row.

10. The memory access method according to claim 9, characterized in that: The memory is a memory as described in any one of claims 6 to 8, and the method also includes, in the data reading and writing stage, loading an on-level signal on a selection control line connected to the bit line of the target row, and loading an off-level signal on a selection control line connected to the bit line of a non-target row.

11. The memory access method according to claim 10, characterized in that: The activation signal loaded on the second word line corresponding to the target row and the turn-on level signal loaded on the selection control line connected to the bit line of the target row are the same signal, and the inactivation signal loaded on the second word line corresponding to the non-target row and the turn-off level signal loaded on the selection control line connected to the bit line of the non-target row are the same signal.

12. The memory access method according to claim 10, characterized in that: The method further includes, in the precharge phase, for each memory cell, loading an inactive signal on at least one of the first word line and the second word line connected to the memory cell, and loading an on-level signal on all the selection control lines.

13. An electronic device, characterized in that: Comprising a memory as claimed in any one of claims 2 to 8.

14. The electronic device according to claim 13, characterized in that: The electronic device further comprises a control circuit, wherein the control circuit is configured to access the memory according to the memory access method according to any one of claims 9 to 12.

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