Memory, access method thereof and electronic equipment

Abstract

A memory and an access method thereof, and an electronic device, the memory comprising: a plurality of layers of memory arrays stacked along a third direction perpendicular to a substrate, the memory array comprising a plurality of memory cells distributed in an array, the memory further comprising a plurality of second word lines corresponding to rows of the plurality of layers of memory arrays, a plurality of first word lines corresponding to columns of the multilayer memory array; the memory cell comprises a transistor, the transistor comprises a first gate electrode and a second gate electrode, the first gate electrode is connected to the first word line corresponding to the column where the memory cell is located, and the second gate electrode is connected to the second word line corresponding to the row where the memory cell is located. According to the scheme provided by the embodiment of the invention, the memory units at the same position of different layers can be selected through the first word line and the second word line, so that the number of word line drivers is reduced, a gating transistor for word line gating does not need to be arranged, a process step for manufacturing the gating transistor does not need to be added, the process is simplified, the cost is reduced, and the production efficiency is improved. And the control logic is simple.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design in the field of semiconductor technology, and in particular to a memory and an access method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical size of devices is getting smaller and smaller, and the types and number of devices contained in a single chip are increasing, so that any slight difference in process production may affect the performance of the device. In order to reduce the cost of the product as much as possible, people hope to minimize the number of devices used on the basis of achieving the required functions. In a conventional 1T1C memory, each storage cell includes an access transistor and a capacitor. The access transistor is connected to a word line and a bit line, the word line is connected to a word line driver, and the bit line is connected to a sense amplifier. The access transistor is selected through the word line, and data is read and written through the bit line. If each word line is connected to an independent word line driver, when the number of storage cells included in the memory is large, the number of word line drivers is huge, the process is complex, the cost is high, and the device size is too large. Therefore, due to considerations such as device size, cost, and process difficulty, it is necessary to reduce the number of word line drivers. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present application provide a memory and an access method thereof, and an electronic device, which simplify the process and reduce the cost.

[0005] The present disclosure provides a memory, including:

[0006] A multi-layer memory array stacked along a third direction perpendicular to a substrate, the memory array comprising a plurality of memory cells distributed in an array along a first direction parallel to the substrate and along a second direction parallel to the substrate, the memory further comprising a plurality of second word lines corresponding to rows of the multi-layer memory array, a plurality of first word lines corresponding to columns of the multi-layer memory array, each of the second word lines corresponding to the same row of the multi-layer memory array, and each of the first word lines corresponding to the same column of the multi-layer memory array;

[0007] The memory cell includes a transistor, and the transistor includes a first gate electrode and a second gate electrode, the first gate electrode is connected to the first word line corresponding to the column where the memory cell is located, and the second gate electrode is connected to the second word line corresponding to the row where the memory cell is located.

[0008] In some embodiments, each layer of the storage array also includes multiple first sub-word lines extending along the third direction, the first gate electrodes of storage cells in the same row and column of different layers are connected to one of the first sub-word lines, the first gate electrodes of different storage cells in the same layer are connected to different first sub-word lines, and multiple first sub-word lines in the same column are connected to form one first word line.

[0009] In some embodiments, each layer of the storage array also includes multiple second sub-word lines extending along the third direction, the second gate electrodes of storage cells in the same row and column of different layers are connected to one second sub-word line, the second gate electrodes of different storage cells in the same layer are connected to different second sub-word lines, and multiple second sub-word lines in the same row are connected to form one second word line.

[0010] In some embodiments, each layer of the storage array further includes: a plurality of bit lines extending along the second direction; the memory further includes: a plurality of common bit lines; a bit line connects storage cells in the same column of the layer where the bit line is located, bit lines in the same layer are connected to the same common bit line, and bit lines in different layers are connected to different common bit lines.

[0011] In some embodiments, each of the bit lines is connected to the common bit line via a gating subcircuit, the gating subcircuit is also connected to a gating control line, a plurality of gating subcircuits respectively connected to a plurality of bit lines in the same column of different layers are connected to the same gating control line, and the gating subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the gating control line.

[0012] In some embodiments, the gating subcircuit includes a first transistor, the first transistor includes a first gate electrode, a second gate electrode, a first electrode and a second electrode, the first gate electrode and the second gate electrode of the first transistor are connected to the gating control line, the first electrode of the first transistor is connected to the bit line, and the second electrode of the first transistor is connected to the common bit line.

[0013] In some embodiments, the gating control line connected to the plurality of gating subcircuits respectively connected to the plurality of bit lines of the j-th column is connected to the first word line corresponding to the memory cell of the j-th column.

[0014] The present disclosure provides a method for accessing the above memory, including:

[0015] During the data reading and writing stage, according to the target row and target column where the storage unit to be operated is located, an activation signal is loaded on the second word line corresponding to the target row, and a deactivation signal is loaded on the second word line corresponding to the non-target row; an activation signal is loaded on the first word line corresponding to the target column, and a deactivation signal is loaded on the first word line corresponding to the non-target column.

[0016] In some embodiments, the method further includes, during the data reading and writing phase, loading an on-level signal on a strobe control line connected to the bit line of the target column, and loading an off-level signal on a strobe control line connected to the bit line of a non-target column.

[0017] In some embodiments, the activation signal loaded on the first word line corresponding to the target column and the turn-on level signal loaded on the enable control line connected to the bit line of the target column are the same signal, and the inactivation signal loaded on the first word line corresponding to the non-target column and the turn-off level signal loaded on the enable control line connected to the bit line of the non-target column are the same signal.

[0018] In some embodiments, the method further includes, in a precharge phase, for each memory cell, loading a non-activation signal on at least one of the first word line and the second word line connected to the memory cell, and loading an on-level signal on all the selection control lines.

[0019] An embodiment of the present disclosure provides an electronic device, comprising the memory described in any of the above embodiments.

[0020] In some embodiments, the electronic device further includes a control circuit, and the control circuit is configured to access the memory according to the memory access method described in any of the above embodiments.

[0021] The disclosed embodiment provides a memory and an access method thereof, and an electronic device, wherein the memory comprises: a multi-layer memory array stacked along a third direction perpendicular to a substrate, the memory array comprising a plurality of memory cells arranged in an array along a first direction parallel to the substrate and along a second direction parallel to the substrate, the memory further comprising a plurality of second word lines corresponding to the rows of the multi-layer memory array, a plurality of first word lines corresponding to the columns of the multi-layer memory array, each of the second word lines corresponding to the same row of the multi-layer memory array, and each of the first word lines corresponding to the same column of the multi-layer memory array; the memory cell comprises a transistor, the transistor comprises a first gate electrode and a second gate electrode, the first gate electrode is connected to the first word line corresponding to the column where the memory cell is located, and the second gate electrode is connected to the second word line corresponding to the row where the memory cell is located. The solution provided by the embodiment can select memory cells at the same position in different layers through the first word line and the second word line, and while reducing the number of word line drivers, it is not necessary to set a gate transistor for word line selection, and it is not necessary to increase the process steps for manufacturing the gate transistor, thereby simplifying the process, reducing the cost, and having simple control logic.

[0022] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings.

[0023] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0025] Figure 1A A schematic diagram of an equivalent circuit of a storage unit provided by a technical solution;

[0026] Figure 1B An equivalent circuit diagram of a memory provided by a technical solution;

[0027] Figure 2 An equivalent circuit diagram of a memory cell provided for an exemplary embodiment;

[0028] Figure 3 An equivalent circuit diagram of a memory provided for an exemplary embodiment;

[0029] Figure 4 An equivalent circuit diagram of a memory is provided for another exemplary embodiment. DETAILED DESCRIPTION

[0030] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0031] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0032] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0033] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0034] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0035] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0036] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0037] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0038] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0039] Figure 1A The equivalent circuit diagram of a storage unit provided by a technical solution is shown in FIG. Figure 1AAs shown, the storage cell may include an access transistor and a capacitor, wherein the gate electrode of the access transistor is connected to the word line WL, the first electrode is connected to the bit line BL, the second electrode is connected to the first end of the capacitor, the second end of the capacitor is connected to the voltage terminal Vcom, and the first end of the capacitor serves as the storage node SN. Figure 1B This is a schematic diagram of a 1T1C memory. Figure 1B As shown, the memory includes a multi-layer memory array (memory array L1 to Lk), each layer of the memory array includes a plurality of memory cells (memory cells not shown) distributed in an array along a first direction X and a second direction Y, and each memory cell is connected to a word line WL and a bit line BL. The bit line BL extends in a direction parallel to the substrate, and the word line WL extends in a direction perpendicular to the substrate and is distributed in an array. In one scheme, the word lines WL of the same row distributed along the first direction X can be connected together. In this scheme, the number of SAs required is very large, n*k, where n is the number of columns of the memory array and k is the number of layers of the stacked memory array. As the number of stacked layers increases, the number of SAs increases sharply. In another scheme, a gating array composed of gating transistors can be set around the memory array, and the word lines are gated by the gating array to reduce the word line drivers. In this scheme, although the number of word line drivers is reduced, multiple gating transistors are added additionally, and additional process steps need to be added for the multiple gating transistors, which increases the cost.

[0040] In the disclosed embodiment, a dual-gate transistor is used in the memory cell, and the two gate electrodes of the transistor are respectively connected to different word lines, the first gate electrodes of the memory cells in the same column of different layers are connected to the same first word line, and the second gate electrodes of the memory cells in the same row of different layers are connected to the same second word line. The memory cells in the same position of different layers are selected by the first word line and the second word line, thereby achieving the purpose of selecting a group of memory cells and reducing the number of word line drivers without the need for selecting transistors.

[0041] Figure 2 FIG. 1 is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment. Figure 2As shown, the memory cell provided in this embodiment includes a transistor (also called an access transistor) and a capacitor Cs, the transistor includes a first gate electrode G1, a second gate electrode G2, a first electrode E1 and a second electrode E2, the first gate electrode G1 is connected to the first word line WL1, the second gate electrode G2 is connected to the second word line WL2, the first electrode E1 is connected to the bit line BL, the second electrode E2 is connected to the first end of the capacitor Cs, the second end of the capacitor Cs is connected to the preset voltage end Vs, and the first end of the capacitor Cs is used as a storage node SN. The first word line WL1 and the second word line WL2 are connected to different signal ends, that is, the first word line WL1 and the second word line WL2 are independently controlled. The memory cell can be applied to a 3D stacked 1T1C memory, so that the gating of a vertical column of memory cells (including memory cells at the same position in each layer) can be realized by the first word line WL1 and the second word line WL2 without the need for a gating transistor. Compared with a single-gate 1T1C memory cell, the solution provided in this embodiment provides support for realizing a 3D stacked 1T1C memory with a simpler process and lower cost.

[0042] In some embodiments, the transistor may be an N-type transistor or a P-type transistor.

[0043] In some embodiments, when both the first word line WL1 and the second word line WL2 are loaded with an activation signal, the transistor is turned on; when at least one of the first word line WL1 and the second word line WL2 is loaded with an inactivation signal, the transistor is turned off. The activation signal and the inactivation signal are different according to the type of transistor. When the transistor is an N-type transistor, when both the first word line WL1 and the second word line WL2 are loaded with a high-level signal, the transistor is turned on, and when at least one of the first word line WL1 and the second word line WL2 is loaded with a low-level signal, the transistor is turned off; or when the transistor is a P-type transistor, when both the first word line WL1 and the second word line WL2 are loaded with a low-level signal, the transistor is turned on, and when at least one of the first word line WL1 and the second word line WL2 is loaded with a high-level signal, the transistor is turned off.

[0044] Figure 3 FIG. 1 is a schematic diagram of a memory equivalent circuit provided by an exemplary embodiment. Figure 3As shown, the memory may include: a multi-layer stacked memory array (k layers), and the multi-layer memory array is stacked along a third direction z. The memory may also include: a plurality of first sub-word lines Sub_WL1 extending along the third direction z, and a plurality of second sub-word lines Sub_WL2 extending along the third direction z. The plurality of first sub-word lines Sub_WL1 are arrayed along the first direction x and the second direction y. The plurality of second sub-word lines Sub_WL2 are arrayed along the first direction x and the second direction y. Each layer of the memory array may include a plurality of memory cells 100 arrayed along the first direction x and the second direction y, respectively, and a plurality of bit lines BL extending along the second direction y. The plurality of bit lines BL of each layer are spaced apart along the first direction x. The structure of the memory cell 100 is referred to as Figure 2 , no more details.

[0045] Each layer of the memory array includes n rows and m columns of memory cells 100, and m bit lines BL, wherein the bit line BL in the jth column of the rth layer is BL_j_r, wherein j is 1 to m, and r is 1 to k.

[0046] The memory includes n rows and m columns of first sub-word lines Sub_WL1, the first sub-word line of the i-th row and j-th column is Sub_WL1_i_j, i is 1 to n, and j is 1 to m. The memory includes n rows and m columns of second sub-word lines Sub_WL2, the second sub-word line of the i-th row and j-th column is Sub_WL2_i_j, i is 1 to n, and j is 1 to m. Among them, the first gate electrode G1 of the memory cell C_i_j_r of the i-th row and j-th column of the r-th layer is connected to the first sub-word line Sub_WL1_i_j, the second gate electrode G2 is connected to the second sub-word line Sub_WL2_i_j, and the first electrode E1 is connected to the bit line BL_j_r.

[0047] The first direction x and the second direction y are parallel to the substrate ( Figure 3 The substrate is not shown in the figure), and the third direction z is perpendicular to the substrate. The first direction x and the second direction y may intersect. In some embodiments, the first direction x and the second direction y may be perpendicular. The first direction x is also called the row direction, and the second direction y is also called the column direction. The preset voltage terminal Vs may be, for example, a ground terminal.

[0048] In some embodiments, a plurality of first sub-word lines Sub_WL1 in the same column (i.e., a plurality of first sub-word lines Sub_WL1 distributed along the second direction Y) are connected to form a first word line WL1, and memory cells in the same column at different layers correspond to a first word line WL1, that is, n first sub-word lines Sub_WL1_1_j to Sub_WL1_n_j in the j-th column are connected to form the j-th first word line WL1_j, where j is 1 to m. For example, n first sub-word lines Sub_WL1_1_1 to Sub_WL1_n_1 in the 1st column are connected to form the 1st first word line WL1_1, and n first sub-word lines Sub_WL1_1_m to Sub_WL1_n_m in the m-th column are connected to form the m-th first word line WL1_m. Each first word line WL1_j is connected to a first word line driver. Different first word lines WL1_j are connected to different first word line drivers. The plurality of first word line drivers connected to the plurality of first word lines WL1_j may be disposed on the same side of the memory array, but the embodiments of the present disclosure are not limited thereto, and the plurality of first word line drivers may be disposed on different sides of the memory array.

[0049] In some embodiments, multiple first sub-word lines Sub_WL1 in the same column may be connected by a connection line disposed on a side of the memory array away from the substrate and extending along the second direction Y. However, the disclosed embodiments are not limited thereto, and multiple first sub-word lines Sub_WL1 in the same column may be connected by other methods.

[0050] In some embodiments, multiple second sub-word lines Sub_WL2 in the same row are connected to form a second word line WL2, and the memory cells in the same row of different layers correspond to a second word line WL2, that is, the m second sub-word lines Sub_WL2_i_1 to Sub_WL2_i_m in the i-th row are connected to form the i-th second word line WL2_i, where i is 1 to n. The m second sub-word lines Sub_WL2_1_1 to Sub_WL2_1_m in the 1st row are connected to form the 1st second word line WL2_1, and the m second sub-word lines Sub_WL2_n_1 to Sub_WL2_n_m in the n-th row are connected to form the n-th second word line WL2_n. Each second word line WL2_i is connected to a second word line driver. The multiple second word line drivers connected to the multiple second word lines WL2_i can be set on the same side of the memory array, but the embodiments of the present disclosure are not limited thereto, and the multiple second word line drivers can be set on different sides of the memory array.

[0051] In some embodiments, multiple second sub-word lines Sub_WL2 in the same row may be connected by a connection line disposed on a side of the memory array away from the substrate and extending along the first direction X. However, the disclosed embodiment is not limited thereto, and multiple second sub-word lines Sub_WL2 in the same row may be connected by other methods.

[0052] The memory provided in this embodiment can select a vertical column of storage cells by activating a first word line and a second word line. For example, when the target row is the pth row and the target column is the qth column, an activation signal can be loaded on the second word line WL2_p and the first word line WL1_q, thereby selecting k storage cells in the pth row and the qth column of the 1st to the kth layers. The solution provided in this embodiment can select a vertical column of storage cells without setting a gate transistor for the word line. Compared with the solution of setting a gate transistor for the word line, there is no need to add process steps for the manufacture of the gate transistor, and the number of word line drivers is small, the number of first word line drivers is m, the number of second word line drivers is n, and the number of word line drivers remains unchanged as the number of stacked layers increases. In addition, the circuit control logic is simple.

[0053] In some embodiments, the memory may further include a plurality of common bit lines CBL, a plurality of bit lines BL of the same layer may be connected to the same common bit line CBL, and bit lines BL of different layers may be connected to different common bit lines CBL, for example, a plurality of bit lines BL of the first layer may be connected to a first common bit line CBL1, a plurality of bit lines BL of the second layer may be connected to a second common bit line CBL2, and a plurality of bit lines BL of the kth layer may be connected to a kth common bit line CBLk. A common bit line CBL is connected to a sense amplifier SA. Compared with a scheme in which each bit line BL is connected to a sense amplifier SA, the scheme provided in this embodiment can greatly reduce the number of sense amplifiers SA by using a common bit line CBL. Adjacent storage arrays may share the same SA. However, the disclosed embodiments are not limited thereto, and each bit line BL may be connected to a sense amplifier SA.

[0054] In some embodiments, each bit line BL can be connected to the common bit line CBL through a gating sub-circuit 10. The gating sub-circuit 10 can also be connected to a gating control line, and the gating sub-circuit 10 is configured to connect or disconnect the bit line BL and the common bit line CBL under the control of the gating control line (that is, the bit line BL and the common bit line CBL are electrically connected, or disconnected). That is, the signal of the common bit line CBL is loaded or not loaded on the bit line BL under the control of the gating control line. The scheme provided in this embodiment sets a gating sub-circuit, which can reduce the capacitance of CBL, reduce power consumption, and improve the reading speed. However, the embodiments of the present disclosure are not limited to this. In another exemplary embodiment, the gating sub-circuit 10 may not be set.

[0055] In some embodiments, the gating sub-circuits 10 connected to the bit lines BL in the same column of different layers can be connected to the same gating control line, the gating sub-circuits connected to the bit lines BL in different columns of different layers are connected to different gating control lines, and the bit lines BL in m columns are respectively connected to m different gating control lines. Figure 3As shown, the gating sub-circuits 10 connected to the bit lines BL of the first column are all connected to the first gating control line S_1, the gating sub-circuits 10 connected to the bit lines BL of the second column are all connected to the second gating control line S_2, and so on, the gating sub-circuits 10 connected to the bit lines BL of the mth column are all connected to the mth gating control line S_m. Thus, a bit line BL can be selected through the common bit line CBL and the gating control line. For example, the rth common bit line CBLr is loaded with an activation signal (the other common bit lines are loaded with an inactive signal), the jth gating control line S_j selects the corresponding gating sub-circuit 10 (the other gating control lines do not select the corresponding gating sub-circuit 10), then the bit line BL_j_r of the rth layer and the jth column is loaded with an activation signal. Alternatively, the bit lines BL of the same column of different layers can be selected through the gating control line.

[0056] In some embodiments, only bit lines BL of the same column in different layers may be enabled at the same time, so as to reduce the capacitance load of SA and the capacitance of the memory cell.

[0057] In some embodiments, the gating subcircuit 10 may include a first transistor T1, the first transistor T1 may include a gate electrode, a first electrode, and a second electrode, the gate electrode of the first transistor T1 is connected to the gating control line, the first electrode is connected to the bit line BL, and the second electrode is connected to the common bit line CBL. The structure of the gating subcircuit 10 described in this embodiment is only an example, and may be other circuits that can implement gating.

[0058] In another embodiment, if Figure 4 As shown, the first transistor T1 may be a dual-gate transistor, that is, the first transistor T1 may include a first gate electrode, a second gate electrode, a first electrode, and a second electrode, the first gate electrode and the second gate electrode of the first transistor T1 are connected to the selection control line, the first electrode of the first transistor T1 is connected to the bit line BL, and the second electrode is connected to the common bit line CBL. In the solution provided by this embodiment, the first transistor T1 and the access transistor can be completed through a single manufacturing process, that is, the first transistor T1 is manufactured at the same time as the access transistor is manufactured, thereby simplifying the process and reducing costs.

[0059] In some embodiments, the first transistor T1 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto, and the first transistor T1 may be a P-type transistor.

[0060] In some embodiments, when the first word line WL1_j corresponding to the storage unit in the jth column of a different layer is loaded with an activation signal, the gating control line S_j connected to the gating subcircuit 10 connected to the bit line BL of the jth column is loaded with an on-level signal to connect the gating subcircuit 10 connected to the bit line BL of the jth column. When the second word line WL2_i corresponding to the i-th row is loaded with an activation signal, at this time, the storage unit in the i-th row and j-th column of a different layer is gated, and the storage unit in the i-th row and j-th column can be accessed (read or written) through the bit line BL of the j-th column.

[0061] In some embodiments, the first word line WL1_j can be connected to the gating control line S_j connected to the gating sub-circuit 10 connected to the bit line BL of the jth column, where j is 1 to m, that is, the same signal driver can be used to load the same signal to the first word line WL1_j and the gating control line S_j, that is, the activation signal and the start-up level signal of the gating sub-circuit use the same signal. The solution provided in this embodiment can reduce the number of control lines, reduce the control circuit that generates the control signal, reduce the device occupied area, and simplify the control logic.

[0062] An embodiment of the present disclosure provides a method for accessing a memory, which is applied to the memory described in any of the above embodiments. The access method may include:

[0063] During the data reading and writing stage, according to the target row and target column where the storage unit to be operated is located, an activation signal is loaded on the second word line corresponding to the target row, and a non-activation signal is loaded on the corresponding second word line not of the target row; an activation signal is loaded on the corresponding first word line of the target column, and a non-activation signal is loaded on the corresponding first word line not of the target column (at this time, only the first gate electrode and the second gate electrode of the transistor of the storage unit of the target row and target column of each layer are loaded with the activation signal, so that the transistor of the storage unit of the target row and target column of each layer can be turned on).

[0064] In some embodiments, the access method may further include: loading an on-level signal on a gating control line connected to the bit line of the target column (so that the gating subcircuit connected to the bit line of the target column is in a connected state), and loading an off-level signal on a gating control line connected to the bit line of a non-target column (so that the gating subcircuit connected to the bit line of the non-target column is in an off state).

[0065] This embodiment provides a method for accessing a memory, which can access a vertical column of memory cells through a first word line, a second word line and a gate control line, and the control logic is simple.

[0066] The on-level signal is a signal that can put the corresponding gating subcircuit in a connected state, and the off-level signal is a signal that can put the corresponding gating subcircuit in a turned-off state.

[0067] In some embodiments, it may also include:

[0068] In the precharge stage, an inactive signal is loaded on all second word lines, an active signal or an inactive signal is loaded on all first word lines, and an on-level signal is loaded on all the gating control lines. The solution provided in this embodiment can turn off all access transistors, turn on all gating sub-circuits, and precharge the bit lines.

[0069] In some embodiments, the activation signal loaded on the first word line corresponding to the target column and the turn-on level signal loaded on the enable control line connected to the bit line of the target column are the same signal, and the inactivation signal loaded on the first word line corresponding to the non-target column and the turn-off level signal loaded on the enable control line connected to the bit line of the non-target column are the same signal.

[0070] That is, the same signal can be used to control the gating control line connected to the bit line of the target column, and the first word line corresponding to the target column, which reduces the control signal, makes the control simpler, and reduces the signal driver, which is conducive to reducing costs and reducing device area. At this time, the gating control line S_j connected to the gating subcircuit 10 connected to the first word line WL1_j and the bit line BL of the j-th column can be connected together, where j is 1 to m, and m is the number of columns of storage cells contained in each layer of the storage array.

[0071] The following describes the working process of the memory by using an embodiment. Figure 2 Taking the memory shown as an example, in this embodiment, the memory cell 100 is a 1T1C structure, the access transistor is an N-type MOS tube, the first transistor T1 is an N-type MOS tube, the selection control line S_j is connected to the first word line WL1_j, j is 1 to m, and the common bit line CBL can also be connected to the pre-charging sub-circuit. The working phase of the memory may include a pre-charging phase, a data reading phase, and a data write-back phase, wherein:

[0072] In the pre-charging stage, the second word lines WL2_1 to WL2_n are all loaded with low-level signals, which are loaded onto the second sub-word line Sub_WL2, and the first word lines WL1_1 to WL1_m are all loaded with high-level signals (i.e., the selection control line S_j is loaded with a high-level signal). At this time, the selection sub-circuit is turned on, the access transistors of all storage cells are turned off, the pre-charging sub-circuit is turned on, and a pre-charging voltage of 1 / 2VDD is loaded onto each common bit line CBL. Each common bit line CBL loads the pre-charging voltage onto the bit line BL of the same layer connected thereto.

[0073] In the data reading stage, the precharge sub-circuit is turned off; taking the data of the storage cell 100 of the p-th row and the q-th column as an example, among the first word lines WL1_1 to WL1_m, the first word line WL1_q corresponding to the q-th column is loaded with a high level signal, and the other first word lines WL1_j (where j is 1 to m and j≠q) are loaded with a low level signal, and among the second word lines WL2_1 to WL2_n, the second word line WL2_p corresponding to the p-th row is loaded with a high level signal, and the other WL2_i (where i is 1 to n and i≠p) are loaded with a low level signal, so that the p-th row is loaded with a high level signal. The access transistor of the memory cell 100 in the row and the qth column is turned on, and the access transistors of the other memory cells 100 are turned off, the selection subcircuit 10 connected to the bit line in the qth column is turned on, and the common bit lines CBL1 to CBLk are respectively connected to the k bit lines in the qth column, and charge is shared with the storage nodes of the k memory cells 100 in the pth row and the qth column in the 1st to the kth layers, respectively, and the sense amplifiers respectively connected to CBL1 to CBLk sense the voltages of CBL1 to CBLk to determine the data stored in the memory cell 100 in the pth row and the qth column.

[0074] In the data write back stage, among the first word lines WL1_1 to WL1_m, WL1_q is loaded with a high level signal, and the remaining WL1_j (where j is 1 to m and j≠q) are loaded with a low level signal, and among the second word lines WL2_1 to WL2_n, WL2_p is loaded with a high level signal, and the remaining WL2_i (where i is 1 to n and i≠p) are loaded with a low level signal, and the common bit lines CBL1 to CBLk are respectively connected to the k bit lines in the qth column, and charge is shared with the storage nodes of the k storage cells 100 in the pth row and the qth column of the 1st to kth layers, respectively, to realize data write back.

[0075] The solution provided in this embodiment does not need to use a selection transistor to select the storage unit. The first word line and the second word line can be used to select the storage unit in a vertical column. The structure is simple, the control logic is simple, and the same control signal is used to control the selection control line and the second word line in the same column, which reduces the number of control signal lines, reduces the required control circuit, and makes the control logic simpler.

[0076] The present disclosure also provides an electronic device, including the memory of the above-mentioned embodiment. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0077] In some embodiments, the electronic device may further include a control circuit, the control circuit being configured to access the memory according to any of the access methods described above. The control circuit may include a driver that generates a control signal to the first word line, the second word line, a gate control line, etc. The control circuit and the SA together implement access to the memory.

[0078] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A memory, characterized in that: include: A multi-layer memory array stacked along a third direction perpendicular to a substrate, the memory array comprising a plurality of memory cells distributed in an array along a first direction parallel to the substrate and along a second direction parallel to the substrate, the memory further comprising a plurality of second word lines corresponding to rows of the multi-layer memory array, a plurality of first word lines corresponding to columns of the multi-layer memory array, each of the second word lines corresponding to the same row of the multi-layer memory array, and each of the first word lines corresponding to the same column of the multi-layer memory array; The memory cell includes a transistor, and the transistor includes a first gate electrode and a second gate electrode, the first gate electrode is connected to the first word line corresponding to the column where the memory cell is located, and the second gate electrode is connected to the second word line corresponding to the row where the memory cell is located.

2. The memory according to claim 1, characterized in that: Each layer of the storage array further includes a plurality of first sub-word lines extending along the third direction, first gate electrodes of storage cells in the same row and column of different layers are connected to one of the first sub-word lines, first gate electrodes of different storage cells in the same layer are connected to different first sub-word lines, and a plurality of the first sub-word lines in the same column are connected to form one first word line.

3. The memory according to claim 1, characterized in that: Each layer of the storage array also includes a plurality of second sub-word lines extending along the third direction, the second gate electrodes of storage cells in the same row and column of different layers are connected to one second sub-word line, the second gate electrodes of different storage cells in the same layer are connected to different second sub-word lines, and a plurality of second sub-word lines in the same row are connected to form one second word line.

4. The memory according to claim 2, characterized in that: Each layer of the storage array also includes: a plurality of bit lines extending along the second direction; the memory also includes: a plurality of common bit lines; a bit line connects the storage units in the same column of the layer where the bit line is located, the bit lines in the same layer are connected to the same common bit line, and the bit lines in different layers are connected to different common bit lines.

5. The memory according to claim 4, characterized in that: Each of the bit lines is connected to the common bit line via a gating subcircuit, and the gating subcircuit is also connected to a gating control line. Multiple gating subcircuits respectively connected to multiple bit lines in the same column of different layers are connected to the same gating control line, and the gating subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the gating control line.

6. The memory according to claim 5, characterized in that: The gating subcircuit includes a first transistor, which includes a first gate electrode, a second gate electrode, a first electrode and a second electrode. The first gate electrode and the second gate electrode of the first transistor are connected to the gating control line, the first electrode of the first transistor is connected to the bit line, and the second electrode of the first transistor is connected to the common bit line.

7. The memory according to claim 5, characterized in that: The gating control line connected to the plurality of gating subcircuits respectively connected to the plurality of bit lines in the j-th column is connected to the first word line corresponding to the memory cell in the j-th column.

8. A method for accessing a memory according to any one of claims 1 to 7, characterized in that: include: In the data reading and writing phase, according to the target row and target column where the storage unit to be operated is located, an activation signal is loaded on the second word line corresponding to the target row, and an inactivation signal is loaded on the second word line corresponding to the non-target row; An activation signal is loaded on the first word line corresponding to the target column, and a deactivation signal is loaded on the first word line corresponding to a non-target column.

9. The memory access method according to claim 8, characterized in that: The memory is a memory as described in any one of claims 5 to 7, and the method also includes, in the data reading and writing stage, loading an on-level signal on a selection control line connected to the bit line of the target column, and loading an off-level signal on a selection control line connected to the bit line of a non-target column.

10. The memory access method according to claim 9, characterized in that: The activation signal loaded on the first word line corresponding to the target column and the turn-on level signal loaded on the selection control line connected to the bit line of the target column are the same signal, and the inactivation signal loaded on the first word line corresponding to the non-target column and the turn-off level signal loaded on the selection control line connected to the bit line of the non-target column are the same signal.

11. The memory access method according to claim 9, characterized in that: The method further includes, in the precharge phase, for each memory cell, loading an inactive signal on at least one of the first word line and the second word line connected to the memory cell, and loading an on-level signal on all the selection control lines.

12. An electronic device, characterized in that: Comprising the memory as claimed in any one of claims 1 to 7.

13. The electronic device according to claim 12, characterized in that: The electronic device further comprises a control circuit, wherein the control circuit is configured to access the memory according to the memory access method according to any one of claims 8 to 11.

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