Semiconductor structure and method of manufacturing the same, memory, storage system

Abstract

The application provides a semiconductor structure, a manufacturing method thereof, a memory and a storage system. The semiconductor structure comprises a semiconductor layer, and the semiconductor layer comprises a plurality of semiconductor columns which extend along a second direction and are arrayed along a first direction and a third direction, wherein the first direction, the second direction and the third direction intersect with each other. The manufacturing method of the semiconductor structure comprises the following steps: forming a first gate structure which extends along the third direction on the sidewall of the semiconductor column; forming a second gate structure which extends along the first direction on the sidewall of the semiconductor column, wherein the second gate structure and the first gate structure are arranged at intervals along the second direction; and forming a bit line which is connected with the semiconductor column and extends along the first direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures and methods for manufacturing semiconductor structures, memories, and storage systems. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the requirements for storage density of semiconductor structures, such as three-dimensional semiconductor storage devices, are becoming increasingly stringent. However, as the storage density of semiconductor structures increases, the number of storage cells increases, their size decreases, and their spatial density increases. This leads to an increase in capacitance between adjacent components (such as adjacent bit lines), which has a significant impact on the performance of semiconductor structures. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies mentioned in the background section above or other deficiencies in the prior art.

[0004] This application provides a method for manufacturing a semiconductor structure. The semiconductor layer includes a plurality of semiconductor pillars extending along a second direction and arrayed along a first direction and a third direction, wherein the first direction, the second direction, and the third direction intersect each other. The method includes: forming a first gate structure extending along the third direction on the sidewalls of the semiconductor pillars; forming a second gate structure extending along the first direction on the sidewalls of the semiconductor pillars, wherein the second gate structure and the first gate structure are spaced apart along the second direction; and forming a bit line connected to the semiconductor pillars and extending along the first direction.

[0005] In one embodiment, the bit line is adjacent to the first gate structure along the second direction, and the method includes: forming a first gate lead-out structure and a bit line lead-out structure respectively connected to the first gate structure and the bit line from a first side of the semiconductor layer; and forming a second gate lead-out structure connected to the second gate structure from a second side of the semiconductor layer opposite to the first side.

[0006] In one embodiment, forming a first gate structure extending along a third direction on the sidewall of the semiconductor pillar includes: forming a plurality of initial semiconductor pillars extending along the first direction and the second direction within the semiconductor layer; forming a plurality of first trenches passing through the initial semiconductor pillars and extending along a third direction and arranged along the first direction, wherein the plurality of first trenches divide the initial semiconductor pillars into a plurality of semiconductor pillars extending along the second direction; and forming the first gate structure and an isolation layer extending along the third direction and adjacently distributed along the second direction in the first trenches.

[0007] In one embodiment, the method further includes: forming a second trench through the semiconductor pillar and extending in a third direction; and forming an isolation structure in the second trench.

[0008] In one embodiment, forming a first gate structure and an isolation layer extending along the third direction and adjacently distributed along the second direction in the first trench includes: forming a first gate dielectric layer extending along the third direction in the first trench; forming a first gate layer on the surface of the first gate dielectric layer, wherein the first gate layer and the first gate dielectric layer are adjacently distributed along the first direction, the first gate structure includes the first gate layer and the first gate dielectric layer; and forming the isolation layer on the surface of the first gate structure.

[0009] In one embodiment, forming a plurality of initial semiconductor pillars extending along the first direction and the second direction within the semiconductor layer includes: forming a plurality of isolation pillars extending along the first direction and the second direction within the semiconductor layer, wherein the plurality of isolation pillars divide a portion of the semiconductor layer into a plurality of initial semiconductor pillars, and the initial semiconductor pillars and the isolation pillars are alternately arranged along the third direction.

[0010] In one embodiment, forming a second gate structure extending along the first direction on the sidewall of the semiconductor pillar includes: forming the second gate structure extending along the first direction on at least one of a first sidewall and a second sidewall of the semiconductor pillar that are opposite each other along the third direction.

[0011] In one embodiment, the method includes: forming a third trench that passes through the isolation layer and the isolation pillar and extends along the first direction; and forming the second gate structure via the third trench.

[0012] In one embodiment, the second gate structure includes a first sub-gate structure and a second sub-gate structure. The second gate structure extending along the first direction is formed on the sidewall of the semiconductor pillar, including: forming the first sub-gate structure extending along the first direction on at least one of the first sidewall and the second sidewall of the semiconductor pillar that are opposite each other along the third direction; and forming the second sub-gate structure on at least one of the third sidewall and the fourth sidewall of the semiconductor pillar that are opposite each other along the first direction.

[0013] In one embodiment, the method includes: forming a third trench extending through the isolation layer and the isolation pillar and along the first direction, and a fourth trench extending through the isolation layer and along the third direction; forming a first sub-gate structure and a second sub-gate structure via the third trench and the fourth trench, respectively.

[0014] In one embodiment, the bit line is connected to a first end of the semiconductor pillar, and the method further includes: forming a capacitor connected to a second end of the semiconductor pillar, the second end being located on a side of the semiconductor pillar away from the first end.

[0015] This application also provides a semiconductor structure. The semiconductor structure includes: a plurality of semiconductor pillars extending along a second direction and arrayed along a first direction and a third direction, wherein the first direction, the second direction, and the third direction intersect each other; a first gate structure located on a sidewall of the semiconductor pillars and extending along the third direction; a second gate structure located on a sidewall of the semiconductor pillars and extending along the first direction, wherein the second gate structure and the first gate structure are spaced apart along the second direction; and a bit line connected to the semiconductor pillars and extending along the first direction.

[0016] In one embodiment, the second gate structure is located on at least one of the first and second sidewalls of the semiconductor pillar that are oriented in the third direction opposite to each other.

[0017] In one embodiment, the second gate structure includes: a first sub-gate structure located on at least one of a first sidewall and a second sidewall opposite to each other along the third direction of the semiconductor pillar; and a second sub-gate structure located on at least one of a third sidewall and a fourth sidewall opposite to each other along the first direction of the semiconductor pillar.

[0018] In one embodiment, the first gate structure is located on at least one of the third and fourth sidewalls of the semiconductor pillar that are opposite each other along the first direction.

[0019] In one embodiment, the semiconductor structure further includes an isolation structure located between two adjacent semiconductor pillars arranged along the first direction.

[0020] In one embodiment, the first gate structure includes a first gate dielectric layer located on the sidewall of the semiconductor pillar and a first gate layer located outside the first gate dielectric layer; and the second gate structure includes a second gate dielectric layer located on the sidewall of the semiconductor pillar and a second gate layer located outside the second gate dielectric layer.

[0021] In one embodiment, the isolation structure includes a conductive layer and / or an air gap layer.

[0022] In one embodiment, the bit line is connected to a first end of the semiconductor pillar, and the semiconductor structure further includes a capacitor connected to a second end of the semiconductor pillar, the second end being located on the side of the semiconductor pillar away from the first end.

[0023] In one embodiment, the semiconductor structure includes a plurality of first gate structures and a plurality of second gate structures, wherein, in response to turning on a preset first gate structure among the plurality of first gate structures and a preset second gate structure among the plurality of second gate structures to address a preset semiconductor pillar among the plurality of semiconductor pillars and a preset bit line connected to the preset semiconductor pillar, the preset bit line is in a sensing state and the bit line adjacent to the preset bit line is in a non-sensing state.

[0024] In another aspect, this application provides a memory comprising: a memory cell array including a semiconductor structure as described above; and peripheral circuitry coupled to the memory cell array.

[0025] Another aspect of this application provides a storage system including at least one memory; and a controller coupled to a semiconductor structure for controlling the memory to store data.

[0026] In one or more embodiments of this application, by forming a first gate structure and a second gate structure on the sidewall of the semiconductor pillar, the semiconductor pillar can be connected to two gate structures (i.e., the first gate structure and the second gate structure), which is beneficial to realize the control of the semiconductor pillar through at least two gate structures. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0028] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of this application;

[0029] Figure 2 and Figure 3 These are schematic diagrams of partial structures of a semiconductor layer on a plane formed in a first direction and a third direction, and on a plane formed in a third direction and a second direction, respectively, according to exemplary embodiments of this application.

[0030] Figure 4 and Figure 5 These are schematic diagrams illustrating the formation of the initial semiconductor pillar and the isolation pillar according to exemplary embodiments of this application, wherein... Figure 5for Figure 4 A partial cross-sectional diagram along the AA direction;

[0031] Figure 6 and Figure 7 These are schematic diagrams of the structure of the portion of the first groove formed on the planes formed in the first and second directions, and on the planes formed in the third and first directions, according to exemplary embodiments of this application. Figure 7 for Figure 6 A partial cross-sectional diagram along the BB direction;

[0032] Figure 8 and Figure 9 These are schematic diagrams of the structures forming the first dielectric layer and the third dielectric layer according to exemplary embodiments of this application, wherein, Figure 9 for Figure 8 A partial cross-sectional diagram along the BB direction;

[0033] Figure 10 and Figure 11 This is a schematic diagram of the structure forming a first gate dielectric layer and a first gate layer according to an exemplary embodiment of this application, wherein, Figure 11 for Figure 10 A partial cross-sectional diagram along the BB direction;

[0034] Figure 12 and Figure 13 This is a schematic diagram of the structure forming a second dielectric layer, an isolation layer, and a via according to an exemplary embodiment of this application, wherein, Figure 13 for Figure 12 A partial cross-sectional diagram along the BB direction;

[0035] Figure 14 This is a partial structural schematic diagram of a first gate structure provided according to an exemplary embodiment of this application;

[0036] Figure 15 and Figure 16 This is a schematic diagram of a structure forming an isolation structure and a barrier layer according to an exemplary embodiment of this application, wherein, Figure 16 for Figure 15 A partial cross-sectional diagram along the BB direction;

[0037] Figure 17 for Figure 15 A partial cross-sectional diagram along the CC direction;

[0038] Figure 18 for Figure 17 A partial cross-sectional diagram along the DD direction;

[0039] Figure 19 and Figure 20These are schematic diagrams of the structure forming the third trench according to exemplary embodiments of this application, wherein, Figure 20 for Figure 19 A partial cross-sectional diagram along the DD direction;

[0040] Figure 21 and Figure 22 These are schematic diagrams of the formation of the second gate structure according to an exemplary embodiment of this application, wherein, Figure 22 for Figure 21 A partial cross-sectional diagram along the DD direction;

[0041] Figure 23 and Figure 24 These are schematic diagrams of the formation of the third and fourth trenches according to another exemplary embodiment of this application, wherein, Figure 24 for Figure 23 A partial cross-sectional diagram along the DD direction;

[0042] Figures 25 to 27 These are schematic diagrams of the formation of the second gate structure according to another exemplary embodiment of this application, wherein, Figure 26 for Figure 25 A partial cross-sectional diagram along the DD direction. Figure 27 for Figure 25 A partial cross-sectional diagram along the EE direction;

[0043] Figure 28 This is a schematic diagram of a capacitor structure provided according to an exemplary embodiment of this application;

[0044] Figure 29 To be Figure 28 A schematic diagram of a structure that has been thinned after being flipped 180°.

[0045] Figures 30 to 32 This is a partial structural schematic diagram of the semiconductor structure after bit line formation according to an exemplary embodiment of this application on the plane formed by the first direction X and the second direction Z, the plane formed by the first direction X and the third direction Y, and the plane formed by the third direction Y and the second direction Z.

[0046] Figure 33 This is a schematic block diagram of a memory according to an exemplary embodiment of this application;

[0047] Figure 34 This is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of this application; and

[0048] Figure 35A and Figure 35B This is a schematic diagram of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0049] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0050] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first gate structure discussed herein may also be referred to as the second gate structure, and the first direction may also be referred to as the second direction, the third direction, and vice versa.

[0051] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0052] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0053] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0054] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0055] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0056] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer can be a region of a homogeneous or non-homogeneous continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at or between any set of horizontal planes on or between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer can include multiple layers.

[0057] Furthermore, in this application, the use of "connection" or "linkage" may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0058] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0059] Figure 1 This is a flowchart of a method 1000 for manufacturing a semiconductor structure according to an exemplary embodiment of this application.

[0060] The semiconductor layer may include a plurality of semiconductor pillars extending along a second direction and arrayed along a first direction and a third direction, wherein the first direction, the second direction, and the third direction intersect each other. Figure 1As shown, a method 1000 for manufacturing a semiconductor structure may include: S1100, forming a first gate structure extending along a third direction on the sidewall of a semiconductor pillar; S1200, forming a second gate structure extending along a first direction on the sidewall of the semiconductor pillar, wherein the second gate structure and the first gate structure are spaced apart along a second direction; and S1300, forming a bit line connected to the semiconductor pillar and extending along the first direction. Steps S1100 to S1300 will be described in detail below.

[0061] In the exemplary embodiments of this application, such as Figure 6 and Figure 7 As shown, the semiconductor layer 1100 may include a plurality of semiconductor pillars 1110 extending along the second direction Z and distributed in an array along the first direction X and the third direction Y. The first direction X, the second direction Z, and the third direction Y may intersect each other.

[0062] The material of the semiconductor layer 1100 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0063] For example, a plurality of semiconductor pillars 1110 can be formed by removing a portion of semiconductor layer 1100. In other words, the unremoved portion of semiconductor layer 1100 may include a plurality of semiconductor pillars 1110. Therefore, semiconductor pillars 1110 may have the same material as the unremoved portion of semiconductor layer 1100, such as monocrystalline silicon.

[0064] For example, a plurality of semiconductor pillars 1110 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillars 1110. For example, the semiconductor pillars 1110 may have a cubic shape to expose their four sidewalls. It should be understood that the semiconductor pillars 1110 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillars 1110 in a planar view (e.g., in the XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape.

[0065] In the exemplary embodiments of this application, such as Figure 12 and Figure 13 As shown, a first gate structure 1200 extending in the third direction Y can be formed on the sidewall of the semiconductor pillar 1110.

[0066] The first gate structure 1200 may be located on the sidewall of the semiconductor pillar 1110 and may extend in the third direction Y. The first gate structure 1200 may include a first gate dielectric layer 1210 and a first gate layer 1220. The first gate dielectric layer 1210 may be located on the sidewall of the semiconductor pillar 1110. The first gate layer 1220 may be located inside the first gate dielectric layer 1210, such as on the inner surface of the first gate dielectric layer 1210.

[0067] Exemplarily, the first gate structure 1200 may further include a dielectric layer (including a first dielectric layer 1230 and a third dielectric layer 1240) and a second dielectric layer 1250. The dielectric layer may be located at a first end 1111 of the first gate structure 1200 near the semiconductor pillar 1110, wherein the third dielectric layer 1240 may surround a portion of the first dielectric layer 1230, and the first gate layer 1220 and the first gate dielectric layer 1210 may be located on the dielectric layer. The second dielectric layer 1250 may be located on the first dielectric layer 1230 and may be located on the surface of the first gate layer 1220.

[0068] For example, two adjacent first gate structures 1200 may be symmetrically distributed along the second direction Z. The first dielectric layer 1230, second dielectric layer 1250, and third dielectric layer 1240 in the two partially symmetrical first gate structures 1200 are continuous. In other words, the first dielectric layer 1230 in the two partially symmetrical first gate structures 1200 may be connected to form a single structure, the second dielectric layer 1250 in the two first gate structures 1200 may be connected to form a single structure, and the third dielectric layer 1240 in the two first gate structures 1200 may be connected to form a single structure. Figure 14 As shown, a partial structural schematic diagram of a first gate structure 1200 is presented.

[0069] Exemplarily, the semiconductor pillar 1110 and the first gate structure 1200 can be used together to form a vertical transistor, wherein the semiconductor pillar 1110 can be used to form the active region of a plurality of channels in the vertical transistor. Exemplarily, the first gate structure 1200 can be located on at least one sidewall of the semiconductor pillar 1110, i.e., the semiconductor pillar 1110 can be at least partially surrounded by the first gate structure 1200. For example, the semiconductor pillar 1110, the first gate dielectric layer 1210, and the first gate layer 1220 can be arranged radially from the center of the vertical transistor in this order. Exemplarily, the first gate dielectric layer 1210 can surround and contact the semiconductor pillar 1110. The first gate layer 1220 can surround and contact the first gate dielectric layer 1210. The first gate layer 1220 can be a composite layer structure.

[0070] It should be understood that Figure 12 and Figure 13The case shown where the first gate structure 1200 is located on at least two sidewalls of the semiconductor pillar 1110 is merely an example and not a specific limitation. For example, Figure 15 and Figure 16 An example is shown where the first gate structure 1200 is located on one sidewall of the semiconductor pillar 1110.

[0071] In one embodiment of this application, as Figure 12 and Figure 13 As shown, the first gate structure 1200 can be located on multiple sidewalls of the semiconductor pillar 1110. In this case, the semiconductor pillar 1110 and the first gate structure 1200 can be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). Multi-gate transistors can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the off-state, the leakage current of the multi-gate transistor can also be significantly reduced because the channel is completely depleted. Therefore, using a multi-gate transistor can achieve better speed (saturation drain current) / leakage current performance.

[0072] In another embodiment of this application, such as Figure 15 and Figure 16 As shown, the first gate structure 1200 can be located on one sidewall of the semiconductor pillar 1110, where the semiconductor pillar 1110 and the first gate structure 1200 can be used together to form a single-gate transistor. Exemplarily, adjacent single-gate transistors along the first direction X can be arranged symmetrically. By setting single-gate transistors, this application can significantly increase the density of semiconductor pillars 1110 in the first direction X, reducing manufacturing process difficulty. Furthermore, symmetrically distributed single-gate transistors can have a larger process window, which is beneficial for reducing subsequent bit lines, word lines, and the spacing between transistors.

[0073] like Figures 2 to 13 The diagram illustrates the process steps for forming a first gate structure 1200 extending in a third direction (Y) on the sidewall of a semiconductor pillar 1110, as provided in this application. It should be understood that the process for forming the first gate structure 1200 provided in this application is merely an example and not a specific limitation. In actual processes, the process for forming the first gate structure 1200 can be reasonably configured according to actual needs.

[0074] like Figures 2 to 13 As shown, a first gate structure 1200 extending in a third direction Y is formed on the sidewall of the semiconductor pillar 1110, which may include: a plurality of initial semiconductor pillars 1130 extending in a first direction X and a second direction Z may be formed within the semiconductor layer 1100. Figure 4 and Figure 5); forming a plurality of first trenches passing through the initial semiconductor pillar 1110 and extending along a third direction Y and arranged along a first direction X, wherein the plurality of first trenches divide the initial semiconductor pillar 1110 into a plurality of semiconductor pillars 1110 extending along a second direction Z. Figure 6 and Figure 7 ); and a first gate structure 1200 and an isolation layer 1300 extending in the third direction Y and adjacently distributed in the second direction Z are formed on the sidewall of the semiconductor pillar 1110 via the first trench. Figure 12 and Figure 13 ).

[0075] Figure 2 and Figure 3 These are partial structural schematic diagrams of the semiconductor layer 1100 provided according to exemplary embodiments of this application, on a plane formed by a first direction X and a third direction Y, and on a plane formed by a third direction Y and a second direction Z. For example, as shown... Figure 3 As shown, a first dielectric layer 1141 and a second dielectric layer 1142 may be formed on the surface of the semiconductor layer 1100 in sequence. Exemplarily, a patterned mask may be formed subsequently by etching the first dielectric layer 1141 and the second dielectric layer 1142.

[0076] The material of the first dielectric layer 1141 may include an oxide such as silicon oxide. The material of the second dielectric layer 1142 may include a nitride such as silicon nitride. In one exemplary embodiment, the first dielectric layer 1141 and the second dielectric layer 1142 may be deposited by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In another exemplary embodiment, the first dielectric layer 1141 may be formed by oxidizing the surface of the semiconductor layer 1100 by an oxidation process such as an oxidation process.

[0077] Figure 4 and Figure 5 These are schematic diagrams illustrating the formation of the initial semiconductor pillar 1130 and the isolation pillar 1150 according to exemplary embodiments of this application, wherein... Figure 5 for Figure 4 A schematic diagram of a partial cross-section along the AA direction. For example, as shown... Figure 4 and Figure 5 As shown, a plurality of initial semiconductor pillars 1130 extending along the first direction X and the second direction Z can be formed within the semiconductor layer 1100.

[0078] For example, a plurality of isolation pillars 1150 extending along a first direction X and a second direction Z may be formed within the semiconductor layer 1100, wherein the plurality of isolation pillars 1150 divide a portion of the semiconductor layer 1100 into a plurality of initial semiconductor pillars 1130. The initial semiconductor pillars 1130 and the isolation pillars 1150 may be arranged alternately along a third direction Y. For example, a plurality of grooves (not shown) extending along the first direction X and the second direction Z may be formed within the semiconductor layer 1100; and isolation pillars 1150 may be formed within the grooves, wherein the unremoved semiconductor layer 1100 forms the initial semiconductor pillars 1130.

[0079] For example, an etching process can be used to etch the second dielectric layer 1142, the first dielectric layer 1141, and the semiconductor layer 1100 to form a groove and an initial semiconductor pillar 1130. For instance, a photolithography process can be used to etch the second dielectric layer 1142 and the first dielectric layer 1141 to form a patterned mask, wherein the second dielectric layer 1142 can serve as the bottom anti-reflection layer for photolithography, and the first dielectric layer 1141 can serve as a hard mask; then, using the patterned mask as a mask, the semiconductor layer 1100 is etched by one or more dry etching and / or wet etching processes to etch a groove in the semiconductor layer 1100, wherein the unremoved semiconductor layer 1100 can form the initial semiconductor pillar 1130.

[0080] Exemplarily, the material of the isolation pillar 1150 may include, but is not limited to, insulating materials such as oxides. Exemplarily, the isolation pillar 1150 may be formed by depositing insulating material in the trench using a thin-film deposition process, such as a thin-film deposition process, so that adjacent initial semiconductor pillars 1130 are isolated by the isolation pillar 1150. In addition, a planarization process such as a mechanical polishing process may be performed to remove the insulating material from the surface of the second dielectric layer 1142.

[0081] Figure 6 and Figure 7 These are schematic diagrams of the structure of the portion of the first groove 100 formed on the plane formed by the first direction X and the second direction Z, and on the plane formed by the third direction Y and the first direction X, according to exemplary embodiments of this application. Figure 7 for Figure 6 A partial cross-sectional schematic diagram along the BB direction. For example, as shown... Figure 6 and Figure 7 As shown, a plurality of first trenches 100 can be formed that pass through the initial semiconductor pillar 1130 and extend along a third direction Y and are arranged along a first direction X, wherein the plurality of first trenches 100 can divide the initial semiconductor pillar 1130 into a plurality of semiconductor pillars 1110 extending along a second direction Z.

[0082] Exemplarily, the first trench 100 may be formed by etching using one or more dry etching and / or wet etching processes. The first trench 100 may divide the initial semiconductor pillar 1130 into a plurality of semiconductor pillars 1110. In this application, the semiconductor pillars 1110 are formed by etching the semiconductor layer 1100; therefore, the semiconductor pillars 1110 may have the same material as the semiconductor layer 1100 and may extend in the semiconductor layer 1100 along the second direction Z.

[0083] Figures 8 to 13 This is a process step diagram provided in this application for forming a first gate structure 1200 and an isolation layer 1300.

[0084] like Figures 8 to 13 As shown, a first gate structure 1200 extending in the third direction Y and adjacently distributed in the second direction Z can be formed on the sidewall of the semiconductor pillar 1110 via a first trench 100. Exemplarily, the first gate structure 1200 can be formed near the first end 1111 of the semiconductor pillar 1110 in the first trench 100, and the isolation layer 1300 can be formed on the surface of the first gate structure 1200. Exemplarily, two symmetrically distributed first gate structures 1200 can be formed in the first trench 100, wherein... Figure 14 A partial structural schematic diagram of a first gate structure 1200 is shown.

[0085] For example, forming a first gate structure 1200 and an isolation layer 1300 extending in a third direction Y and adjacently distributed in a second direction Z on the sidewall of the semiconductor pillar 1110 via a first trench 100 may include: forming a first gate dielectric layer 1210 extending in a third direction Y on the sidewall of the semiconductor pillar 1110 via the first trench 100; forming a first gate 1220 layer on the surface of the first gate dielectric layer 1210, wherein the first gate layer 1220 and the first gate dielectric layer 1210 may be adjacently distributed in a first direction X, the first gate structure 1200 includes the first gate layer 1220 and the first gate dielectric layer 1210; and forming an isolation layer 1300 on the surface of the first gate structure 1200.

[0086] Specifically, Figure 8 and Figure 9 These are schematic diagrams of the structures forming the first dielectric layer 1230 and the third dielectric layer 1240 according to exemplary embodiments of this application, wherein... Figure 9 for Figure 8 A partial cross-sectional schematic diagram along the BB direction. For example, as shown... Figure 8 and Figure 9As shown, a first dielectric layer 1230 may be formed in the region of the first trench 100 near the first end 1111 of the semiconductor pillar 1110; a portion of the first dielectric layer 1230 may be removed along the second direction Z. For example, one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, may be used to deposit and form the first dielectric layer 1230. The material of the first dielectric layer 1230 may include, but is not limited to, silicon oxide. Exemplarily, prior to forming the first dielectric layer 1230, a third dielectric layer 1240 may be deposited and formed on a portion of the sidewalls of the first trench 100 to partially fill the first trench 100. Exemplarily, a portion of the first dielectric layer 1230 may be removed along the second direction Z, such that the remaining first dielectric layer 1230 covers the bottom surface of the first trench 100.

[0087] Figure 10 and Figure 11 This is a schematic diagram of the structure forming the first gate dielectric layer 1210 and the first gate layer 1220 according to an exemplary embodiment of this application, wherein, Figure 11 for Figure 10 A partial cross-sectional schematic diagram along the BB direction. For example, as shown... Figure 10 and Figure 11 As shown, a first gate dielectric layer 1210 extending in the third direction Y can be formed in the region of the first trench 100 near the first end 1111 of the semiconductor pillar 1110; and a first gate layer 1220 is formed on the surface of the first gate dielectric layer 1210, wherein the first gate layer 1220 and the first gate dielectric layer 1210 are distributed adjacent to each other in the first direction X.

[0088] Exemplarily, the first gate dielectric layer 1210 may be part of a continuous third dielectric layer 1240 formed on the sidewall of a semiconductor pillar 1110 extending along the second direction Z. The first gate dielectric layer 1210 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the first gate dielectric layer 1210 may include silicon oxide, i.e., a gate oxide. Exemplarily, wet oxidation and / or dry oxidation processes, such as in-situ vapor oxidation processes, may be performed to form the first gate dielectric layer 1210 in a region of the first trench 100 near the first end 1111 of the semiconductor pillar 1110.

[0089] Then, a first gate layer 1220 can be formed on the surface of the first gate dielectric layer 1210. Exemplarily, the first gate layer 1220 can be formed by depositing one or more conductive materials, such as metals and / or metal compounds, such as tungsten W and titanium nitride TiN, on the surface of the first gate dielectric layer 1210 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. For example, TiN and W can be deposited sequentially to form the first gate layer 1220, wherein TiN may surround W.

[0090] Figure 12 and Figure 13 This is a schematic diagram of the structure forming a second dielectric layer 1250, an isolation layer 1300, and a via 200 according to an exemplary embodiment of this application, wherein, Figure 13 for Figure 12 A partial cross-sectional schematic diagram along the BB direction. For example, as shown... Figure 12 As shown, a portion of the first gate layer 1220 can be removed along the second direction Z, such as removing portion W, to form a first gap (not shown); a second gap (not shown) can be formed along the second direction Z through the first gate layer 1220 to expose the first dielectric layer 1230, such as removing the TiN exposed at the bottom to expose the first dielectric layer 1230; and a second dielectric layer 1250 can be formed within the first gap and the second gap. Exemplarily, the third dielectric layer 1240, the first dielectric layer 1230, the second dielectric layer 1250, the first gate dielectric layer 1210, and the unremoved first gate layer 1220 can be used to form the first gate structure 1200. Specifically, Figure 14 A partial structural schematic diagram of a first gate structure 1200 is shown. The third dielectric layer 1240, first dielectric layer 1230, second dielectric layer 1250, first gate dielectric layer 1210, and the remaining first gate layer 1220 in the first trench 100 can be used to form at least two symmetrically distributed first gate structures 1200. The first gate layer 1220 can extend along a third direction Y, and the portion corresponding to the semiconductor pillar 1110 can serve as the first gate electrode; the remaining portion can serve as a first word line for connecting the first gate electrode to the peripheral circuit, enabling the transmission of electrical signals between the first gate electrode and the peripheral circuit.

[0091] Exemplarily, etching processes such as bottom-drilling etching, dry etching, and / or wet etching can be used to form the second gap to form two disconnected first gate structures 1200 in the first trench 100. Exemplarily, a bottom-drilling etching process can be used to disconnect the first gate structure 1200 at the bottom of the first trench 100 until the first dielectric layer 1230 is exposed.

[0092] For example, such as Figure 12As shown, an isolation layer 1300 can be formed on the surface of the first gate structure 1200. In other words, the isolation layer 1300 can be formed on the surfaces of the first gate dielectric layer 1210, the first gate layer 1220, and the second dielectric layer 1250. In this application, the first gate structure 1200 may be located in the region of the first trench 100 near the first end 1111 of the semiconductor pillar 1110, and the isolation layer 1300 may be located in the region of the first trench 100 near the second end 1112 of the semiconductor pillar 1110.

[0093] Exemplarily, the isolation layer 1300 and the second dielectric layer 1250 may be formed in the same process step. Exemplarily, one or more thin-film deposition processes may be used to deposit and form the second dielectric layer 1250 and the isolation layer 1300 in the regions of the first gap, the second gap, and the first trench 100 near the second end 1112 of the semiconductor pillar 1110. In other words, the second dielectric layer 1250 and the isolation layer 1300 may be deposited and formed in the remaining space of the first trench 100. The second dielectric layer 1250 and the isolation layer 1300 may comprise the same material, such as any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the second dielectric layer 1250 and the isolation layer 1300 may comprise silicon oxide. In addition, a planarization process such as a mechanical polishing process may be performed to remove the isolation layer 1300, the second dielectric layer 1142, and the first dielectric layer 1141 from the top surface of the semiconductor pillar 1110.

[0094] For example, such as Figure 13 As shown, vias 200 can be formed along the second direction Z through the first gate dielectric layer 1210 and the first gate layer 1220 to divide the annular first gate structure 1200 in the first trench 100 into at least two parts. For example, two vias 200 with a certain interval can be formed in each annular first gate structure 1200 to divide the annular first gate structure 1200 into two parts. In other words, the two vias 200 divide the annular first gate dielectric layer 1210 into two parts and the first gate layer 1220 into two parts.

[0095] It should be understood that this application does not specifically limit the size and / or position of the via 200. The size and / or position of the via 200 can be arbitrarily set according to the actual process to divide the first gate structure 1200 in the first trench 100 into two parts.

[0096] Figure 15 and Figure 16 This is a schematic diagram of the structure forming the isolation structure 1400 and the barrier layer 1500 according to an exemplary embodiment of this application, wherein, Figure 16 for Figure 15 A partial cross-sectional schematic diagram along the BB direction. For example, as shown... Figure 15 and Figure 16 As shown, a second trench (not shown) is formed through the semiconductor pillar 1110 and extending along a third direction Y; and an isolation structure 1400 is formed in the second trench. In other words, the formed isolation structure 1400 divides each semiconductor pillar 1110 into two semiconductor pillars 1110, i.e., the isolation structure 1400 can be located between two adjacent semiconductor pillars 1110 arranged along the first direction X.

[0097] Exemplarily, the second trench can be formed by etching using one or more dry etching and / or wet etching processes, and the isolation structure 1400 and / or barrier layer 1500 can be formed using one or more thin film deposition processes. The second trench can divide each semiconductor pillar 1110 into two semiconductor pillars 1110. Exemplarily, the isolation structure 1400 can be formed in the second trench near the first end 1111 of the semiconductor pillar 1110, and the barrier layer 1500 can be formed on the surface of the isolation structure 1400. That is, the isolation structure 1400 can be located in the region of the second trench near the first end 1111 of the semiconductor pillar 1110, and the barrier layer 1500 can be located in the region of the second trench near the second end 1112 of the semiconductor pillar 1110. In other words, the height of the isolation structure 1400 and the first gate structure 1200 can be approximately the same, and the height of the barrier layer 1500 and the isolation layer 1300 can be approximately the same.

[0098] Exemplarily, the isolation structure 1400 may include a conductive layer and / or an air gap layer. Specifically, an air gap layer (such as an air gap) and / or a conductive layer (such as a metal material layer) may be formed in the second trench according to the spacing of the semiconductor pillars 1110, such as the dimension of the second trench along the first direction X. The barrier layer 1500 may include an insulating layer and / or an air gap layer. Specifically, an air gap layer (such as an air gap) and / or an insulating layer (such as an oxide material layer) may be formed on the surface of the isolation structure 1400 according to the spacing of the semiconductor pillars 1110, such as the dimension of the second trench along the first direction X.

[0099] For example, if the isolation structure 1400 includes a conductive layer, an isolation lead-out structure (not shown) connected to the isolation structure 1400 can also be formed. In this application, the isolation lead-out structure can be grounded or a certain fixed potential can be applied to the isolation lead-out structure, so that the isolation structure 1400 can electrically insulate adjacent semiconductor pillars 1110 and reduce the coupling phenomenon between adjacent semiconductor pillars 1110.

[0100] Figure 17 for Figure 15 A partial cross-sectional diagram along the CC direction. Figure 18 for Figure 17 A partial cross-sectional diagram along the DD direction. Figures 19 to 22This is a process step diagram for forming a second gate structure 1600 provided in this application. Figures 23 to 27 This is another process step diagram for forming the second gate structure 1600 provided in this application. It should be understood that the process for forming the second gate structure 1600 provided in this application is only an example and not a specific limitation. In actual processes, the process for forming the second gate structure 1600 can be reasonably set according to actual needs.

[0101] In one exemplary embodiment of this application, such as Figure 21 and Figure 22 As shown, a second gate structure 1600 extending along the first direction X can be formed on the sidewall of the semiconductor pillar 1110, wherein the second gate structure 1600 and the first gate structure 1200 are spaced apart along the second direction Z.

[0102] For example, forming a second gate structure 1600 extending in a first direction X on a sidewall of a semiconductor pillar 1110 may include forming the second gate structure 1600 extending in the first direction X on at least one of a first sidewall 1113 and a second sidewall 1114 of the semiconductor pillar 1110 that are opposite each other in a third direction Y. For example, as Figures 19 to 22 As shown, a third trench 300 can be formed that passes through the isolation layer 1300 and the isolation pillar 1150 and extends along the first direction X. Figure 19 and Figure 20 ); and a second gate structure 1600 is formed via a third trench 300. Figure 21 and Figure 22 ).

[0103] Specifically, Figure 19 and Figure 20 These are schematic diagrams of the structure forming the third trench 300 according to exemplary embodiments of this application, wherein, Figure 20 for Figure 19 A partial cross-sectional schematic diagram along the DD direction. For example, as shown... Figure 19 and Figure 20 As shown, a third trench 300 can be formed, passing through the isolation layer 1300 and the isolation pillar 1150 and extending along the first direction X. Exemplarily, the third trench 300 and the first gate structure 1200 can be spaced apart along the second direction Z. In other words, the third trench 300 and the first gate structure 1200 are not connected and can be separated from each other by the isolation layer 1300. Exemplarily, the third trench 300 can be formed by etching using one or more dry etching and / or wet etching processes.

[0104] Figure 21 and Figure 22 These are schematic diagrams of the formation of the second gate structure 1600 according to exemplary embodiments of this application, wherein, Figure 22for Figure 21 A partial cross-sectional diagram along the DD direction. (See diagram below.) Figure 21 and Figure 22 As shown, a second gate structure 1600 can be formed via a third trench 300. Exemplarily, the second gate structure 1600 extending in the first direction X can be formed on at least one of the first sidewall 1113 and the second sidewall 1114 of the semiconductor pillar 1110, which are opposite each other in the third direction Y. For example, Figure 21 and Figure 22 This illustrates a case where a second gate structure 1600 can be formed on both the first sidewall 1113 and the second sidewall 1114.

[0105] Exemplarily, the second gate structure 1600 may include a second gate dielectric layer 1610 and a second gate layer 1620. The second gate dielectric layer 1610 may be located on the sidewall of the semiconductor pillar 1110, and the second gate layer 1620 may be located outside the second gate dielectric layer 1610. For example, the semiconductor pillar 1110, the second gate dielectric layer 1610, and the second gate layer 1620 are arranged sequentially along a third direction Y.

[0106] Exemplarily, the second gate dielectric layer 1610 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the second gate dielectric layer 1610 may comprise silicon oxide, i.e., a gate oxide. The second gate layer 1620 may comprise any suitable conductive material, such as a metal and / or a metal compound. For example, the second gate layer 1620 may comprise tungsten.

[0107] For example, a second gate layer 1620 can be formed by depositing a conductive material in a third trench 300; then a second gate dielectric layer 1610 can be formed by removing the conductive material on at least one of the first sidewalls 1113 and the second sidewalls 1114 and depositing a dielectric material.

[0108] Exemplarily, two symmetrically distributed second gate structures 1600 can be formed in the third trench 300. For example, two second gate layers 1620 can be formed by filling the third trench with a dielectric material 1630 to isolate the conductive material. Exemplarily, the second gate layer 1620 can extend along the first direction X, and the portion corresponding to the semiconductor pillar 1110 can serve as the second gate electrode; the remaining portion can serve as a second word line for connecting the second gate electrode to the peripheral circuit, thereby enabling the transmission of electrical signals between the second gate electrode and the peripheral circuit. In this application, the first gate structure 1200 and the second gate structure 1600 work together to enable the semiconductor pillar 1110 to conduct.

[0109] In another exemplary embodiment of this application, such as Figures 25 to 27As shown, the second gate structure 1600 may include a first sub-gate structure 1600-1 and a second sub-gate structure 1600-2. Forming the second gate structure 1600 extending along a first direction X on the sidewall of the semiconductor pillar 1110 may include: forming a first sub-gate structure 1600-1 extending along the first direction X on at least one of the first sidewall 1113 and the second sidewall 1114 of the semiconductor pillar 1110, which are opposite each other along a third direction Y. Figure 25 and Figure 26 ); and a second sub-gate structure 1600-2 is formed on at least one of the third sidewall 1115 and the fourth sidewall 1116 of the semiconductor pillar 1110, which are opposite each other in the first direction X. Figure 25 and Figure 27 For example, such as Figures 23 to 27 As shown, a third trench 300 extending through the isolation layer 1300 and the isolation pillar 1150 and along the first direction X, and a fourth trench 400 extending through the isolation layer 1300 and along the third direction Y can be formed. Figure 23 and Figure 24 The first sub-gate structure 1600-1 and the second sub-gate structure 1600-2 are formed via the third trench 300 and the fourth trench 400, respectively. Figures 25 to 27 ).

[0110] Specifically, Figure 23 and Figure 24 These are schematic diagrams of the structures forming the third trench 300 and the fourth trench 400 according to exemplary embodiments of this application, wherein, Figure 24 for Figure 23 A partial cross-sectional schematic diagram along the DD direction. For example, as shown... Figure 23 and Figure 24 As shown, a third trench 300 is formed, extending through the isolation layer 1300 and the isolation pillar 1150 and along a first direction X, and a fourth trench 400 is formed, extending through the isolation layer 1300 and along a third direction Y. Exemplarily, the third trench 300 and the fourth trench 400 may be spaced apart from the first gate structure 1200 along a second direction Z. In other words, the third trench 300 (or the fourth trench 400) and the first gate structure 1200 are not connected, and are separated from each other by the isolation layer 1300. Exemplarily, the third trench 300 and the fourth trench 400 may be formed by etching using one or more dry etching and / or wet etching processes.

[0111] Figures 25 to 27 These are schematic diagrams of the formation of the second gate structure 1600 according to exemplary embodiments of this application, wherein, Figure 26 for Figure 25 A partial cross-sectional diagram along the DD direction. Figure 27 for Figure 25A partial cross-sectional diagram along the EE direction. (See diagram below.) Figures 25 to 27 As shown, a first sub-gate structure 1600-1 and a second sub-gate structure 1600-2 can be formed via a third trench 300 and a fourth trench 400, respectively. Exemplarily, a first sub-gate structure 1600-1 extending in a first direction X can be formed on at least one of a first sidewall 1113 and a second sidewall 1114 of the semiconductor pillar 1110, which are opposite each other in the third direction Y; and a second sub-gate structure 1600-2 can be formed on at least one of a third sidewall 1115 and a fourth sidewall 1116 of the semiconductor pillar 1110, which are opposite each other in the first direction X. For example, Figure 25 and Figure 26 This illustrates that a first sub-gate structure 1600-1 can be formed on both the first sidewall 1113 and the second sidewall 1114, and Figure 25 and Figure 27 The case in which a second sub-gate structure 1600-2 can be formed on both the third sidewall 1115 and the fourth sidewall 1116 is shown.

[0112] Exemplarily, the first sub-gate structure 1600-1 and / or the second sub-gate structure 1600-2 may include a second gate dielectric layer 1610 and a second gate layer 1620. The second gate dielectric layer 1610 may be located on the sidewall of the semiconductor pillar 1110, and the second gate layer 1620 may be located on the outer surface of the second gate dielectric layer 1610. For example, the semiconductor pillar 1110, the second gate dielectric layer 1610, and the second gate layer 1620 are distributed sequentially from the center outwards.

[0113] For example, a second gate layer 1620 can be formed by depositing conductive material in a third trench 300 and / or a fourth trench 400; then a second gate dielectric layer 1610 can be formed by removing conductive material on at least one of the first sidewalls 1113, the second sidewall 1114, the third sidewall 1115 and the fourth sidewall 1116 and depositing dielectric material.

[0114] For example, two symmetrical first sub-gate structures 1600-1 can be formed in the third trench 300. For instance, two second gate layers 1620 can be formed by filling the third trench with a dielectric material 1630 to isolate the conductive material. For example, the second gate layer 1620 can extend along a first direction X, and the portion corresponding to the semiconductor pillar 1110 can serve as a second gate electrode; the remaining portion can serve as a first word line for connecting the second gate electrode to the peripheral circuit, thereby enabling the transmission of electrical signals between the first gate electrode and the peripheral circuit.

[0115] In the exemplary embodiments of this application, such as Figure 28As shown, a capacitor 1700 can be formed that is connected to the second end 1112 of the semiconductor pillar 1110. The capacitor 1700 may include a first electrode (not shown) connected to the second end 1112 of the semiconductor pillar 1110, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1700 may include, but is not limited to, planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-planar capacitors. Exemplarily, the capacitor 1700 may be a vertical capacitor, wherein the first electrode, capacitor dielectric, and second electrode are stacked along a second direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0116] Figure 29 To be Figure 28 A schematic diagram of a structure that has been thinned after being flipped 180°. In an exemplary embodiment of this application, such as... Figure 29 As shown, a portion of the semiconductor layer 1100 can be removed from the side away from the semiconductor pillar 1110 to expose the first end 1111 of the semiconductor pillar 1110.

[0117] Figures 30 to 32 This is a partial structural schematic diagram of the semiconductor structure after forming bit line 1800 according to an exemplary embodiment of this application, on the plane formed by the first direction X and the second direction Z, the plane formed by the first direction X and the third direction Y, and the plane formed by the third direction Y and the second direction Z.

[0118] In the exemplary embodiments of this application, such as Figures 30 to 32 As shown, a bit line 1800 can be formed that is connected to the semiconductor pillar 1110 and extends along the first direction X. Exemplarily, the bit line 1800 can be formed at the first end 1111 of the semiconductor pillar 1110, that is, the bit line 1800 can be connected to the first end 1111 of the semiconductor pillar 1110 and extend along the first direction X.

[0119] In this application, preset first gate structures in multiple first gate structures 1200 and preset second gate structures in multiple second gate structures 1600 can be turned on to address preset semiconductor pillars in multiple semiconductor pillars 1110 and preset bit lines 1800 connected to the preset semiconductor pillars. This puts the preset bit line 1800 in a sensing state, while the bit lines adjacent to the preset bit line 1800 are in a non-sensing state. Specifically, when the preset first gate structure and the preset second gate structure are turned on, other first gate structures adjacent to the preset first gate structure are turned off, and other second gate structures adjacent to the preset second gate structure are turned off. At this time, only the preset bit line is in a sensing state, and other bit lines adjacent to the preset bit line can be connected to a fixed voltage. This reduces the coupling phenomenon between the preset bit line and other adjacent bit lines, thereby helping to reduce interference between adjacent bit lines. For example, in this application, the potential amplitude of the preset bit line in the sensing state can be increased to 150mV, greatly improving the sensing intensity of the semiconductor structure.

[0120] In the exemplary embodiments of this application, such as Figure 30 As shown, bit line 1800 may be adjacent to the first gate structure 1200 along the second direction Z. Exemplarily, a first gate lead-out structure 1910 and a bit line lead-out structure 1920, respectively connected to the first gate structure 1200 and bit line 1800, may be formed from a first side of the semiconductor layer 1100 (e.g., the side near the first end 1111 of the semiconductor pillar 1110). Figure 30 ); and a second gate lead-out structure 1930 connected to the second gate structure 1600 is formed from the second side of the semiconductor layer 1100 opposite to the first side (such as the side near the second end 1112 of the semiconductor pillar 1110). Figure 32 For example, the first gate lead-out structure 1910, the bit line lead-out structure 1920, and the second gate lead-out structure 1930 can be used to connect the first gate structure 1200, the bit line 1800, and the second gate structure 1600 to external circuits, respectively.

[0121] Figures 30 to 32 This is a partial structural schematic diagram of a semiconductor structure provided according to an exemplary embodiment of this application, on a plane formed by a first direction X and a second direction Z, a plane formed by the first direction X and a third direction Y, and a plane formed by the third direction Y and the second direction Z. The semiconductor structure includes a plurality of semiconductor pillars 1110, a first gate structure 1200, a second gate structure 1600, and a bit line 1800.

[0122] Multiple semiconductor pillars 1110 can extend along the second direction Z and be arrayed along the first direction X and the third direction Y, wherein the first direction X, the second direction Z and the third direction Y intersect each other.

[0123] For example, a plurality of semiconductor pillars 1110 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillars 1110. For example, the semiconductor pillars 1110 may have a cubic shape to expose their four sidewalls. It should be understood that the semiconductor pillars 1110 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillars 1110 in a planar view (e.g., in the XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape.

[0124] The material of the semiconductor pillar 1110 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0125] The first gate structure 1200 may be located on the sidewall of the semiconductor pillar 1110 and extend in the third direction Y. The first gate structure 1200 may include a first gate dielectric layer 1210 and a first gate layer 1220. The first gate dielectric layer 1210 may be located on the sidewall of the semiconductor pillar 1110. The first gate layer 1220 may be located inside the first gate dielectric layer 1210, such as on the inner surface of the first gate dielectric layer 1210.

[0126] The first gate dielectric layer 1210 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the first gate dielectric layer 1210 may include silicon oxide, i.e., a gate oxide. The first gate layer 1220 may include any suitable conductive material, such as one or more conductive materials such as metals and / or metal compounds such as tungsten W and titanium nitride TiN.

[0127] Exemplarily, the first gate structure 1200 may further include a dielectric layer (including a first dielectric layer 1230 and a third dielectric layer 1240) and a second dielectric layer 1250. The dielectric layer may be located at a first end 1111 of the first gate structure 1200 near the semiconductor pillar 1110, wherein the third dielectric layer 1240 may surround a portion of the first dielectric layer 1230, and the first gate layer 1220 and the first gate dielectric layer 1210 may be located on the dielectric layer. The second dielectric layer 1250 may be located on the first dielectric layer 1230 and may be located on the surface of the first gate layer 1220. The first dielectric layer 1230, the third dielectric layer 1240, and the second dielectric layer 1250 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0128] For example, two adjacent first gate structures 1200 may be symmetrically distributed along the second direction Z. The first dielectric layer 1230, second dielectric layer 1250, and third dielectric layer 1240 in the two partially symmetrical first gate structures 1200 are continuous. In other words, the first dielectric layer 1230 in the two partially symmetrical first gate structures 1200 may be connected to form a single structure, the second dielectric layer 1250 in the two first gate structures 1200 may be connected to form a single structure, and the third dielectric layer 1240 in the two first gate structures 1200 may be connected to form a single structure. Figure 14 As shown, a partial structural schematic diagram of a first gate structure 1200 is presented.

[0129] Exemplarily, the semiconductor pillar 1110 and the first gate structure 1200 can be used together to form a vertical transistor, wherein the semiconductor pillar 1110 can be used to form the active region of a plurality of channels in the vertical transistor. Exemplarily, the first gate structure 1200 can be located on at least one sidewall of the semiconductor pillar 1110, i.e., the semiconductor pillar 1110 can be at least partially surrounded by the first gate structure 1200. For example, the semiconductor pillar 1110, the first gate dielectric layer 1210, and the first gate layer 1220 can be arranged radially from the center of the vertical transistor in this order. Exemplarily, the first gate dielectric layer 1210 can surround and contact the semiconductor pillar 1110. The first gate layer 1220 can surround and contact the first gate dielectric layer 1210.

[0130] In one embodiment of this application, reference may be made to Figure 12 and Figure 13 As shown, the first gate structure 1200 can be located on multiple sidewalls of the semiconductor pillar 1110. In this case, the semiconductor pillar 1110 and the first gate structure 1200 can be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). Multi-gate transistors can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the off-state, the leakage current of the multi-gate transistor can also be significantly reduced because the channel is completely depleted. Therefore, using a multi-gate transistor can achieve better speed (saturation drain current) / leakage current performance.

[0131] In another embodiment of this application, reference may be made to Figure 15 and Figure 16As shown, the first gate structure 1200 can be located on one sidewall of the semiconductor pillar 1110, where the semiconductor pillar 1110 and the first gate structure 1200 can be used together to form a single-gate transistor. Exemplarily, adjacent single-gate transistors along the first direction X can be arranged symmetrically. By setting single-gate transistors, this application can significantly increase the density of semiconductor pillars 1110 in the first direction X, reducing manufacturing process difficulty. Furthermore, symmetrically distributed single-gate transistors can have a larger process window, which is beneficial for reducing subsequent bit lines, word lines, and the spacing between transistors.

[0132] Exemplarily, the semiconductor structure may further include an isolation layer 1300 located on the surface of the first gate structure. In other words, the isolation layer 1300 may be located on the surfaces of the first gate dielectric layer 1210, the first gate layer 1220, and the second dielectric layer 1250. In this application, the first gate structure 1200 may be located in the region of the first trench 100 near the first end 1111 of the semiconductor pillar 1110, and the isolation layer 1300 may be located in the region of the first trench 100 near the second end 1112 of the semiconductor pillar 1110.

[0133] The second dielectric layer 1250 and the isolation layer 1300 may comprise the same material, such as any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the second dielectric layer 1250 and the isolation layer 1300 may comprise silicon oxide.

[0134] In an exemplary embodiment of this application, the semiconductor structure may further include an isolation structure 1400 and a barrier layer 1500. The isolation structure 1400 may be located between two adjacent semiconductor pillars 1110 arranged along a first direction X. The barrier layer 1500 may be located on the surface of the isolation structure 1400. That is, the isolation structure 1400 may be located in the region of the second trench near the first end 1111 of the semiconductor pillar 1110, and the barrier layer 1500 may be located in the region of the second trench near the second end 1112 of the semiconductor pillar 1110. In other words, the height of the isolation structure 1400 and the first gate structure 1200 may be approximately the same, and the height of the barrier layer 1500 and the isolation layer 1300 may be approximately the same.

[0135] Exemplarily, the isolation structure 1400 may include a conductive layer and / or an air gap layer. Specifically, an air gap layer (such as an air gap) and / or a conductive layer (such as a metal material layer) may be formed in the second trench according to the spacing of the semiconductor pillars 1110, such as the dimension of the second trench along the first direction X. The barrier layer 1500 may include an insulating layer and / or an air gap layer. Specifically, an air gap layer (such as an air gap) and / or an insulating layer (such as an oxide material layer) may be formed on the surface of the isolation structure 1400 according to the spacing of the semiconductor pillars 1110, such as the dimension of the second trench along the first direction X.

[0136] For example, if the isolation structure 1400 includes a conductive layer, an isolation lead-out structure (not shown) connected to the isolation structure 1400 can also be formed. In this application, the isolation lead-out structure can be grounded or a certain fixed potential can be applied to the isolation lead-out structure, so that the isolation structure 1400 can electrically insulate adjacent semiconductor pillars 1110 and reduce the coupling phenomenon between adjacent semiconductor pillars 1110.

[0137] The second gate structure 1600 may be located on the sidewall of the semiconductor pillar 1110 and extend along the first direction X, wherein the second gate structure 1600 and the first gate structure 1200 may be spaced apart along the second direction Z.

[0138] In one exemplary embodiment of this application, reference may be made to Figure 21 and Figure 22 As shown, the second gate structure 1600 may be located on at least one of the first sidewall 1113 and the second sidewall 1114 of the semiconductor pillar 1110, which are opposite each other in the third direction Y. The second gate structure 1600 and the first gate structure 1200 are not connected and can be separated from each other by an isolation layer 1300.

[0139] Exemplarily, the second gate structure 1600 may include a second gate dielectric layer 1610 and a second gate layer 1620. The second gate dielectric layer 1610 may be located on the sidewall of the semiconductor pillar 1110, and the second gate layer 1620 may be located outside the second gate dielectric layer 1610. For example, the semiconductor pillar 1110, the second gate dielectric layer 1610, and the second gate layer 1620 are arranged sequentially along a third direction Y.

[0140] Exemplarily, the second gate dielectric layer 1610 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the second gate dielectric layer 1610 may comprise silicon oxide, i.e., a gate oxide. The second gate layer 1620 may comprise any suitable conductive material, such as a metal and / or a metal compound. For example, the second gate layer 1620 may comprise tungsten.

[0141] Exemplarily, at least two adjacent second gate structures 1600 may be symmetrically distributed. The semiconductor structure may also include a dielectric material 1630 located between at least two adjacent second gate structures 1600 to isolate adjacent second gate layers 1620. Exemplarily, the second gate layer 1620 may extend along a first direction X, and the portion corresponding to the semiconductor pillar 1110 may serve as a second gate electrode; the remaining portion may serve as a second word line for connecting the second gate electrode to a peripheral circuit, thereby enabling the transmission of electrical signals between the second gate electrode and the peripheral circuit. In this application, the first gate structure 1200 and the second gate structure 1600 work together to enable the semiconductor pillar 1110 to conduct.

[0142] In another exemplary embodiment of this application, reference may be made to Figures 25 to 27 As shown, the second gate structure 1600 may include a first sub-gate structure 1600-1 and a second sub-gate structure 1600-2. The first sub-gate structure 1600-1 may be located on at least one of the first sidewalls 1113 and 1114 of the semiconductor pillar 1110, which are opposite each other in the third direction Y. The second sub-gate structure 1600-2 may be located on at least one of the third sidewalls 1115 and 1116 of the semiconductor pillar 1110, which are opposite each other in the first direction X. For example, Figure 25 and Figure 26 This illustrates that a first sub-gate structure 1600-1 can be formed on both the first sidewall 1113 and the second sidewall 1114, and Figure 25 and Figure 27 The case in which a second sub-gate structure 1600-2 can be formed on both the third sidewall 1115 and the fourth sidewall 1116 is shown.

[0143] For example, the first sub-gate structure 1600-1 can pass through the isolation layer 1300 and the isolation pillar 1150 and extend along a first direction X. The second sub-gate structure 1600-2 can pass through the isolation layer 1300 and extend along a third direction Y. The first sub-gate structure 1600-1 (or the second sub-gate structure 1600-2) and the first gate structure 1200 are not connected and can be separated from each other by the isolation layer 1300.

[0144] Exemplarily, the first sub-gate structure 1600-1 and / or the second sub-gate structure 1600-2 may include a second gate dielectric layer 1610 and a second gate layer 1620. The second gate dielectric layer 1610 may be located on the sidewall of the semiconductor pillar 1110, and the second gate layer 1620 may be located on the outer surface of the second gate dielectric layer 1610. For example, the semiconductor pillar 1110, the second gate dielectric layer 1610, and the second gate layer 1620 are distributed sequentially from the center outwards.

[0145] Bit line 1800 may be connected to semiconductor pillar 1110 and extend along a first direction X. Exemplarily, bit line 1800 may be connected to a first end 1111 of semiconductor pillar 1110 and extend along a first direction X.

[0146] In this application, preset first gate structures in multiple first gate structures 1200 and preset second gate structures in multiple second gate structures 1600 can be turned on to address preset semiconductor pillars in multiple semiconductor pillars 1110 and preset bit lines 1800 connected to the preset semiconductor pillars. This puts the preset bit line 1800 in a sensing state, while the bit lines adjacent to the preset bit line 1800 are in a non-sensing state. Specifically, when the preset first gate structure and the preset second gate structure are turned on, other first gate structures adjacent to the preset first gate structure are turned off, and other second gate structures adjacent to the preset second gate structure are turned off. At this time, only the preset bit line is in a sensing state, and other bit lines adjacent to the preset bit line can be connected to a fixed voltage. This reduces the coupling phenomenon between the preset bit line and other adjacent bit lines, thereby helping to reduce interference between adjacent bit lines. For example, in this application, the potential amplitude of the preset bit line in the sensing state can be increased to 150mV, greatly improving the sensing intensity of the semiconductor structure.

[0147] In an exemplary embodiment of this application, the semiconductor structure may further include a capacitor 1700 connected to the second end 1112 of the semiconductor pillar 1110, the second end being located on the side of the semiconductor pillar 1110 away from the first end 1111. The capacitor 1700 may include a first electrode (not shown) connected to the second end 1112 of the semiconductor pillar 1110, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1700 may include, but is not limited to, planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-planar capacitors. Exemplarily, the capacitor 1700 may be a vertical capacitor, wherein the first electrode, capacitor dielectric, and second electrode are stacked along a second direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0148] Since the content and structure described above in the method 1000 for manufacturing a semiconductor structure can be applied in whole or in part to the semiconductor structure described herein, related or similar content will not be repeated here.

[0149] Although exemplary structures and fabrication methods of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the fabrication methods of the semiconductor structure. Furthermore, the layers and materials described are merely exemplary.

[0150] Figure 33This is a schematic block diagram of a memory 2000 according to an exemplary embodiment of this application. The memory 2000 may include a memory cell array 2100 and peripheral circuitry 2200.

[0151] The memory cell array 2100 and peripheral circuitry 2200 can be formed separately on different substrates and then bonded to form the memory 2000.

[0152] Peripheral circuitry 2200 may be coupled to memory cell array 2100. Peripheral circuitry 2200 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 2100. For example, peripheral circuitry 2200 may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0153] The memory cell array 2100 may include an array of memory cells (such as the semiconductor structure 1000 described above) that use transistors as switching and selection devices. In some embodiments, the memory cell array 2100 includes a DRAM cell array. For ease of description, a DRAM cell array may be used as an example to describe the memory cell array 2100 in the present application. However, it should be understood that the memory cell array 2100 is not limited to a DRAM cell array and may include any other suitable type of memory cell array 2100 that can use transistors as switching and selection devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, an FRAM cell array, a resistive memory cell array 2100, a magnetic memory cell array 2100, a spin transfer torque (STT) memory cell array 2100, to name just a few examples, or any combination thereof.

[0154] The memory cell array 2100 may be a DRAM device, wherein memory cells are provided in the form of an array of DRAM cells. In some embodiments, each DRAM cell includes a capacitor for storing data bits as positive or negative charges and one or more transistors (also referred to as transfer transistors) for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor-capacitor (ITC) cell. The DRAM cells may be refreshed, for example, by peripheral circuitry 2200 in the first semiconductor structure 102 to retain data.

[0155] Figure 34 This is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of this application.

[0156] System 10 can be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 12 located therein). Figure 34 As shown, system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more memories 2000 (including three-dimensional memory 14) and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memory 14.

[0157] The three-dimensional memory 14 may include the semiconductor structure described in any embodiment of this application. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18 and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device, such as a smartphone, tablet, laptop, etc. The controller 16 may be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0158] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 35AIn one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 34 The host 18) is coupled to the memory card connector 24. In such a way... Figure 35B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 34 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0159] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, The semiconductor layer includes a plurality of semiconductor pillars extending along a second direction and arrayed along a first direction and a third direction, wherein the first direction, the second direction, and the third direction intersect each other pairwise, and the method includes: A first gate structure extending in the third direction is formed on the sidewall of the semiconductor pillar; A second gate structure extending along the first direction is formed on the sidewall of the semiconductor pillar, wherein the second gate structure and the first gate structure are spaced apart along the second direction; and A bit line is formed that is connected to the semiconductor pillar and extends along the first direction.

2. The method according to claim 1, characterized in that, The bit line is adjacent to the first gate structure along the second direction, and the method includes: A first gate lead-out structure and a bit line lead-out structure, respectively connected to the first gate structure and the bit line, are formed from a first side of the semiconductor layer; and A second gate lead-out structure is formed from the second side of the semiconductor layer, opposite to the first side, and is connected to the second gate structure.

3. The method according to claim 1, characterized in that, A first gate structure extending in the third direction is formed on the sidewall of the semiconductor pillar, comprising: A plurality of initial semiconductor pillars extending along the first direction and the second direction are formed within the semiconductor layer; Forming a plurality of first trenches extending through the initial semiconductor pillar and along a third direction and arranged in a first direction, wherein the plurality of first trenches divide the initial semiconductor pillar into a plurality of semiconductor pillars extending along a second direction; and The first gate structure and the isolation layer are formed on the sidewall of the semiconductor pillar via the first trench, extending along the third direction and distributed adjacently along the second direction.

4. The method according to claim 3, characterized in that, The method further includes: Forming a second trench through the semiconductor pillar and extending in a third direction; and An isolation structure is formed in the second trench.

5. The method according to claim 3, characterized in that, The first gate structure and the isolation layer, extending along the third direction and adjacently distributed along the second direction, are formed on the sidewall of the semiconductor pillar via the first trench, including: A first gate dielectric layer extending in the third direction is formed on the sidewall of the semiconductor pillar via the first trench; A first gate layer is formed on the surface of the first gate dielectric layer, wherein the first gate layer and the first gate dielectric layer are distributed adjacent to each other along the first direction, and the first gate structure includes the first gate layer and the first gate dielectric layer; and The isolation layer is formed on the surface of the first gate structure.

6. The method according to claim 3, characterized in that, Forming a plurality of initial semiconductor pillars extending along the first direction and the second direction within the semiconductor layer, comprising: A plurality of isolation pillars extending along the first direction and the second direction are formed within the semiconductor layer, wherein the plurality of isolation pillars divide a portion of the semiconductor layer into a plurality of initial semiconductor pillars, and the initial semiconductor pillars and the isolation pillars are alternately arranged along the third direction.

7. The method according to claim 6, characterized in that, A second gate structure extending along the first direction is formed on the sidewall of the semiconductor pillar, comprising: A second gate structure extending in the first direction is formed on at least one of a first sidewall and a second sidewall that are opposite each other in the third direction of the semiconductor pillar.

8. The method according to claim 7, characterized in that, The method includes: Forming a third trench that passes through the isolation layer and the isolation pillar and extends along the first direction; and The second gate structure is formed via the third trench.

9. The method according to claim 6, characterized in that, The second gate structure includes a first sub-gate structure and a second sub-gate structure, wherein the second gate structure extending along the first direction is formed on the sidewall of the semiconductor pillar, comprising: A first sub-gate structure extending in the first direction is formed on at least one of a first sidewall and a second sidewall opposite in the third direction of the semiconductor pillar; and The second sub-gate structure is formed on at least one of the third and fourth sidewalls of the semiconductor pillar that are opposite each other along the first direction.

10. The method according to claim 9, characterized in that, The method includes: A third trench is formed that passes through the isolation layer and the isolation pillar and extends along the first direction, and a fourth trench passes through the isolation layer and extends along the third direction; The first sub-gate structure and the second sub-gate structure are formed via the third trench and the fourth trench, respectively.

11. The method according to any one of claims 1-10, characterized in that, The bit line is connected to the first end of the semiconductor pillar, and the method further includes: A capacitor is formed connected to a second end of the semiconductor pillar, the second end being located on the side of the semiconductor pillar away from the first end.

12. A semiconductor structure, characterized in that, include: Multiple semiconductor pillars extend along a second direction and are arrayed along a first direction and a third direction, wherein the first direction, the second direction and the third direction intersect each other; A first gate structure is located on the sidewall of the semiconductor pillar and extends along the third direction; A second gate structure is located on the sidewall of the semiconductor pillar and extends along the first direction, wherein the second gate structure and the first gate structure are spaced apart along the second direction; as well as Bit lines are connected to the semiconductor pillars and extend along the first direction.

13. The semiconductor structure according to claim 12, characterized in that, The second gate structure is located on at least one of the first and second sidewalls of the semiconductor pillar that are opposite each other in the third direction.

14. The semiconductor structure according to claim 12, characterized in that, The second gate structure includes: A first sub-gate structure is located on at least one of a first sidewall and a second sidewall that are perpendicular to each other along the third direction of the semiconductor pillar; and The second sub-gate structure is located on at least one of the third and fourth sidewalls of the semiconductor pillar, which are opposite each other along the first direction.

15. The semiconductor structure according to claim 12, characterized in that, The first gate structure is located on at least one of the third and fourth sidewalls of the semiconductor pillar, which are opposite each other along the first direction.

16. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure also includes: An isolation structure is located between two adjacent semiconductor pillars arranged along the first direction.

17. The semiconductor structure according to claim 12, characterized in that, The first gate structure includes a first gate dielectric layer located on the sidewall of the semiconductor pillar and a first gate layer located outside the first gate dielectric layer; and The second gate structure includes a second gate dielectric layer located on the sidewall of the semiconductor pillar and a second gate layer located outside the second gate dielectric layer.

18. The semiconductor structure according to claim 16, characterized in that, The isolation structure includes a conductive layer and / or an air gap layer.

19. The semiconductor structure according to claim 12, characterized in that, The bit line is connected to the first end of the semiconductor pillar, and the semiconductor structure further includes: A capacitor is connected to a second end of the semiconductor pillar, the second end being located on the side of the semiconductor pillar away from the first end.

20. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure includes a plurality of first gate structures and a plurality of second gate structures, wherein, In response to turning on a preset first gate structure among a plurality of first gate structures and a preset second gate structure among a plurality of second gate structures, a preset semiconductor pillar among a plurality of semiconductor pillars and a preset bit line connected to the preset semiconductor pillar are addressed, such that the preset bit line is in a sensing state and the bit line adjacent to the preset bit line is in a non-sensing state.

21. A memory, characterized in that, include: A memory cell array, comprising the semiconductor structure as described in any one of claims 12 to 20; as well as The peripheral circuitry is coupled to the memory cell array.

22. A storage system, characterized in that, include: At least one memory as described in claim 21; as well as A controller, coupled to the semiconductor structure, is used to control the memory to store data.

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