Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes: a first interlayer insulating layer on a substrate and including an upper surface at a first level; a second interlayer insulating layer on the first interlayer insulating layer and including a material having a density smaller than that of the first interlayer insulating layer; a first contact in the first interlayer insulating layer and having an upper surface at a second level higher than the first level; a through via in the first interlayer insulating layer and the substrate and having an upper surface at a third level higher than the second level; a first wiring in the second interlayer insulating layer, in contact with the first contact, and having a lower surface at a fourth level lower than the first level; and a second wiring in the second interlayer insulating layer, in contact with the through-via, and having a fifth level lower than the fourth level.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices are beneficial in the electronics industry due to their small size, multifunctionality and / or low manufacturing cost. However, with the significant development of the electronics industry, semiconductor devices are being highly integrated. The line width of the pattern of the semiconductor device is being reduced to achieve its high integration. New exposure techniques and / or expensive exposure techniques can be used for fine patterns to manufacture highly integrated semiconductor devices. Therefore, various studies have been conducted on new integration techniques. Summary of the invention

[0003] The inventive concept may provide a semiconductor device having improved reliability.

[0004] The inventive concept may provide a method of manufacturing a semiconductor device capable of improving yield.

[0005] A semiconductor device according to some embodiments of the inventive concept includes: a substrate; a first interlayer insulating layer on the substrate, wherein an upper surface of the first interlayer insulating layer is at a first distance from an upper surface of the substrate; a second interlayer insulating layer on the first interlayer insulating layer, wherein the second interlayer insulating layer is in direct contact with the first interlayer insulating layer; a first contact in the first interlayer insulating layer, wherein an upper surface of the first contact is at a second distance from an upper surface of the substrate, the second distance being farther from the upper surface of the substrate than the first distance; a through via in the first interlayer insulating layer and the substrate, wherein an upper surface of the through via is at a third distance from an upper surface of the substrate at a third distance farther from the upper surface of the substrate than the second distance; a first wiring in the second interlayer insulating layer, wherein the first wiring is in contact with the first contact, and the lower surface of the first wiring is at a fourth distance, and the fourth distance is closer to the upper surface of the substrate than the first distance; and a second wiring in the second interlayer insulating layer, wherein the second wiring is in contact with the through-via, and the lower surface of the second wiring is at a fifth distance, and the fifth distance is closer to the upper surface of the substrate than the fourth distance, wherein the first interlayer insulating layer includes a first material having a first density, wherein the second interlayer insulating layer includes a second material having a second density, and wherein the first density is greater than the second density.

[0006] A semiconductor device according to some embodiments of the inventive concept includes: a substrate; a first interlayer insulating layer on the substrate; a second interlayer insulating layer on the first interlayer insulating layer, wherein the second interlayer insulating layer is in direct contact with the first interlayer insulating layer; a first contact in the first interlayer insulating layer; a through-via in the first interlayer insulating layer and the substrate; a first wiring in the second interlayer insulating layer, wherein the first wiring is in contact with the first contact; a second wiring in the second interlayer insulating layer, wherein the second wiring is in contact with the through-via; a polishing stop pattern in contact with a side surface of the second wiring; and a cap pattern on the polishing stop pattern, wherein the cap pattern is in contact with a side surface of the second wiring, wherein an upper surface of the first interlayer insulating layer includes a protrusion extending away from an upper surface of the substrate and in contact with a lower surface of the polishing stop pattern, wherein the cap pattern and the polishing stop pattern are spaced apart from the first wiring, wherein the first interlayer insulating layer includes a first material having a first density, wherein the second interlayer insulating layer includes a second material having a second density, wherein the first density is greater than the second density.

[0007] A semiconductor device according to some embodiments of the inventive concept includes: a substrate including a cell array region, a peripheral circuit region, and a through-via region; a peripheral structure in the peripheral circuit region; a cell structure in the cell array region; a first interlayer insulating layer on the peripheral structure, the cell structure, and the through-via region; a second interlayer insulating layer on the first interlayer insulating layer, wherein the second interlayer insulating layer is in direct contact with the first interlayer insulating layer; a first contact in the first interlayer insulating layer, wherein the first contact is electrically connected to the peripheral structure; a through-via in the through-via region, wherein the through-via extends in the first interlayer insulating layer and the substrate; a first wiring in the second interlayer insulating layer, wherein the first wiring is in contact with the first contact contact; and a second wiring in a second interlayer insulating layer, wherein the second wiring is in contact with the through-via, wherein the peripheral structure includes: a peripheral transistor on or in the substrate; and a peripheral contact electrically connected to the peripheral transistor and between the substrate and the first contact, wherein the cell structure includes: a word line in the substrate; a storage node contact in contact with the substrate and on one side of the word line; a bit line contact in contact with the substrate and on the other side of the word line; a bit line on the bit line contact and overlapping with the word line; and a capacitor on the storage node contact, wherein the first interlayer insulating layer includes a first material having a first density, wherein the second interlayer insulating layer includes a second material having a second density, wherein the first density is greater than the second density.

[0008] A method for manufacturing a semiconductor device according to some embodiments of the inventive concept includes: forming a first interlayer insulating layer on a substrate; forming a first contact in the first interlayer insulating layer; forming a polishing stop layer on the first contact and the first interlayer insulating layer; forming a through via hole by etching the polishing stop layer, the first interlayer insulating layer and a portion of the substrate; forming a via insulating layer and a through via in the through via hole; forming a capping layer on the through via, the via insulating layer and the polishing stop layer; forming a mask pattern on the capping layer, wherein the mask pattern overlaps with the through via and the via insulating layer; forming a capping pattern and a polishing stop pattern, and exposing the first interlayer insulating layer by removing portions of the capping layer and the polishing stop layer exposed from the mask pattern; removing the mask pattern; forming a second interlayer insulating layer on the first interlayer insulating layer and the capping pattern; forming a first groove and a second groove by removing at least portions of the second interlayer insulating layer, the capping pattern and the polishing stop pattern, wherein the first groove exposes the first contact and the second groove exposes the through via; and forming a first wiring in the first groove and a second wiring in the second groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments described herein.

[0010] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept.

[0011] Figure 2A According to the embodiment of the invention Figure 1 An enlarged view of portion “P1”.

[0012] Figure 2B According to the embodiment of the invention Figure 2A A plan view of the third M1 wiring.

[0013] FIG. 3A to FIG. 3M The manufacturing method of the embodiment according to the inventive concept is shown in sequence. Figure 1 A cross-sectional view of a method for a semiconductor device.

[0014] FIG. 4A to FIG. 4D The manufacturing method of the embodiment according to the inventive concept is shown in sequence. Figure 1 A cross-sectional view of a method for a semiconductor device.

[0015] Figure 5A According to the embodiment of the invention Figure 1 The enlarged view corresponding to the portion “P1”.

[0016] Figure 5B yes Figure 5A A plan view of the third M1 wiring.

[0017] Fig. 6A According to the embodiment of the invention Figure 1 The enlarged view corresponding to the portion “P1”.

[0018] Figure 6B yes Fig. 6A A plan view of the third M1 wiring.

[0019] Figure 7 According to the embodiment of the invention Figure 1 The enlarged view corresponding to the portion “P1”.

[0020] Figure 8 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept.

[0021] Fig. 9 is a plan view of a semiconductor device according to an embodiment of the inventive concept.

[0022] Fig.10 According to the embodiment of the invention, Fig. 9 Cross-sectional views taken along lines R1-R1' and R2-R2'.

[0023] Fig.11 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0024] Hereinafter, in order to explain the inventive concept in detail, embodiments according to the inventive concept will be described with reference to the accompanying drawings.

[0025] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept. Figure 2A According to the embodiment of the invention Figure 1 An enlarged view of portion “P1”. Figure 2B According to the embodiment of the invention Figure 2A A plan view of the third M1 wiring.

[0026] Reference Figure 1 , Figure 2A and Figure 2B, a substrate 1 may be provided. The substrate 1 may include, for example, a semiconductor material. The substrate 1 may include, for example, a silicon single crystal substrate (layer) (for example, may be formed of a silicon single crystal substrate (layer)). The substrate 1 may include a peripheral circuit area PA and a through-via area VA. The substrate 1 may include a first surface 1a and a second surface 1b opposite to each other (along a vertical direction). For example, the first surface 1a of the substrate 1 may be an upper surface of the substrate 1, and the second surface 1b of the substrate 1 may be a lower surface of the substrate 1. The peripheral circuit structure PST may be arranged in the substrate 1 in the peripheral circuit area PA and / or on the first surface 1a of the substrate 1. The peripheral circuit structure PST may include a peripheral transistor and a peripheral wiring. The first interlayer insulating layer IL1 may be on the first surface 1a of the substrate 1 (for example, may cover the first surface 1a of the substrate 1 or overlap with the first surface 1a of the substrate 1). The first contact CT1 may be arranged in the first interlayer insulating layer IL1 and may be connected (for example, electrically connected) to the peripheral circuit structure PST. The first interlayer insulating layer IL1 may include, for example, silicon oxide (for example, SiO 2 ) (For example, silicon oxide (such as SiO 2) is formed). The through via TV and the via insulating layer VL may be in the first interlayer insulating layer IL1 and the substrate 1 (e.g., may extend in or penetrate the first interlayer insulating layer IL1 and the substrate 1). For example, the through via TV and the via insulating layer VL may extend in the first interlayer insulating layer IL1 and the substrate 1 in a vertical direction (e.g., penetrate the first interlayer insulating layer IL1 and the substrate 1). The via insulating layer VL may include, for example, silicon oxide (e.g., may be formed of, for example, silicon oxide). An air gap region may be provided in the via insulating layer VL. The via insulating layer VL may extend around the sidewalls of the through via TV (e.g., surround the sidewalls of the through via TV). The through via TV may include a first metal portion MP1 and a first diffusion barrier layer BM1. The first diffusion barrier layer BM1 may be interposed (in a horizontal direction) between the first metal portion MP1 and the via insulating layer VL. The first diffusion barrier layer BM1 may have a single layer or multilayer structure including, for example, titanium, titanium nitride, tantalum and / or tantalum nitride (e.g., formed of, for example, titanium, titanium nitride, tantalum and / or tantalum nitride). The first metal portion MP1 may include, for example, copper (e.g., may be formed of, for example, copper). It will be understood that when an element or layer is referred to as being "connected to" another element or layer, "contacting" another element or layer, or "connected to" another element or layer, it may be directly on the other element or layer, directly connected to the other element or layer, or directly connected to the other element or layer, or there may be one or more intervening elements or layers. In contrast, when an element is referred to as being "directly connected" to another element, "directly connected" to another element, "directly contacting" another element, "directly responding to" another element, or "directly on" another element, there is no intervening element. In addition, "electrically connected" conceptually includes physical connection and physical disconnection. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. Expressions such as "at least one of" when following a list of elements modify the entire list of elements, rather than the individual elements of the list. The horizontal direction may be parallel to the first surface 1a (e.g., the upper surface) of the substrate 1, and the vertical direction may be perpendicular to the first surface 1a (e.g., the upper surface) of the substrate 1. As used herein, "element A overlaps element B in direction X" (or similar language) means that there is at least one line that extends along direction X and intersects both elements A and B.

[0027] The second interlayer insulating layer IL2 may be disposed on the first interlayer insulating layer IL1. The second interlayer insulating layer IL2 may be in direct contact with the first interlayer insulating layer IL1. The density of the second interlayer insulating layer IL2 may be less than that of the first interlayer insulating layer IL1. For example, the second interlayer insulating layer IL2 may include a material having a density lower than that of the material (of the first interlayer insulating layer IL1) in the first interlayer insulating layer IL1 (for example, may be formed of the material). The mechanical strength of the second interlayer insulating layer IL2 may be lower than that of the first interlayer insulating layer IL1. For example, the material (of the second interlayer insulating layer IL2) in the second interlayer insulating layer IL2 may have a hardness lower than that of the material (of the first interlayer insulating layer IL1) in the first interlayer insulating layer IL1. The second interlayer insulating layer IL2 may include a low-k material having a dielectric constant smaller than that of silicon oxide (for example, may be formed of the low-k material). In some embodiments, the second interlayer insulating layer IL2 may include carbon, and the first interlayer insulating layer IL1 may exclude carbon. The first interlayer insulating layer IL1 may not include carbon. The second interlayer insulating layer IL2 may include (eg, may be formed of), for example, a porous insulating material and / or SiOCH.

[0028] The M1 wirings ML1a, ML1b, and ML1c may be disposed in the first interlayer insulating layer IL1 and / or the second interlayer insulating layer IL2. Each of the M1 wirings ML1a, ML1b, and ML1c may include a second metal portion MP2 and a second diffusion barrier layer BM2. The second diffusion barrier layer BM2 may have a single-layer or multi-layer structure including, for example, titanium, titanium nitride, tantalum, and / or tantalum nitride (e.g., formed of, for example, titanium, titanium nitride, tantalum, and / or tantalum nitride). The second metal portion MP2 may include, for example, copper (e.g., may be formed of, for example, copper). The second diffusion barrier layer BM2 may be on the side surface and the lower surface of the second metal portion MP2 (e.g., may cover the side surface and the lower surface of the second metal portion MP2 or overlap the side surface and the lower surface of the second metal portion MP2).

[0029] The M1 wirings ML1a, ML1b, and ML1c may include a first M1 wiring ML1a, a second M1 wiring ML1b, and a third M1 wiring ML1c. The first M1 wiring ML1a may be in contact with the first contact CT1. The second M1 wiring ML1b may be spaced apart from the first contact CT1 (and / or the through via TV) (in the horizontal direction) without being in contact with the first contact CT1 (and / or the through via TV). The third M1 wiring ML1c may be in contact with the through via TV.

[0030] Reference Figure 2A, each of the first M1 wiring ML1a and the second M1 wiring ML1b may have a first width WT1 (in the horizontal direction). The third M1 wiring ML1c may have a second width WT2 (in the horizontal direction) greater than the first width WT1. The upper surface of the first contact CT1 may have a first level LV1 (may be at the first level LV1). The upper surface of the first metal portion MP1 of the through via TV may have a second level LV2 (may be at the second level LV2) higher than the first level LV1. The upper surface of the first interlayer insulating layer IL1 may have a fourth level LV4 (may be at the fourth level LV4) lower than the first level LV1 and the second level LV2. The first M1 wiring ML1a may be on the upper surface and the upper side surface of the first contact CT1 (for example, may cover the upper surface and the upper side surface of the first contact CT1 or overlap with the upper surface and the upper side surface of the first contact CT1). The lower surface of the first M1 wiring ML1a may have a fifth level LV5 (may be at the fifth level LV5) lower than the fourth level LV4. The lower surface of the second M1 wiring ML1b may have a sixth level LV6 (may be at the sixth level LV6). The sixth level LV6 may be equal to the fifth level LV5 (e.g., may be coplanar with the fifth level LV5) or lower than the fifth level LV5. The third M1 wiring ML1c may be on the upper surface and the upper side surface of the first metal portion MP1 of the through-via TV (e.g., may cover the upper surface and the upper side surface of the first metal portion MP1 or overlap with the upper surface and the upper side surface of the first metal portion MP1). The lower surface of the third M1 wiring ML1c may have a seventh level LV7 lower than the sixth level LV6 (may be at the seventh level LV7). The third M1 wiring ML1c may have a pad shape. When viewed in a plan view, the upper surface of the third M1 wiring ML1c may have a Figure 2BCircular shape as shown. However, the inventive concept is not limited thereto, and the upper surface of the third M1 wiring ML1c may have a square shape, a rectangular shape or a line shape. As used herein, the term "horizontal" refers to the distance in the vertical direction from the upper surface (first surface 1a) of the substrate 1. For ease of description, spatial relationship terms such as "under ...", "under ...", "under ...", "above ...", "on ...", "higher" and the like may be used here to describe the relationship of an element or feature with another element or feature as shown in the figure. It will be understood that, in addition to the orientations depicted in the figure, the spatial relationship terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, the element described as "under" or "under" other elements or features will be oriented to "above" the other elements or features. Therefore, the term "under ..." can cover both upper and lower orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations) and the spatial relationship descriptors used here can be interpreted accordingly. For example, when the element A is said to be at a higher level than the element B, the element A may be disposed farther from the upper surface (first surface 1 a ) of the substrate 1 than the element B in the vertical direction.

[0031] In the inventive concept, the second interlayer insulating layer IL2 may be in direct contact with the first interlayer insulating layer IL1, and the silicon nitride (eg, Si 3 N 4 ) may not be interposed between the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2, thereby improving adhesion between the second interlayer insulating layer IL2 and the first insulating layer IL1. As a result, the reliability of the semiconductor device may be improved.

[0032] The dielectric constant of silicon nitride may be higher than the dielectric constant of silicon oxide. When a layer including silicon nitride (e.g., formed of silicon nitride) is interposed between the second interlayer insulating layer IL2 and the first interlayer insulating layer IL1, parasitic capacitance between the M1 wirings ML1a, ML1b, and ML1c may increase and insulation therebetween may decrease, and thus, the possibility of signal interference between the M1 wirings ML1a, ML1b, and ML1c may increase. However, in the inventive concept, the second interlayer insulating layer IL2 and the first interlayer insulating layer IL1 may be in direct contact with each other, and thus, signal interference between the M1 wirings ML1a, ML1b, and ML1c may be prevented / minimized / reduced, thereby improving the reliability of the semiconductor device.

[0033] The second capping layer CPL2 and the third interlayer insulating layer IL3 may be sequentially stacked on the second interlayer insulating layer IL2. The second capping layer CPL2 may include, for example, SiCN (eg, may be formed of, for example, SiCN). The dielectric constant of SiCN may be lower than that of silicon nitride (eg, Si3 N 4 ). The second cap layer CPL2 may prevent (interrupt) the metal (e.g., copper) in the second metal portion MP2 of the M1 wirings ML1a, ML1b, and ML1c (the metal (e.g., copper) constituting the second metal portion MP2 of the M1 wirings ML1a, ML1b, and ML1c) from dissolving / diffusion. The third interlayer insulating layer IL3 may include (e.g., may be formed of) the same material (e.g., SiOCH) as the second interlayer insulating layer IL2.

[0034] The M2 wiring ML2 may be in the third interlayer insulating layer IL3 and the second cap layer CPL2 (e.g., may extend in the third interlayer insulating layer IL3 and the second cap layer CPL2, or penetrate the third interlayer insulating layer IL3 and the second cap layer CPL2) and may contact at least a portion of the M1 wirings ML1a, ML1b, and ML1c, respectively. Each of the M2 wirings ML2 may include a third metal portion MP3 and a third diffusion barrier layer BM3. The M2 wiring ML2 may be formed as a dual damascene structure. For example, the third metal portion MP3 may include a via portion VP and a wiring portion LP. The third diffusion barrier layer BM3 may have a single-layer or multi-layer structure including, for example, titanium, titanium nitride, tantalum, and / or tantalum nitride (e.g., formed of, for example, titanium, titanium nitride, tantalum, and / or tantalum nitride). The third metal portion MP3 may include, for example, copper (e.g., may be formed of, for example, copper). The third diffusion barrier layer BM3 may be on the side surface and the lower surface of the third metal portion MP3 (e.g., may cover the side surface and the lower surface of the third metal portion MP3, or overlap the side surface and the lower surface of the third metal portion MP3). A plurality of M2 wirings ML2 may be disposed on the third M1 wiring ML1c having a relatively wide width WT2.

[0035] The third capping layer CPL3 and the fourth interlayer insulating layer IL4 may be sequentially stacked on the third interlayer insulating layer IL3. The third capping layer CPL3 may include, for example, SiCN (eg, may be formed of, for example, SiCN). The dielectric constant of SiCN may be lower than that of silicon nitride (eg, Si 3 N 4 ). The third cap layer CPL3 may prevent (interrupt) the metal (e.g., copper) in the third metal portion MP3 of the M2 wiring ML2 (the metal constituting the third metal portion MP3 of the M2 wiring ML2) from dissolving / diffusion. The fourth interlayer insulating layer IL4 may include the same material (e.g., SiOCH) as the second interlayer insulating layer IL2 (e.g., may be formed of the material (e.g., SiOCH)).

[0036] The M3 wiring ML3 may be in the fourth interlayer insulating layer IL4 and the third cap layer CPL3 (e.g., may extend in the fourth interlayer insulating layer IL4 and the third cap layer CPL3, or penetrate the fourth interlayer insulating layer IL4 and the third cap layer CPL3), and may contact some of the M2 wirings ML2, respectively. Each of the M3 wirings ML3 may include a fourth metal portion MP4 and a fourth diffusion barrier layer BM4. The M3 wiring ML3 may be formed as a dual damascene structure. For example, the fourth metal portion MP4 may include a via portion VP and a wiring portion LP. The fourth diffusion barrier layer BM4 may have a single-layer or multi-layer structure including, for example, titanium, titanium nitride, tantalum and / or tantalum nitride (e.g., formed of, for example, titanium, titanium nitride, tantalum and / or tantalum nitride). The fourth metal portion MP4 may include, for example, copper (e.g., may be formed of, for example, copper). The fourth diffusion barrier layer BM4 may be on (eg, may cover or overlap) side and lower surfaces of the fourth metal portion MP4 .

[0037] The fourth cap layer CPL4, the fifth interlayer insulating layer IL5 and the sixth interlayer insulating layer IL6 may be sequentially stacked on the fourth interlayer insulating layer IL4. The fourth cap layer CPL4 may include, for example, SiCN (e.g., may be formed of, for example, SiCN). Each of the fifth interlayer insulating layer IL5 and the sixth interlayer insulating layer IL6 may have a single-layer or multi-layer structure including, for example, silicon oxide, silicon nitride, silicon oxynitride and / or SiCN (e.g., formed of, for example, silicon oxide, silicon nitride, silicon oxynitride and / or SiCN). The sixth interlayer insulating layer IL6 may also be referred to as a passivation layer, a bonding layer or an interface layer.

[0038] The M4 wiring ML4 may be in the fifth interlayer insulating layer IL5 and the fourth cover layer CPL4 (for example, may extend in the fifth interlayer insulating layer IL5 and the fourth cover layer CPL4, or may penetrate the fifth interlayer insulating layer IL5 and the fourth cover layer CPL4), and may contact some of the M3 wiring ML3. The M4 wiring ML4 may also be named as a "via". The M4 wiring ML4 may include, for example, tungsten (for example, may be formed of, for example, tungsten). The M5 wiring ML5 and the upper bonding pad UBP may be set in the sixth interlayer insulating layer IL6. The M5 wiring ML5 may have a pad shape. The M5 wiring ML5 may include, for example, aluminum (for example, may be formed of, for example, aluminum). The upper bonding pad UBP may include, for example, copper (for example, may be formed of, for example, copper).

[0039] The passivation layer PL may be on the second surface 1b of the substrate 1. For example, at least a portion of the second surface 1b of the substrate 1 may be covered by the passivation layer PL (overlapping with the passivation layer PL). The passivation layer PL may have a single-layer or multi-layer structure including, for example, SiCN, silicon oxide, and / or silicon nitride (for example, formed of, for example, SiCN, silicon oxide, and / or silicon nitride). The lower bonding pad LBP may be disposed in the passivation layer PL. The lower bonding pad LBP may include, for example, copper (for example, may be formed of, for example, copper). The through-via TV may contact the lower bonding pad LBP.

[0040] FIG. 3A to FIG. 3M The manufacturing method of the embodiment according to the inventive concept is shown in sequence. Figure 1 A cross-sectional view of a method for a semiconductor device.

[0041] Reference Figure 3A , a substrate 1 having a first surface 1a and a second surface 1b opposite to each other (in a vertical direction) may be prepared. The substrate 1 may include a peripheral circuit area PA and a through-via area VA. The peripheral circuit structure PST may be formed in the substrate 1 and / or on the first surface 1a of the substrate 1 in the peripheral circuit area PA. The first interlayer insulating layer IL1 may be formed on the first surface 1a of the substrate 1 (e.g., may cover the first surface 1a of the substrate 1 or overlap the first surface 1a of the substrate 1). A contact hole may be formed in the first interlayer insulating layer IL1 and filled with a conductive layer, and then a full-surface anisotropic etching process and / or a polishing process may be performed to form a first contact CT1. Therefore, the upper surface of the first interlayer insulating layer IL1 and the upper surface of the first contact CT1 may have a first level LV1 (may be at the first level LV1).

[0042] Reference Figure 3B A polishing stop layer PSL may be formed on (an upper surface of) the first interlayer insulating layer IL1 and (an upper surface of) the first contact CT1. The polishing stop layer PSL may include (eg, may be formed of), for example, silicon nitride.

[0043] Reference Figure 3C, a first mask pattern MK1 may be formed on the polishing stop layer PSL. The first mask pattern MK1 may include (e.g., may be formed as) a photoresist pattern, for example. The first mask pattern MK1 may define a position in the through-via area VA where a through-via TV and a through-via insulating layer VL are to be formed. The first mask pattern MK1 may be used as an etching mask to remove (e.g., etch) a portion of the polishing stop layer PSL, a portion of the first interlayer insulating layer IL1, and a portion of the substrate 1 to form a through-via hole VH. In some embodiments, the through-via hole VH may extend in the polishing stop layer PSL and the first interlayer insulating layer IL1 (e.g., penetrate the polishing stop layer PSL and the first interlayer insulating layer IL1). The through-via hole VH may extend in at least a portion of the substrate 1.

[0044] Reference Figure 3D , the first mask pattern MK1 may be removed. The via insulating layer VL, the first diffusion barrier layer BM1, and the first metal layer (which will become the first metal portion MP1 after a subsequent process (e.g., a CMP process)) may be sequentially stacked on the polishing stop layer PSL to fill the through via hole VH, and then a chemical mechanical polishing (CMP) process may be performed. The via insulating layer VL and the through via TV may be formed in the through via hole VH, and the upper surface of the polishing stop layer PSL may be exposed. After the polishing process (e.g., a CMP process), the upper surface of the polishing stop layer PSL and the upper surface of the through via TV (e.g., the upper surface of the first metal portion MP1) may have a second level LV2 (may be at the second level LV2) that is higher than the first level LV1.

[0045] Reference Figure 3E , the first cap layer CPL1 may be formed on the polishing stop layer PSL and the through via TV (e.g., may cover the polishing stop layer PSL and the through via TV, or overlap with the polishing stop layer PSL and the through via TV). The first cap layer CPL1 may include, for example, silicon nitride and / or SiCN (e.g., may be formed of, for example, silicon nitride and / or SiCN). The first cap layer CPL1 may prevent (interrupt) the metal (e.g., copper) in the first metal portion MP1 of the through via TV (the metal (e.g., copper) constituting the first metal portion MP1 of the through via TV) from dissolving / diffusion. The upper surface of the first cap layer CPL1 may have a third level LV3 higher than the second level LV2 (may be at the third level LV3).

[0046] Reference Figure 3F, the second mask pattern MK2 may be formed on the first cap layer CPL1. The second mask pattern MK2 may include (e.g., may be formed as) a photoresist pattern. The second mask pattern MK2 may cover at least a portion of the through via TV and a portion of the first cap layer CPL1 adjacent to the through via TV (or overlap at least a portion of the through via TV and a portion of the first cap layer CPL1 adjacent to the through via TV).

[0047] Reference Figure 3G and Figure 3H , the first cap layer CPL1 and the polishing stop layer PSL exposed from and adjacent to the second mask pattern MK2 can be etched (in sequence) using the second mask pattern MK2 as an etching mask to expose the upper surface of the first interlayer insulating layer IL1 and form a cap pattern CPP and a polishing stop pattern PSP, respectively. For example, portions of the first cap layer CPL1 and the polishing stop layer PSL that are not covered by (not overlapping with) the second mask pattern MK2 can be removed (e.g., etched) to expose a portion of the upper surface of the first interlayer insulating layer IL1 and form a cap pattern CPP and a polishing stop pattern PSP, respectively. The polishing stop pattern PSP can be formed as a portion of the polishing stop layer PSL. The cap pattern CPP can be formed as a portion of the first cap layer CPL1. The sidewalls of the polishing stop pattern PSP and the sidewalls of the cap pattern CPP can be formed to be aligned with each other. The cap pattern CPP can be formed to have a third width WT3 (in the horizontal direction), such as Figure 3H In the etching process, a portion of the first interlayer insulating layer IL1 may also be etched so that the upper surface of the first interlayer insulating layer IL1 may be lowered (from the first level LV1) to the fourth level LV4. Therefore, the upper surface and a portion of the sidewall (eg, the upper sidewall) of the first contact CT1 may be exposed.

[0048] Reference Figure 3H , the second mask pattern MK2 may be removed to expose the upper surface of the capping pattern CPP.

[0049] Reference Fig. 3I , the second interlayer insulating layer IL2 may be formed on the first interlayer insulating layer IL1. In addition, the third mask pattern MK3 may be formed on the second interlayer insulating layer IL2. The third mask pattern MK3 may include Figure 1 The first opening OP1, the second opening OP2, and the third opening OP3 are formed at the positions of the M1 wirings ML1a, ML1b, and ML1c. The first opening OP1 and the second opening OP2 may be formed to have a first width WT1 (in the horizontal direction). The third opening OP3 may be formed to have a second width WT2 (in the horizontal direction). The second width WT2 may be greater than Figure 3HThe third width WT3 of the cover pattern CPP in φ is larger (wider).

[0050] In the inventive concept, the second interlayer insulating layer IL2 may be formed to directly contact the first interlayer insulating layer IL1, thereby improving adhesion between the second interlayer insulating layer IL2 and the first interlayer insulating layer IL1. As a result, process defects may be prevented (reduced) and yield may be improved.

[0051] Reference Figure 3J , the second interlayer insulating layer IL2 may be etched using the third mask pattern MK3 as an etching mask to form a first trench TC1, a second trench TC2, and a third trench TC3. In the etching process, a portion of the upper portion of the first interlayer insulating layer IL1 may also be removed. In addition, a portion (e.g., the upper portion) of the path insulating layer VL and a portion (e.g., the upper portion) of the first diffusion barrier layer BM1 may also be removed. The first trench TC1 and the second trench TC2 may be formed to have a first width WT1 (in the horizontal direction). The third trench TC3 may be formed to have a second width WT2 (in the horizontal direction). Due to the load effect, as the width of the trench (in the horizontal direction) is larger (wider), the depth of the trench (in the vertical direction) may be larger (deeper). The lower surface of the first trench TC1 may have a fifth level LV5 (may be at the fifth level LV5). The lower surface of the second trench TC2 may have a sixth level LV6 (may be at the sixth level LV6). The lower surface of the third trench TC3 may have a seventh level LV7 (may be at the seventh level LV7). The fifth level LV5 may be equal to or higher than the sixth level LV6. This is because the etchant may have difficulty approaching the lower surface of the first trench TC1 due to the influence of the first contact CT1 on the lower surface of the first trench TC1 (e.g., protruding from the lower surface of the first trench TC1). The seventh level LV7 may be lower than the sixth level LV6.

[0052] Reference Figure 3K , the third mask pattern MK3 may be removed. Then, the second diffusion barrier layer BM2 and the second metal layer (which will become the second metal portion MP2 after a subsequent process (e.g., a CMP process)) may be sequentially and conformally stacked on the entire surface of the second interlayer insulating layer IL2 to fill the first trench TC1, the second trench TC2, and the third trench TC3, and a polishing process (e.g., a CMP process) may be performed. As a result, while the first M1 wiring ML1a, the second M1 wiring ML1b, and the third M1 wiring ML1c are formed in the first trench TC1, the second trench TC2, and the third trench TC3, the upper surface of the second interlayer insulating layer IL2 may be exposed.

[0053] Reference Figure 3L, the second cap layer CPL2 and the third interlayer insulating layer IL3 may be sequentially stacked on the second interlayer insulating layer IL2. A dual damascene hole may be formed in the third interlayer insulating layer IL3 and the second cap layer CPL2. A third diffusion barrier layer BM3 and a third metal layer (which will become a third metal portion MP3 after a subsequent process (e.g., a CMP process)) may be sequentially and conformally stacked on the third interlayer insulating layer IL3 to fill the dual damascene hole, and a polishing process (e.g., a CMP process) may be performed to form the M2 wiring ML2.

[0054] Reference Figure 3M , the third cap layer CPL3, the fourth interlayer insulating layer IL4, the M3 wiring ML3, the fourth cap layer CPL4, the fifth interlayer insulating layer IL5, the M4 wiring ML4, the sixth interlayer insulating layer IL6, the M5 wiring ML5 and the upper bonding pad UBP can be connected with Figure 3L The same / similar method as described in the above is formed on the third interlayer insulating layer IL3. Then, referring to Figure 1 , a back grinding process may be performed on the second surface 1b of the substrate 1 to expose (a portion of) the through via TV. A passivation layer PL and a lower bonding pad LBP may be formed on the second surface 1b of the substrate 1. Thus, a Figure 1 semiconductor devices.

[0055] FIG. 4A to FIG. 4D The manufacturing method of the embodiment according to the inventive concept is shown in sequence. Figure 1 A cross-sectional view of a method for a semiconductor device. FIG. 4A to FIG. 4D The processes can correspond to FIG. 3F to FIG. 3I Craftsmanship. FIG. 3F to FIG. 3I The same reference numerals in the drawings respectively denote the same components unless otherwise explicitly stated, and their repeated descriptions may be omitted here.

[0056] Reference Figure 4A The second mask pattern MK2 may be formed in plural to be on not only the through via TV but also the first contact CT1 (eg, to cover not only the through via TV but also the first contact CT1 , or to overlap not only the through via TV but also the first contact CT1 ).

[0057] Reference Figure 4B, the first cap layer CPL1 and the polishing stop layer PSL exposed from and adjacent to the second mask pattern MK2 may be removed (in sequence) using the second mask pattern MK2 as an etching mask to expose a portion of the upper surface of the first interlayer insulating layer IL1 and to form a cap pattern CPP and a polishing stop pattern PSP, respectively. One of the cap patterns CPP may be on the through via TV (e.g., may cover the through via TV, or overlap the through via TV), and another of the cap patterns CPP may be on the first contact CT1 (e.g., may cover the first contact CT1, or overlap the first contact CT1). In the etching process, a portion of the first interlayer insulating layer IL1 may also be etched so that the upper surface of the first interlayer insulating layer IL1 may be lowered (from the first level LV1) to the fourth level LV4. The upper sidewall of the first contact CT1 may be covered by a portion of the first interlayer insulating layer IL1 (or overlap with a portion of the first interlayer insulating layer IL1). The cap pattern CPP may protect the through via TV and the first contact CT1 during the (subsequent) etching process.

[0058] Reference Figure 4B and Figure 4C , the cap pattern CPP may have a third width WT3 on the through via TV (in the horizontal direction). On the first contact CT1, the cap pattern CPP and the polish stop pattern PSP may each have a fourth width WT4 (in the horizontal direction). The second mask pattern MK2 may be removed to expose an upper surface of the cap pattern CPP.

[0059] Reference Figure 4D , a second interlayer insulating layer IL2 may be formed on the first interlayer insulating layer IL1. Then, a third mask pattern MK3 may be formed on the second interlayer insulating layer IL2. The third mask pattern MK3 may include Figure 1 The first opening OP1, the second opening OP2, and the third opening OP3 are formed at the positions of the M1 wirings ML1a, ML1b, and ML1c. The first opening OP1 and the second opening OP2 may be formed to have a first width WT1 (in the horizontal direction). The first width WT1 may be greater than the fourth width WT4 (in the horizontal direction). Figure 4C The third opening OP3 may be formed to have a second width WT2 (in the horizontal direction). The second width WT2 may be greater than Figure 3H Medium (or Figure 4C The third width WT3 of the cover pattern CPP in FIG. 2 is larger (wider).

[0060] Reference Figure 4D and Figure 3J, the second interlayer insulating layer IL2 may be etched using the third mask pattern MK3 as an etching mask to form the first trench TC1, the second trench TC2, and the third trench TC3. In this case, both the polishing stop pattern PSP and the cap pattern CPP may be removed. Subsequently, a reference Figures 3K to 3M Describe the process.

[0061] Figure 5A According to the embodiment of the invention Figure 1 The enlarged view corresponding to the portion “P1”. Figure 5B yes Figure 5A A plan view of the third M1 wiring (ML1c).

[0062] Reference Figure 5A and Figure 5B , the polishing stop pattern PSP and the cap pattern CPP may be disposed on one side (side surface) of the third M1 wiring ML1c (e.g., may be in contact with one side (side surface) of the third M1 wiring ML1c). The first interlayer insulating layer IL1 may include a protrusion IL1_P on one side (side surface) of the third M1 wiring ML1c (in contact with one side (side surface) of the third M1 wiring ML1c). For example, the upper surface of the first interlayer insulating layer IL1 may have the protrusion IL1_P extending away from the upper surface (e.g., the first surface 1a) of the substrate 1. For example, the first interlayer insulating layer IL1 may have an upper surface at different distances from the upper surface (e.g., the first surface 1a) of the substrate 1. In some embodiments, the upper surface of the protrusion IL1_P may be the uppermost surface of the first interlayer insulating layer IL1. For example, the upper surface of the protrusion IL1_P may be the upper surface of the first interlayer insulating layer IL1 farthest from the upper surface (e.g., the first surface 1a) of the substrate 1. The polishing stop pattern PSP and the capping pattern CPP may be sequentially stacked on the protrusion IL1_P. Side surfaces of the polishing stop pattern PSP, the capping pattern CPP, and the protrusion IL1_P may be aligned with each other and may contact the second interlayer insulating layer IL2. The polishing stop pattern PSP and the capping pattern CPP may be spaced apart from the first M1 wiring ML1a and the second M1 wiring ML1b by the second interlayer insulating layer IL2.

[0063] An upper surface of the protrusion IL1_P may have a first level LV1 (may be at the first level LV1). An upper surface of the polishing stop pattern PSP may have a second level LV2 (may be at the second level LV2) higher than the first level LV1. An upper surface of the cap pattern CPP may have a third level LV3 higher than the second level LV2. The polishing stop pattern PSP and the cap pattern CPP may include the same material, such as silicon nitride. Alternatively, the polishing stop pattern PSP and the cap pattern CPP may include different materials. In this case, the polishing stop pattern PSP may include, for example, silicon nitride (for example, may be formed of, for example, silicon nitride), and the cap pattern CPP may include, for example, SiCN (for example, may be formed of, for example, SiCN). According to one example, when viewed in a plan view, the polishing stop pattern PSP and the cap pattern CPP may have (may be) a "C" shape or a "C"-shaped (crescent) shape, such as Figure 5B Other structures can be compared with reference Figures 1 to 2A The structures described are the same / similar.

[0064] when Fig. 3I When the position of the third mask pattern MK3 is (partially) misaligned, it can be formed Figure 5A and Figure 5B As a result, Fig. 3I The polishing stop pattern PSP and the cap pattern CPP in the Figure 3J As shown, not all of them are removed, and some portions of the polish stop pattern PSP and the cap pattern CPP may remain, thereby forming Figure 5A and Figure 5B Other manufacturing processes may be the same / similar to the above processes.

[0065] Fig. 6A According to the embodiment of the invention Figure 1 The enlarged view corresponding to the portion “P1”. Figure 6B yes Fig. 6A A plan view of the third M1 wiring (ML1c).

[0066] Reference Fig. 6A and Figure 6B, the polishing stop pattern PSP and the cap pattern CPP may be disposed on both (e.g., opposite) sides (e.g., side surfaces) of the third M1 wiring ML1c (e.g., may be in contact with both (e.g., opposite) sides (e.g., side surfaces) of the third M1 wiring ML1c). The first interlayer insulating layer IL1 may include a protrusion IL1_P, and the protrusion IL1_P is on both (e.g., opposite) sides (e.g., side surfaces) of the third M1 wiring ML1c (e.g., in contact with both (e.g., opposite) sides (e.g., side surfaces) of the third M1 wiring ML1c). When viewed in a plan view, the polishing stop pattern PSP and the cap pattern CPP may have a ring or closed curve shape extending around the third M1 wiring ML1c (e.g., surrounding the third M1 wiring ML1c). Other structures may be the same as those described with reference to FIG. Figure 5A and Figure 5B The structures described are the same / similar.

[0067] when Fig. 3I The second width WT2 of the third opening OP3 of the third mask pattern MK3 is less than Figure 3H When the third width WT3 of the cap pattern CPP is formed Fig. 6A and Figure 6B Other manufacturing processes may be the same / similar to the above processes.

[0068] Figure 7 According to the embodiment of the invention Figure 1 The enlarged view corresponding to the portion “P1”.

[0069] Reference Figure 7 , a plurality of polishing stop patterns PSP and a plurality of cap patterns CPP may be provided. The polishing stop pattern PSP and the cap pattern CPP may be disposed on one side (e.g., side surface) of the first M1 wiring ML1a (e.g., may be in contact with one side (e.g., side surface) of the first M1 wiring ML1a). The polishing stop pattern PSP and the cap pattern CPP may be disposed on one side (e.g., side surface) of the third M1 wiring ML1c (e.g., may be in contact with one side (e.g., side surface) of the third M1 wiring ML1c). The first interlayer insulating layer IL1 may include a protrusion IL1_P in contact with the side surfaces of the first M1 wiring ML1a and the third M1 wiring ML1c. The polishing stop pattern PSP and the cap pattern CPP may be spaced apart from the second M1 wiring ML1b. The polishing stop pattern PSP and the cap pattern CPP may be on each protrusion IL1_P. Other structures may be the same as those described with reference to FIG. Figure 5A and Figure 5B The structures described are the same / similar.

[0070] when Figure 4D When the position of the third mask pattern MK3 is (partially) misaligned, it can be formed Figure 7In some embodiments, when Figure 4D The first width WT1 of the first opening OP1 is less than Figure 4C a fourth width WT4 of the cap pattern CPP on the first contact CT1 and / or Fig. 3I The second width WT2 of the third opening OP3 of the third mask pattern MK3 is less than Figure 3H When the third width WT3 of the cap pattern CPP is formed Figure 7 Other manufacturing processes may be the same / similar to the above processes.

[0071] Figure 8 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept.

[0072] Reference Figure 8 In the semiconductor device according to the present example, the wiring portions LP of the M2 wiring ML2 disposed on the third M1 wiring ML1c (for example, overlapping the third M1 wiring ML1c in the vertical direction) may be connected to each other. For example, the wiring portions LP of the M2 wiring ML2 overlapping the third M1 wiring ML1c in the vertical direction may be connected to each other to form an integrated structure with no visible boundary therebetween. In addition, the wiring portions LP of the M3 wiring ML3 disposed on the third M1 wiring ML1c (for example, overlapping the third M1 wiring ML1c in the vertical direction) may be connected to each other. For example, the wiring portions LP of the M3 wiring ML3 overlapping the third M1 wiring ML1c in the vertical direction may be connected to each other to form an integrated structure with no visible boundary therebetween. Other structures may be the same / similar to the above-described structures.

[0073] Fig. 9 is a plan view of a semiconductor device according to an embodiment of the inventive concept. Fig.10 According to the embodiment of the invention, Fig. 9 Cross-sectional views taken along lines R1-R1' and R2-R2'.

[0074] Reference Fig. 9 and Fig.10 , the substrate 1 may include a cell array region CA and a peripheral circuit region PA. Fig. 9 and Fig.10 As shown in FIG. 1 , the substrate 1 may further include Figure 1 The through-pass area VA. Figures 1 to 8The described structures may be disposed on (in) the through-via region VA. The cell structure CST may be disposed on (in) the cell array region CA, and the peripheral circuit structure PST may be disposed on (in) the peripheral circuit region PA. The first interlayer insulating layer IL1 may be on (e.g., may cover or overlap) the cell structure CST and the peripheral circuit structure PST.

[0075] The device isolation layer 303 may be disposed on (in) the substrate 1 to define a unit active portion ACTC and a peripheral active portion ACTP. Each unit active portion ACTC may have an isolated shape. When viewed in a plan view, each unit active portion ACTC may have a strip shape elongated in the first direction D1. The substrate 1 may include (for example, may be) a silicon single crystal substrate or an SOI substrate. The device isolation layer 303 may include, for example, an oxide liner, a nitride liner and / or a buried insulating layer. The unit active portions ACTC may be arranged parallel to each other in the first direction D1, and the end (portion) of one unit active portion ACTC (in the third direction D3) may be arranged adjacent to the center (portion) of another unit active portion ACTC (in the third direction D3) adjacent thereto.

[0076] The word line WL may cross (overlap) the cell active portion ACTC. The word line WL may be disposed in a groove formed in the device isolation layer 303 and the cell active portion ACTC. The word line WL may be parallel to (may extend in) a second direction D2 intersecting the first direction D1. At least a portion of the word line WL may be (recessed) in the substrate 1.

[0077] The first impurity region 305a may be disposed in each cell active region ACTC between a pair of (adjacent) word lines WL, and a pair of second impurity regions 305b may be disposed in two (e.g., opposite) edge regions of each cell active region ACTC. For example, the first impurity region 305a and the second impurity region 305b may be doped with N-type impurities. The first impurity region 305a may correspond to a common drain region, and the second impurity region 305b may correspond to a source region.

[0078] The first insulating layer 307 may be disposed on the substrate 1 in the cell array region CA. The first insulating layer 307 may include a single-layer or multi-layer structure including (eg, formed of) a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0079] The bit line BL may be disposed on the first insulating layer 307. The bit line BL may cross (overlap) the word line WL. Fig. 9 As shown, the bit line BL may be parallel to a third direction D3 intersecting the first direction D1 and the second direction D2 (may extend in the third direction D3). The bit line BL may include a cell polysilicon pattern 311a, a cell ohmic pattern 315a, and a cell metal-containing pattern 317a stacked in sequence. The cell polysilicon pattern 311a may include, for example, polysilicon doped with impurities. The cell ohmic pattern 315a may include, for example, a metal silicide (such as cobalt silicide) (for example, may be formed of, for example, a metal silicide (such as cobalt silicide)). The cell metal-containing pattern 317a may include, for example, a metal, such as aluminum, tungsten, and / or copper. The bit line cap pattern BLC may be disposed on the bit line BL. The bit line cap pattern BLC may include a first bit line cap pattern 319a and a second bit line cap pattern 331a stacked in sequence. The first bit line cap pattern 319a and the second bit line cap pattern 331a may include, for example, a silicon nitride layer (for example, may be formed of, for example, a silicon nitride layer).

[0080] The first bit line spacer 335 may be on the side wall of the bit line BL and the lower side wall of the bit line cap pattern BLC. For example, the side wall of the bit line BL and the lower side wall of the bit line cap pattern BLC may be covered by the first bit line spacer 335 (overlapping with the first bit line spacer 335). The second bit line spacer 336 may be on the upper side wall of the bit line cap pattern BLC. For example, the upper side wall of the bit line cap pattern BLC may be covered by the second bit line spacer 336 (overlapping with the second bit line spacer 336). The first bit line spacer 335 and the second bit line spacer 336 may each have a single-layer or multi-layer structure including, for example, a silicon nitride layer, a silicon oxide layer and / or a silicon oxynitride layer (for example, formed by, for example, a silicon nitride layer, a silicon oxide layer and / or a silicon oxynitride layer). The second bit line spacer 336 may include an air gap therein.

[0081] The first insulating layer 307 may be interposed between the bit line BL and the substrate 1 and between the first bit line spacer 335 and the substrate 1. Sidewalls of the first bit line spacer 335 may be aligned with sidewalls of the first insulating layer 307.

[0082] The bit line BL may be electrically connected to the first impurity region 305a through a bit line contact DC. The bit line contact DC may include, for example, polysilicon doped with impurities (e.g., may be formed of, for example, polysilicon doped with impurities). A recessed region 313 may be formed on the first impurity region 305a and on the device isolation layer 303 adjacent thereto. The bit line contact DC may be disposed in the recessed region 313. The space between the lower sidewall of the bit line contact DC and the inner wall of the recessed region 313 may be filled with a buried insulating pattern 316. The buried insulating pattern 316 may have a single-layer or multi-layer structure including, for example, a silicon nitride layer and / or a silicon oxide layer (e.g., formed of, for example, a silicon nitride layer and / or a silicon oxide layer).

[0083] The storage node contact BC may be disposed between a pair of adjacent bit lines BL. The storage node contacts BC may be spaced apart from each other. The storage node contacts BC may include, for example, polysilicon doped with impurities. When viewed in a plan view, the storage node contacts BC may have an island shape spaced apart from each other. The storage node contacts BC may extend in the first insulating layer 307 (e.g., may penetrate the first insulating layer 307) and may contact the second impurity region 305b.

[0084] The storage node ohmic layer 341a may be disposed on the storage node contact BC. The storage node ohmic layer 341a may include, for example, metal silicide. As a specific example, the storage node ohmic layer 341a may include (eg, may be) cobalt silicide.

[0085] The landing pad LP may be disposed on the storage node ohmic layer 341a. For example, the landing pad LP may include, for example, a metal-containing material such as tungsten, aluminum, and copper (for example, may be formed of, for example, a metal-containing material such as tungsten, aluminum, and copper). The upper portion of the landing pad LP may be on the upper surface of the bit line cap pattern BLC (for example, may cover the upper surface of the bit line cap pattern BLC, or overlap the upper surface of the bit line cap pattern BLC). The center (for example, the horizontal center) of the landing pad LP may be offset from the center (for example, the horizontal center) of the storage node contact BC in a direction opposite to the second direction D2. A portion of the bit line BL may vertically overlap the landing pad LP.

[0086] The adjacent (neighboring) landing pads LP may be separated by a landing pad separation pattern 347a. The landing pad separation pattern 347a may have a single-layer or multi-layer structure including (e.g., formed of) a silicon nitride layer, a silicon oxide layer, and / or a silicon carbon nitride layer, for example. The landing pad separation pattern 347a may extend into the second bit line capping pattern 331a and the second bit line spacer 336.

[0087] The etch stop layer EL may be disposed on the landing pad LP and the landing pad separation pattern 347a. The etch stop layer EL may include, for example, a silicon nitride layer. The lower electrode BE may extend in the etch stop layer EL (e.g., may penetrate the etch stop layer EL) and may contact the landing pad LP. Some of the upper side walls of the lower electrode BE may contact the support pattern SP. The dielectric layer DL may be on (the surface of) the lower electrode BE and the support pattern SP (e.g., may cover (the surface of) the lower electrode BE and the support pattern SP, or overlap (the surface of) the lower electrode BE and the support pattern SP). The upper electrode UE may be disposed on the dielectric layer DL. The lower electrode BE, the dielectric layer DL, and the upper electrode UE may form a capacitor CAP.

[0088] The first interlayer insulating layer IL1 may be stacked on the upper electrode UE. The second contact CT2 may extend in the first interlayer insulating layer IL1 (e.g., may penetrate the first interlayer insulating layer IL1) and may contact the upper electrode UE. The fourth M1 wiring ML1d may be disposed on the first interlayer insulating layer IL1 and may be connected (e.g., electrically connected) to the upper electrode UE through the second contact CT2.

[0089] The peripheral gate electrode 323b may be disposed on (in) the substrate 1 in the peripheral circuit region PA. The peripheral gate insulating pattern 309b may be interposed between the peripheral gate electrode 323b and the substrate 1. The peripheral gate capping pattern 319b may be disposed on the peripheral gate electrode 323b. The peripheral source / drain region 327 may be disposed in the substrate 1 on both (e.g., opposite) sides of the peripheral gate electrode 323b. The peripheral spacer 325 may be on (e.g., may cover both (e.g., opposite) sides (e.g., side surfaces) of the peripheral gate electrode 323b, or overlap both (e.g., opposite) sides (e.g., side surfaces) of the peripheral gate electrode 323b. The peripheral gate electrode 323b may include a peripheral polysilicon pattern 311b, a peripheral ohmic pattern 315b, and a peripheral metal-containing pattern 317b stacked in sequence. The second insulating layer 329 may be on (eg, may cover or overlap) the peripheral gate capping pattern 319 b and the peripheral spacer 325 . The third insulating layer 331 may be disposed on the second insulating layer 329 .

[0090] The peripheral conductive pattern 343bw may be disposed on the third insulating layer 331. The upper surface of the peripheral conductive pattern 343bw may be located at the same height (same distance) as the upper surface of the landing pad LP from the upper surface of the substrate 1. The first peripheral contact 343bc may extend in the third insulating layer 331 and the second insulating layer 329 (e.g., may penetrate the third insulating layer 331 and the second insulating layer 329) and be electrically connected to the peripheral source / drain region 327, respectively. The first peripheral contact 343bc may be integrally connected to the peripheral conductive pattern 343bw. The peripheral ohmic layer 341b may be interposed between the first peripheral contact 343bc and the peripheral source / drain region 327. The fourth insulating layer 347b may be interposed between the peripheral conductive patterns 343bw. The etching stop layer EL may be on the peripheral conductive pattern 343bw and the fourth insulating layer 347b (for example, may extend onto, cover, or overlap the peripheral conductive pattern 343bw and the fourth insulating layer 347b). In the peripheral circuit area PA, the first interlayer insulating layer IL1 may be on the etching stop layer EL (for example, may cover, or overlap the etching stop layer EL). The first contact CT1 may extend in the first interlayer insulating layer IL1 (for example, may penetrate the first interlayer insulating layer IL1) and may contact the peripheral conductive pattern 343bw. The first M1 wiring ML1a may be disposed on the first interlayer insulating layer IL1 and may contact the first contact CT1.

[0091] Fig.11 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0092] Reference Fig.11 , the semiconductor package according to the present example may be a high bandwidth memory (HBM) chip. Specifically, the semiconductor package according to the present example may include a first memory die ME1 to a fourth memory die ME4 stacked sequentially on a buffer die BD. The buffer die BD and each of the first memory die ME1 to the third memory die ME3 may include an upper bonding pad UBP, a lower bonding pad LBP, and a through via TV. The solder ball SB may be bonded to the lower bonding pad LBP of the buffer die BD. The first memory die ME1 to the fourth memory die ME4 may be the same memory chip and may have, for example, a DRAM structure. Each of the first memory die ME1 to the fourth memory die ME4 may have a reference Figures 1 to 10The structure described. The lower bonding pad LBP and the upper bonding pad UBP may face each other, respectively, and the adjacent (corresponding) lower bonding pad LBP and the upper bonding pad UBP may be bonded to each other using Cu-to-Cu bonding, so that the buffer die BD and the first memory die ME1 to the fourth memory die ME4 are connected to each other (e.g., electrically connected). Although not shown, a solder ball connecting (e.g., electrically connecting) the buffer die BD with the first memory die ME1 to the fourth memory die ME4 may be added.

[0093] Since the width (in the horizontal direction) of each of the first to fourth memory dies ME1 to ME4 may be smaller than the width (in the horizontal direction) of the buffer die BD, a portion of the upper surface of the buffer die BD may be exposed. The mold layer MD may be on the upper surface of the buffer die BD and (the exposed portion of) the side surfaces of the first to fourth memory dies ME1 to ME4 (e.g., may cover the upper surface of the buffer die BD and (the exposed portion of) the side surfaces of the first to fourth memory dies ME1 to ME4, or overlap with the upper surface of the buffer die BD and (the exposed portion of) the side surfaces of the first to fourth memory dies ME1 to ME4).

[0094] In a semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the inventive concept, the second interlayer insulating layer in which the M1 wiring is disposed may be in direct contact with the first interlayer insulating layer thereunder, and a layer formed of silicon nitride may not be interposed between the M1 wirings, thereby preventing / minimizing signal interference between the M1 wirings. In addition, the adhesion between the first interlayer insulating layer and the second interlayer insulating layer may be improved to improve the reliability of the semiconductor device and prevent process defects, thereby improving its yield.

[0095] Although the embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept are to be considered in all respects as illustrative and not restrictive, and the scope of the inventive concept is indicated by the appended claims. Figures 1 to 11 The embodiments of the present invention may be combined with each other.

[0096] This application claims the priority of Korean Patent Application No. 10-2023-0143177 filed in the Korean Intellectual Property Office on October 24, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: substrate; a first interlayer insulating layer on the substrate, wherein an upper surface of the first interlayer insulating layer is at a first distance from an upper surface of the substrate; a second interlayer insulating layer on the first interlayer insulating layer, wherein the second interlayer insulating layer is in direct contact with the first interlayer insulating layer; a first contact in the first interlayer insulating layer, wherein an upper surface of the first contact is at a second distance from the upper surface of the substrate, the second distance being farther from the upper surface of the substrate than the first distance; a through via in the first interlayer insulating layer and the substrate, wherein an upper surface of the through via is at a third distance from the upper surface of the substrate, the third distance being farther from the upper surface of the substrate than the second distance; a first wiring in the second interlayer insulating layer, wherein the first wiring is in contact with the first contact, a lower surface of the first wiring is at a fourth distance, the fourth distance being closer to the upper surface of the substrate than the first distance; and a second wiring in the second interlayer insulating layer, wherein the second wiring is in contact with the through via, a lower surface of the second wiring being at a fifth distance, the fifth distance being closer to the upper surface of the substrate than the fourth distance, wherein the first interlayer insulating layer comprises a first material having a first density, wherein the second interlayer insulating layer comprises a second material having a second density, and Wherein, the first density is greater than the second density.

2. The semiconductor device according to claim 1, wherein The first wiring has a first width in a first direction parallel to the upper surface of the substrate, wherein the second wiring has a second width in the first direction, and Wherein, the second width is greater than the first width.

3. The semiconductor device according to claim 2, further comprising: a third wiring in the second interlayer insulating layer, wherein the third wiring is spaced apart from the first wiring and the second wiring, wherein the third wiring has the first width in the first direction, wherein the lower surface of the third wiring is at a sixth distance, the sixth distance being the same distance as the fourth distance from the upper surface of the substrate or closer to the upper surface of the substrate than the fourth distance, and The sixth distance is farther from the upper surface of the substrate than the fifth distance.

4. The semiconductor device according to claim 1, wherein: The first interlayer insulating layer does not contain carbon, and Wherein, the second interlayer insulating layer includes carbon.

5. The semiconductor device according to claim 1, further comprising: a polish stop pattern in contact with a side surface of the second wiring; as well as a cap pattern on the polish stop pattern and in contact with the side surface of the second wiring, wherein the upper surface of the first interlayer insulating layer includes a protrusion extending away from the upper surface of the substrate and contacting a lower surface of the polishing stop pattern, and Wherein, the second interlayer insulating layer is on the side surface of the protrusion.

6. The semiconductor device according to claim 5, wherein: A side surface of the cap pattern is aligned with a side surface of the polish stop pattern.

7. The semiconductor device according to claim 5, wherein: Each of the cap pattern and the polish stop pattern is a “C” shape or a closed curve shape in a plan view.

8. The semiconductor device according to claim 5, wherein: The capping pattern and the polishing stop pattern are spaced apart from the first wiring.

9. The semiconductor device according to claim 5, wherein: an upper surface of the polish stop pattern is at the third distance, and The upper surface of the cover pattern is at a seventh distance, and the seventh distance is farther from the upper surface of the substrate than the third distance.

10. The semiconductor device according to claim 1, wherein The substrate includes a cell array region, a peripheral circuit region and a through-via region, wherein the first contact is in the peripheral circuit region, wherein the through passage is in the through passage region, Wherein, the semiconductor device further comprises: a peripheral structure in the peripheral circuit region, wherein the first interlayer insulating layer is on the peripheral structure; and A cell structure in the cell array region, wherein the first interlayer insulating layer is on the cell structure, Wherein, the peripheral structure includes: a peripheral transistor on or in the substrate; and a peripheral contact electrically connected to the peripheral transistor and between the substrate and the first contact; Wherein, the unit structure comprises: a word line in the substrate; A storage node contact in contact with the substrate and on one side of the word line; a bit line contact in contact with the substrate and on the other side of the word line; a bit line on the bit line contact, wherein the bit line overlaps the word line; and A capacitor is contacted on the storage node.

11. A semiconductor device comprising: substrate; a first interlayer insulating layer on the substrate; a second interlayer insulating layer on the first interlayer insulating layer, wherein the second interlayer insulating layer is in direct contact with the first interlayer insulating layer; a first contact in the first interlayer insulating layer; a through via in the first interlayer insulating layer and the substrate; a first wiring in the second interlayer insulating layer, wherein the first wiring is in contact with the first contact; a second wiring in the second interlayer insulating layer, wherein the second wiring is in contact with the through via; a polish stop pattern in contact with a side surface of the second wiring; and a cap pattern on the polish stop pattern, wherein the cap pattern is in contact with the side surface of the second wiring, wherein the upper surface of the first interlayer insulating layer includes a protrusion, the protrusion extending away from the upper surface of the substrate and contacting the lower surface of the polishing stop pattern, wherein the cap pattern and the polish stop pattern are spaced apart from the first wiring, wherein the first interlayer insulating layer comprises a first material having a first density, wherein the second interlayer insulating layer comprises a second material having a second density, and Wherein, the first density is greater than the second density.

12. The semiconductor device according to claim 11, wherein The second interlayer insulating layer is on a side surface of the protrusion.

13. The semiconductor device according to claim 11, wherein A side surface of the cap pattern is aligned with a side surface of the polish stop pattern.

14. The semiconductor device according to claim 11, wherein Each of the cap pattern and the polish stop pattern is a “C” shape or a closed curve shape in a plan view.

15. The semiconductor device according to claim 11, wherein The cap pattern and the polish stop pattern include the same material.

16. A semiconductor device comprising: A substrate including a cell array region, a peripheral circuit region and a through-via region; a peripheral structure in the peripheral circuit region; a cell structure in the cell array region; a first interlayer insulating layer on the peripheral structure, the cell structure and the through-via region; a second interlayer insulating layer on the first interlayer insulating layer, wherein the second interlayer insulating layer is in direct contact with the first interlayer insulating layer; a first contact in the first interlayer insulating layer, wherein the first contact is electrically connected to the peripheral structure; a through via in the through via region, wherein the through via extends in the first interlayer insulating layer and the substrate; a first wiring in the second interlayer insulating layer, wherein the first wiring is in contact with the first contact; and a second wiring in the second interlayer insulating layer, wherein the second wiring is in contact with the through via, Wherein, the peripheral structure includes: a peripheral transistor on or in the substrate; and a peripheral contact electrically connected to the peripheral transistor and between the substrate and the first contact, Wherein, the unit structure comprises: a word line in the substrate; A storage node contact in contact with the substrate and on one side of the word line; a bit line contact in contact with the substrate and on the other side of the word line; a bit line on the bit line contact and overlapping the word line; and A capacitor on the storage node contact, wherein the first interlayer insulating layer comprises a first material having a first density, wherein the second interlayer insulating layer comprises a second material having a second density, and Wherein, the first density is greater than the second density.

17. The semiconductor device according to claim 16, wherein: The upper surface of the first interlayer insulating layer is at a first distance from the upper surface of the substrate, wherein the upper surface of the first contact is at a second distance from the upper surface of the substrate, the second distance being farther from the upper surface of the substrate than the first distance, wherein the upper surface of the through-via is at a third distance from the upper surface of the substrate, the third distance being farther from the upper surface of the substrate than the second distance, wherein the lower surface of the first wiring is at a fourth distance from the upper surface of the substrate, the fourth distance being closer to the upper surface of the substrate than the first distance, and The lower surface of the second wiring is at a fifth distance from the upper surface of the substrate, and the fifth distance is closer to the upper surface of the substrate than the fourth distance.

18. The semiconductor device according to claim 16, wherein: The first interlayer insulating layer does not contain carbon, and Wherein, the second interlayer insulating layer includes carbon.

19. The semiconductor device according to claim 16, further comprising: a polish stop pattern in contact with a side surface of the second wiring; as well as a cap pattern on the polish stop pattern and in contact with the side surface of the second wiring, wherein an upper surface of the first interlayer insulating layer includes a protrusion extending away from an upper surface of the substrate and contacting a lower surface of the polishing stop pattern, and Wherein, the second interlayer insulating layer is on the side surface of the protrusion.

20. The semiconductor device according to claim 19, wherein The capping pattern and the polishing stop pattern are spaced apart from the first wiring.

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