Flash memory and inter-polysilicon dielectric layer thereof
By infiltrating nitride ions on the silicon nitride layer of the flash memory device to form an nitriding oxide layer, the problem of read ‘0’ operation failure caused by the dielectric layer defect between polysilicon is solved, and a higher dielectric constant and read stability are achieved.
Patent Information
- Application Number
- CN202510101145.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-04-25
AI Technical Summary
During the long-term use of existing flash memory devices, the inter-polysilicon dielectric layer between the control gate and the floating gate is prone to defects, resulting in electrons in the floating gate being sucked out and the ‘0’ state of the memory cell is failed to read.
By infiltrating nitride ions into the upper surface layer of the silicon nitride layer, an nitriding oxide layer is formed, and the dielectric constant of the dielectric layer between the polysilicon is increased, thereby preventing electrons from being attracted to the '0' operation from failing.
The dielectric constant of the dielectric layer between polysilicon is effectively improved, preventing electrons in the floating gate from being sucked out, and ensuring the effectiveness of the read ‘0’ operation of the flash memory device.
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Figure CN119893994A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a flash memory and an inter-polysilicon dielectric layer thereof. Background Art
[0002] Flash memory is a non-volatile memory that can program storage cells. The programming operation includes write operation and read operation. When performing a program write operation on a flash memory device, the source end channel hot carrier injection process of the storage cell can be used to make electrons flow into the floating gate of the storage cell, so that negative charges are stored in the floating gate, and the storage state of the storage cell is programmed to "0". After this operation, a read operation will be performed to read out the data written into the storage cell by the previous write operation.
[0003] However, for existing flash memory devices, if the control gate is pressurized for a long time, it is easy to cause defects in the polysilicon dielectric layer between the control gate and the floating gate. That is, the voltage applied to the control gate causes the free electrons in the floating gate to be sucked out and become less. The floating gate with fewer free electrons will cause the subsequent read "0" operation of the storage cell to fail, making it impossible to correctly read the previous write operation data of the storage cell. Summary of the invention
[0004] The present application provides a flash memory and an inter-polysilicon dielectric layer thereof, which can solve the problem of failure of a read "0" operation of a storage unit in the related art.
[0005] In order to solve the technical problem in the background technology, the first aspect of the present application provides a polysilicon inter-dielectric layer, the polysilicon inter-dielectric layer comprising:
[0006] A first silicon oxide layer, wherein the first oxide layer covers the floating gate polysilicon;
[0007] a silicon nitride layer, wherein the silicon nitride layer covers the first silicon oxide layer,
[0008] A dense oxide layer, the dense oxide layer covers the silicon nitride layer, and the dense oxide layer is infiltrated with nitrogen ions to form a nitrided oxide layer;
[0009] A second silicon oxide layer is provided, wherein the second silicon oxide layer covers the nitrided oxide layer, and the second silicon oxide layer is covered with control gate polysilicon.
[0010] Optionally, the thickness of the dense oxide layer is 10A to 30A.
[0011] Optionally, the concentration of nitrogen ions infiltrated into the upper surface of the dense oxide layer is 1.0*10E5 atoms / cm 3 To 1.0*10E6 atoms / cm3 A nitriding oxide layer is formed.
[0012] Optionally, the upper surface of the nitrided oxide layer forms a lattice repair layer.
[0013] Optionally, the lattice repair layer is formed by a PNA process.
[0014] Optionally, the nitrided oxide layer is infiltrated into the dense oxide layer by a DPN process with a dosage of 2*10E5 atoms / cm 2 of nitrogen ions.
[0015] Optionally, the dense oxide layer is formed by an ISSG process.
[0016] In order to solve the technical problem in the background technology, the second aspect of the present application provides a flash memory and an inter-polysilicon dielectric layer thereof, wherein the flash memory and the inter-polysilicon dielectric layer thereof include the inter-polysilicon dielectric layer as described in the first aspect of the present application.
[0017] The technical solution of the present application includes at least the following advantages: the present application forms a nitrided oxide layer by infiltrating nitrogen ions into the upper surface layer of the silicon nitride layer, that is, forming a nitrided oxide layer between the silicon nitride layer and the second silicon oxide layer to increase the dielectric constant of the inter-polysilicon dielectric layer, effectively suppressing the electrons in the floating gate polysilicon from being attracted out by the voltage applied to the control gate polysilicon, thereby avoiding the problem of flash memory reading 0 failure. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1 A schematic diagram of the structure of a dielectric layer between polysilicon layers provided in one embodiment of the present application is shown. DETAILED DESCRIPTION
[0020] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0021] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0022] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0023] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0024] Figure 1 The schematic diagram of the structure of the dielectric layer between polysilicon layers provided in one embodiment of the present application is shown. Figure 1 As can be seen in FIG. 1 , the inter-polysilicon dielectric layer includes: a first silicon oxide layer 110 , a silicon nitride layer 130 , a dense oxide layer, and a second silicon oxide layer 120 .
[0025] The first oxide layer 110 covers the floating gate polysilicon 100 .
[0026] The silicon nitride layer 130 covers the first silicon oxide layer.
[0027] The dense oxide layer covers the silicon nitride layer 130 , and nitrogen ions are infiltrated into the dense oxide layer to form a nitrided oxide layer 140 .
[0028] The second silicon oxide layer 120 covers the nitrided oxide layer 140 , and the second silicon oxide layer 120 is covered with a control gate polysilicon 200 .
[0029] The present application forms a nitrided oxide layer by infiltrating nitrogen ions into the upper surface layer of the silicon nitride layer, that is, forming a nitrided oxide layer between the silicon nitride layer and the second silicon oxide layer to increase the dielectric constant of the inter-polysilicon dielectric layer, effectively suppressing the electrons in the floating gate polysilicon from being attracted out by the voltage applied to the control gate polysilicon, and avoiding the problem of flash memory reading 0 failure.
[0030] Exemplarily, the thickness of the dense oxide layer is 10A to 30A. Preferably, the thickness of the dense oxide layer is 20A.
[0031] The concentration of nitrogen ions infiltrated into the upper surface of the dense oxide layer is 1.0*10E5 atoms / cm 3 To 1.0*10E6atoms / cm 3 A nitrided oxide layer 140 is formed.
[0032] In order to further improve the dielectric constant of the inter-polysilicon dielectric layer, a lattice repair layer is formed on the upper surface of the nitrided oxide layer 140. Exemplarily, the nitrided oxide layer 140 can be manufactured by the following process: first, a DPN (Decoupled Plasma Nitridation) process is used to implant a dose of 2*10E5 atoms / cm into the dense oxide layer. 2 The nitrogen ions form a nitrided oxide layer 140. The concentration of nitrogen ions in the nitrided oxide layer 140 is 1.0*10E5 atoms / cm 3 To 1.0*10E6 atoms / cm 3 .
[0033] Then, a PNA (Post Nitride Anneal) process is performed on the surface of the nitrided oxide layer 140 to form a lattice repair layer.
[0034] The dense oxide layer can be formed by an ISSG (In Situ Steam Generation) process.
[0035] The present application also provides a flash memory device, which includes Figure 1 The inter-polysilicon dielectric layer is shown. Nitrogen ions are infiltrated into the upper surface layer of the silicon nitride layer to form a nitrided oxide layer, that is, a nitrided oxide layer is formed between the silicon nitride layer and the second silicon oxide layer to increase the dielectric constant of the inter-polysilicon dielectric layer, effectively suppressing the electrons in the floating gate polysilicon from being attracted out by the voltage applied to the control gate polysilicon, and avoiding the problem of flash memory read 0 failure.
[0036] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A polysilicon inter-dielectric layer, characterized in that: The inter-polysilicon dielectric layer comprises: A first silicon oxide layer, wherein the first oxide layer covers the floating gate polysilicon; a silicon nitride layer, wherein the silicon nitride layer covers the first silicon oxide layer; A dense oxide layer, the dense oxide layer covers the silicon nitride layer, and the dense oxide layer is infiltrated with nitrogen ions to form a nitrided oxide layer; A second silicon oxide layer is provided, wherein the second silicon oxide layer covers the nitrided oxide layer, and the second silicon oxide layer is covered with control gate polysilicon.
2. The inter-polysilicon dielectric layer according to claim 1, wherein: The thickness of the dense oxide layer is 10A to 30A.
3. The inter-polysilicon dielectric layer according to claim 1, wherein: The concentration of nitrogen ions infiltrated into the upper surface of the dense oxide layer is 1.0*10E5 atoms / cm 3 To 1.0*10E6 atoms / cm 3 A nitriding oxide layer is formed.
4. The inter-polysilicon dielectric layer according to claim 1, wherein: The upper surface of the nitrided oxide layer forms a lattice repair layer.
5. The inter-polysilicon dielectric layer according to claim 4, characterized in that: The lattice repair layer is formed by a PNA process.
6. The inter-polysilicon dielectric layer according to claim 1, wherein: The nitrided oxide layer is implanted into the dense oxide layer by a DPN process with a dosage of 2*10E5 atoms / cm 2 of nitrogen ions.
7. The inter-polysilicon dielectric layer according to claim 1, wherein: The dense oxide layer is formed by an ISSG process.
8. A flash memory device, characterized in that: The flash memory device comprises the inter-polysilicon dielectric layer as claimed in any one of claims 1 to 7.