Methods for forming semiconductor structures

Abstract

In a method for forming a semiconductor structure, during the dry etching step of the first oxide layer on the surface of a first region in a substrate, polymer impurities are easily generated. Typically, these polymer impurities adhere to the sidewalls of the stacked gate structures on both sides of the first region, causing the thickness of the first oxide layer on the sidewalls of the stacked gate structures on both sides of the first region to be greater than the thickness of the first oxide layer on the surface of the first region. The cleaning process can remove the polymer impurities on the sidewalls of the stacked gate structures on both sides of the first region, so that the polymer impurities are less likely to obstruct the etching solution during wet etching. When the first oxide layer on the surface of the first region is removed by wet etching, the first oxide layer on the sidewalls of the stacked gate structures on both sides of the first region is also thinned, and a portion of the thickness is still retained after thinning, which is beneficial to the smooth progress of subsequent semiconductor processes, enabling the subsequently formed semiconductor structure to have high performance and reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Non-volatile memory (NVRAM) is a storage technology that retains data even after power loss, playing a vital role in modern technology and daily life. Its importance is reflected in the following aspects: Data persistence: NVRAM ensures data retention after power failure, preventing data loss and guaranteeing system reliability. High-speed read / write: NVRAMs such as flash memory provide fast data read and write speeds, improving device performance and responsiveness. Large-capacity storage: Modern NVRAMs can provide enormous storage capacity to meet the ever-increasing demand for data storage. Low power consumption: Compared to volatile memory, NVRAMs typically have lower power consumption, helping to extend battery life and reduce energy consumption. Programmability: Some NVRAMs (such as EEPROM and Flash) are programmable, allowing data modification and updates, providing flexibility and customizability.

[0003] Split-gate nonvolatile memory cells are known in the industry, where two distinct portions of the channel region are controlled by two different gates (a floating gate structure and a select gate). The memory cell also includes a control gate structure above the floating gate structure and an erase gate structure above the source region. Split-gate memory cells are advantageous because the operating voltage is relatively low, meaning that the onboard power supply can be smaller and more efficient. Split-gate memory cells are disadvantageous because the memory cell size is enlarged to accommodate two laterally shifted separate gates, thus controlling two separate portions of the channel region. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure and to optimize the electrical performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of stacked gate groups on the substrate, wherein the area between adjacent stacked gate groups is a first region, each stacked gate group includes at least two stacked gate structures, and the stacked gate structures are spaced apart in an extension direction perpendicular to the stacked gate structures; and the area between adjacent stacked gate structures in the same stacked gate group is a second region; forming a first oxide layer on the sidewalls and topwalls of the stacked gate structures, and on the first and second regions of the substrate; performing dry etching on the first oxide layer on the surface of the first region of the substrate to remove a portion of the first oxide layer; after the dry etching step, cleaning the surface of the first region of the substrate and the sidewalls of the stacked gate structures on both sides of the first region; after the cleaning step, using a wet etching process to remove the remaining first oxide layer on the surface of the first region of the substrate, while simultaneously thinning the first oxide layer on the sidewalls of the stacked gate structures on both sides of the first region while retaining a portion of its thickness.

[0006] Optionally, the gas used in the cleaning step is an oxygen-containing gas, which includes oxygen.

[0007] Optionally, the parameters of the cleaning step include: radio frequency power less than 100W and process time of 5 to 10 seconds.

[0008] Optionally, after the dry etching and before the cleaning step, the thickness of the remaining first oxide layer on the surface of the first region in the substrate is 200 to 400 angstroms.

[0009] Optionally, in the wet etching step, the thickness of the first oxide layer retained on the sidewalls of the stacked gate structure on both sides of the first region is 200 to 300 angstroms.

[0010] Optionally, the wet etching process parameters include: the etching solution includes hydrofluoric acid and ammonium fluoride.

[0011] Optionally, the first oxide layer is formed using a high-temperature oxidation process.

[0012] Optionally, the material of the first oxide layer includes silicon oxide.

[0013] Optionally, in the step of forming the first oxide layer on the stacked gate structure and the substrate, the thickness of the first oxide layer is 300 angstroms to 500 angstroms.

[0014] Optionally, the method for forming the semiconductor structure further includes: after forming the first oxide layer and before performing the dry etching, forming a shielding layer covering the stacked gate group and the second region, and exposing the first region; in the dry etching step, using the shielding layer as a mask to etch the first oxide layer on the surface of the first region in the substrate; in the cleaning step, using the shielding layer as a mask to clean the surface of the first region in the substrate and the sidewalls of the stacked gate structure on both sides of the first region; in the wet etching process, using the shielding layer as a mask to remove the remaining first oxide layer on the surface of the first region in the substrate; the method for forming the semiconductor structure further includes: after the wet etching process, removing the shielding layer.

[0015] Optionally, the first region is a low-voltage region and the second region is a high-voltage region; the semiconductor structure further includes: after the wet etching process, forming a second oxide layer on the stacked gate structure and the substrate exposed by the stacked gate structure, the second oxide layer being located on the surface of the first region in the substrate and on the remaining first oxide layer.

[0016] Optionally, in the step of forming the second oxide layer, the thickness of the second oxide layer is 15 to 25 angstroms.

[0017] Optionally, in the step of forming a plurality of stacked gate groups on the substrate, the stacked gate structure includes: a floating gate structure, an inter-gate dielectric layer located on the floating gate structure, and a control gate structure located on the inter-gate dielectric layer; the method of forming the semiconductor structure further includes: after forming the second oxide layer, forming an erase gate structure on the second oxide layer in the second region of the substrate, and forming a select gate on the second oxide layer in the first region of the substrate.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0019] In the semiconductor structure formation method provided by this invention, during the dry etching step of the first oxide layer on the surface of the first region in the substrate, polymer impurities are easily generated. These polymer impurities typically adhere to the sidewalls of the stacked gate structure on both sides of the first region. Combined with the anisotropic nature of dry etching and the protective effect of the polymer impurities, the thickness of the first oxide layer on the sidewalls of the stacked gate structure on both sides of the first region is greater than the thickness of the first oxide layer on the surface of the first region. The cleaning step can remove the polymer impurities from the sidewalls of the stacked gate structure on both sides of the first region, thus preventing polymer impurities from easily forming during wet etching. The etching solution is blocked, and while the etching solution contacts the first oxide layer on the surface of the first region, it can also contact the first oxide layer on the sidewalls of the stacked gate structure on both sides of the first region. However, because the thickness of the first oxide layer on the surface of the first region is less than the thickness of the first oxide layer on the stacked gate structure on both sides of the first region, under the isotropic characteristic of wet etching, when the remaining first oxide layer on the surface of the first region is removed by wet etching, the first oxide layer on the sidewalls of the stacked gate structure on both sides of the first region is thinned, but a part of the thickness can still be retained. This is conducive to the smooth progress of subsequent semiconductor processes, so that the semiconductor structure formed later has high performance and high reliability.

[0020] In an optional embodiment, the first region is a low-voltage region, and the second region is a high-voltage region. The semiconductor structure further includes: after the wet etching process, forming a second oxide layer on the stacked gate structure and the substrate exposed by the stacked gate structure, the second oxide layer being located on the surface of the first region in the substrate and on the remaining first oxide layer; the stacked gate structure includes: a floating gate structure, an inter-gate dielectric layer located on the floating gate structure, and a control gate structure located on the inter-gate dielectric layer; the method of forming the semiconductor structure further includes: after forming the second oxide layer, forming an erase gate structure on the second oxide layer in the second region of the substrate, and forming a select gate on the second oxide layer in the first region of the substrate. The semiconductor structure forming method provided by the embodiments of the present invention allows the erase gate structure in the second region and the substrate to be spaced between a first oxide layer and a second oxide layer, which can meet the high-voltage design requirements of the second region; allows the select gate and the substrate to have only a second oxide layer, which can meet the low-voltage design requirements of the first region; and allows the select gate and the floating gate structure to be spaced between a second oxide layer and a thinned first oxide layer, which allows the select gate to smoothly perform read and program operations on the floating gate structure, which is beneficial to improving the performance of the semiconductor structure. Attached Figure Description

[0021] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0022] Figures 7 to 15This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0023] As the background technology shows, the semiconductor structures currently formed still have performance issues. This paper analyzes the reasons for these performance issues using a semiconductor structure formation method as an example.

[0024] refer to Figures 1 to 6 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0025] like Figure 1 As shown, a substrate 1 is provided; a plurality of stacked gate groups 2 are formed on the substrate 1, and the area between adjacent stacked gate groups 2 is a first region I. Each stacked gate group 2 includes at least two stacked gate structures 20, and the stacked gate structures 20 are arranged at intervals in an extension direction perpendicular to the extension direction of the stacked gate structures 20. The area between adjacent stacked gate structures 20 in the same stacked gate group 2 is a second region II. The first region I is a low-voltage region, and the second region II is a high-voltage region.

[0026] In this embodiment, the stacked gate structure 20 includes: a floating gate structure 21, an inter-gate dielectric layer 22 located on the floating gate structure 21, and a control gate structure 23 located on the inter-gate dielectric layer 22.

[0027] like Figure 2 As shown, a first oxide layer 3 is formed on the sidewalls and top wall of the stacked gate structure 20, as well as on the first region I and the second region II of the substrate 1, forming a shielding layer 4 that covers the stacked gate group 2 and the second region II and exposes the first region I.

[0028] like Figure 3 As shown, the first oxide layer 3 on the surface of the first region I in the substrate 1 is subjected to dry etching.

[0029] Because the first oxide layer 3 on the surface of the first region I in the substrate 1 has been dry etched, the thickness of the first oxide layer 3 on the sidewalls of the stacked gate structure 20 on both sides of the first region I is greater than the thickness of the first oxide layer 3 on the surface of the first region I. This means that when the first oxide layer 3 of the first region I is removed by wet etching, a portion of the thickness of the first oxide layer 3 on the sidewalls of the stacked gate structure 20 on both sides of the first region I remains.

[0030] like Figure 4 As shown, the remaining first oxide layer 3 on the surface of the first region I in the substrate 1 is removed using a wet etching process.

[0031] like Figure 5As shown, after the wet etching process, the masking layer 4 is removed by an ashing process; after removing the masking layer 4, a second oxide layer 6 is formed on the stacked gate structure 20 and the substrate 1 exposed by the stacked gate structure 20. The second oxide layer 6 is located on the surface of the first region I in the substrate 1 and on the remaining first oxide layer 3.

[0032] like Figure 6 As shown, after the second oxide layer 6 is formed, an erase gate structure 7 is formed in the area enclosed by the second oxide layer 6 on the surface of the second region II of the substrate 1 and the second oxide layer 6 on the sidewall of the stacked gate structure 20, and a select gate 8 is formed on the second oxide layer 6 on the sidewall of the stacked gate structure 20 in the first region I of the substrate 1.

[0033] In the above method for forming a semiconductor structure, removing a portion of the first oxide layer 3 allows the etching gas to easily react with the shielding layer 4, generating polymer impurities 5 (such as...). Figure 3 As shown, the polymer impurities 5 adhere to the sidewalls of the stacked gate structure 20 on both sides of the first region I. Therefore, during the wet etching process to remove the remaining first oxide layer 3 on the surface of the first region I in the substrate 1, the polymer impurities 5 on the sidewalls of the stacked gate structure 20 on both sides of the first region I easily obstruct the etching solution. The first oxide layer 3 on the sidewalls of the stacked gate structure 20 cannot be thinned during the wet etching process. Consequently, in the final semiconductor structure, the sum of the second oxide layer 6 between the select gate 8 and the floating gate structure 21 and the remaining first oxide layer 3 is too large. Correspondingly, the resistance between the select gate 8 and the floating gate structure 21 is too large, causing the select gate 8 to be unable to smoothly read and program the floating gate structure 21 when the semiconductor structure is working, resulting in poor performance of the semiconductor structure.

[0034] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 7 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0036] refer to Figure 7 Provides a base of 100.

[0037] The substrate 100 provides the basis for the process operation of forming the semiconductor structure, which is a non-volatile memory device, specifically a discrete gate memory structure.

[0038] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate 100 may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate 100 may also be other types of substrate 100, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.

[0039] Continue to refer to Figure 7 Multiple stacked gate groups 300 are formed on the substrate 100. The area between adjacent stacked gate groups 300 is a first region I. Each stacked gate group 300 includes at least two stacked gate structures 200. The stacked gate structures 200 are arranged at intervals in an extension direction perpendicular to the stacked gate structures 200. The area between adjacent stacked gate structures 200 in the same stacked gate group 300 is a second region II.

[0040] The adjacent stacked gate groups 300 define the location of a first region I, a low-voltage region used to form a select gate and a drain. The select gate is used for memory cell access control, data transfer, and memory cell selection and erase operations, while the drain is used to connect to the bitline to realize data reading and writing of memory cells. The location of a second region II is defined between adjacent stacked gate structures 200 within the same stacked gate group 300. The second region II is a high-voltage region used for subsequent formation of the erase gate structure.

[0041] The stacked gate structure 200 plays a role in the read, write, and erase operations of the memory.

[0042] Specifically, in the step of forming a plurality of stacked gate groups 300 on the substrate 100, the stacked gate structure 200 includes: a floating gate structure 201, an inter-gate dielectric layer 202 located on the floating gate structure 201, and a control gate (CG) structure 203 located on the inter-gate dielectric layer 202.

[0043] The floating gate structure 201 is used as a unit structure for storing data and maintaining the data state in a memory. By storing or not storing electrons in the floating gate structure 201, the memory is in a state after storing or erasing information.

[0044] In this embodiment, the floating gate structure 201 is made of polycrystalline silicon. The floating gate structure 201 is doped with N-type ions. The N-type ions include one or more of phosphorus, arsenic, and antimony.

[0045] During the writing and erasing process, the N-type ions cause a large difference between the write threshold voltage and the erase threshold voltage of the floating gate structure 201. During the use of the memory, the fluctuation of the voltage applied across the floating gate structure 201 will not affect the normal writing or erasing operation of the floating gate structure 201.

[0046] The control gate structure 203 is used to connect to an external electrical source to control the longitudinal electric field of the floating gate structure 201. During a read operation, it reads the data stored in the floating gate structure 201. During a write operation, it controls the injection or movement of the electron flow in the floating gate structure 201 to change the charge state of the floating gate structure 201. During an erase operation, the control gate structure 203 and the erase gate work together to create an erase electric field.

[0047] The control gate structure 203 is used to inject electrons into or pull electrons out of the floating gate structure 201 during the process of writing or erasing data in the memory. When reading data from the memory, the on / off state of the channel region at the bottom of the floating gate structure 201 is controlled by applying a working voltage to the control gate structure 203 and utilizing the energized state of the floating gate structure 201.

[0048] In this embodiment, the control gate structure 203 is made of polycrystalline silicon.

[0049] It should be noted that the control gate structure 203 is doped with P-type ions, which makes the control gate structure 203 less prone to being in a depleted state, thereby making the control gate structure 203 in a conductive state.

[0050] The P-type ions include one or more of boron, gallium, and indium.

[0051] The inter-gate dielectric layer 202 is used to electrically isolate the floating gate structure 201 and the control gate structure 203.

[0052] In this embodiment, the inter-gate dielectric layer 202 is made of a dielectric material. Specifically, the material of the inter-gate dielectric layer 202 includes one or both of silicon oxide and silicon nitride. In this embodiment, the inter-gate dielectric layer 202 is a sandwich structure composed of silicon oxide, silicon nitride, and silicon oxide (ONO).

[0053] The semiconductor structure further includes a floating gate oxide layer 101, located between the substrate 100 and the stacked gate structure 200, for isolating the stacked gate structure 200 and the substrate 100.

[0054] In this embodiment, the floating gate dielectric layer 101 is made of a dielectric material, such as silicon oxide. In other embodiments, the floating gate dielectric layer may also be a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers.

[0055] It should be noted that the stacked gate structure 200 further includes a hard mask layer 204, located on top of the control gate structure 203.

[0056] The hard mask layer 204 is used to protect the control gate structure 203 on top of the stacked gate structure 200 from damage.

[0057] In this embodiment, the hard mask layer 204 is a silicon nitride-oxygen-nitride (NON) structure.

[0058] refer to Figure 8 A first oxide layer 102 is formed on the sidewalls and topwalls of the stacked gate structure 200, and on the first region I and the second region II of the substrate 100.

[0059] The first oxide layer 102 formed in this step prepares for subsequent dry and wet etching.

[0060] In this embodiment, the material of the first oxide layer 102 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the first oxide layer 102.

[0061] In this embodiment, the first oxide layer 102 is formed using a high-temperature oxidation process. The first oxide layer 102 formed by the high-temperature oxidation process has good thickness uniformity and density, thus providing good electrical isolation.

[0062] It should be noted that in the step of forming the first oxide layer 102 on the stacked gate structure 200 and the substrate 100, the first oxide layer 102 should not be too thick or too thin. In subsequent processes, the first oxide layer 102 on the surface of the first region I in the substrate 100 needs to be removed, and the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I needs to be thinned. If the first oxide layer 102 formed by the high-temperature oxidation process is too thick, it will take more time to remove the first oxide layer 102 on the surface of the first region I in the substrate 100, which is not conducive to shortening the semiconductor structure fabrication cycle. If the first oxide layer 102 formed by the high-temperature oxidation process is too thin, in subsequent processes, the first oxide layer 102 on the surface of the first region I in the substrate 100 will be removed too quickly, the top of the substrate will be exposed too early, and the material on the top of the substrate 100 will be easily damaged. This will result in a poor interface for the second oxide layer 104 to be formed on the surface of the first region I of the substrate 100, leading to poor formation quality of the second oxide layer 104. In this embodiment, in the step of forming the first oxide layer 102 on the stacked gate structure 200 and the substrate 100, the thickness of the first oxide layer 102 is 300 angstroms to 500 angstroms.

[0063] refer to Figure 9 and Figure 10 Dry etching is performed on the first oxide layer 102 on the surface of the first region I in the substrate 100 to remove a portion of the thickness of the first oxide layer 102.

[0064] The removal of a portion of the thickness of the first oxide layer 102 from the surface of the first region I of the substrate 100 prepares for the subsequent complete removal of the first oxide layer 102 from the surface of the first region I of the substrate 100. Furthermore, the reason why the first oxide layer 102 is not completely removed by dry etching is that the first oxide layer 102 on the sidewalls of the stacked gate structures 200 on both sides of the first region I needs to be thinned. If, in this step, the thickness of the first oxide layer 102 on the surface of the first region I of the substrate 100 is not reserved, the wet etching solution will directly contact the substrate 100 of the first region I when thinning the first oxide layer 102 on the sidewalls of the stacked gate structures 200 on both sides of the first region I. The top of the first region I in the substrate 100 is easily damaged, and a good interface cannot be provided for the subsequent formation of the second oxide layer 104.

[0065] Dry etching process has anisotropic etching characteristics, which can specifically etch the first oxide layer 102 on the surface of the first region I in the substrate 100. Moreover, dry etching process is easy to precisely control the amount of the first oxide layer 102 removed, and is not easy to etch through the first oxide layer 102 on the surface of the first region I in the substrate 100.

[0066] It should be noted that after dry etching of the first oxide layer 102 on the surface of the first region I in the substrate 100, the remaining thickness of the first oxide layer 102 in the first region I of the substrate 100 should not be too large or too small. After subsequent cleaning operations, a wet etching process will be used to remove the remaining first oxide layer 102 on the surface of the first region I in the substrate 100. Considering the need to reduce the damage of the wet etching solution to the first region I in the substrate 100, if the remaining thickness of the first oxide layer 102 in the first region I of the substrate 100 is too small after several etching operations, the first oxide layer 102 on the surface of the first region I in the substrate 100 will be removed too quickly, prematurely exposing the substrate 100 of the first region I to the etching solution. This would damage the top of the first region I in the substrate 100, preventing it from providing a good interface for the subsequent formation of the second oxide layer 104. After several etching processes, the remaining thickness of the first oxide layer 102 on the surface of the first region I in the substrate 100 is too large, requiring excessive time for wet etching. However, wet etching suffers from weak process controllability, potentially resulting in the etching of material on the top of the substrate 100, which is detrimental to improving the reliability of the semiconductor structure. In this embodiment, after dry etching, the thickness of the remaining first oxide layer 102 on the surface of the first region I in the substrate 100 is 200 to 400 angstroms.

[0067] It should be noted that during dry etching, the etching gas easily reacts with the shielding layer 103 to generate polymer impurities. These polymer impurities typically adhere to the sidewalls of the stacked gate structures 200 on both sides of the first region I. Considering the anisotropic nature of dry etching and the protective effect of the polymer impurities on the first oxide layer 102 on the sidewalls of the stacked gate structures 200, the thickness of the first oxide layer 102 on the sidewalls of the stacked gate structures 200 on both sides of the first region I is greater than the thickness of the first oxide layer 102 on the surface of the first region I.

[0068] It should be noted that the material of the first oxide layer 102 is a dielectric material, and the dry etching gas used includes fluorine-based gases.

[0069] In this embodiment, the method for forming the semiconductor structure further includes: after forming the first oxide layer 102 and before performing the dry etching, forming a shielding layer 103 that covers the stacked gate group 300 and the second region II and exposes the first region I. In the dry etching step, the first oxide layer 102 on the surface of the first region I in the substrate 100 is etched using the shielding layer 103 as a mask.

[0070] The shielding layer 103 is used to protect the top of the stacked gate structure 200, the first oxide layer 102 on the second region II in the substrate 100, and the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the second region II.

[0071] In this embodiment, the shielding layer 103 is made of a material that is easy to form and easy to remove, for example, the material of the shielding layer 103 is photoresist.

[0072] refer to Figure 11 After the dry etching step, the surface of the first region I in the substrate 100 and the sidewalls of the stacked gate structure 200 on both sides of the first region I are cleaned.

[0073] In the cleaning process provided by this embodiment of the invention, polymer impurities on the sidewalls of the stacked gate structure 200 on both sides of the first region I can be removed. Thus, during the wet etching process, polymer impurities are less likely to obstruct the etching solution. While the etching solution contacts the first oxide layer 102 on the surface of the first region I, it can also contact the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I. However, because the thickness of the first oxide layer 102 on the surface of the first region I is less than the thickness of the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I, under the isotropic characteristic of wet etching, when the first oxide layer 102 on the surface of the first region I is removed by wet etching, the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I is thinned, but a portion of the thickness can still be retained. This is beneficial to the smooth progress of subsequent semiconductor processes, enabling the subsequently formed semiconductor structure to have high performance and reliability.

[0074] In this embodiment, the gas used in the cleaning step is an oxygen-containing gas, which includes oxygen. At high temperatures, oxygen can react with polymer impurities on the sidewalls of the stacked grid structure 200 on both sides of the first region I to generate a gas that is easily discharged.

[0075] It should be noted that, in the cleaning step, the shielding layer 103 is used as a mask to clean the surface of the first region I in the substrate and the sidewalls of the stacked gate structure 200 on both sides of the first region I.

[0076] In this embodiment, the parameters of the cleaning step include: the radio frequency power is less than 100W, and the process time of the cleaning step is 5 to 10 seconds.

[0077] It should be noted that the RF power of the cleaning step should not be too high. If the RF power of the cleaning step is too high, the shielding layer 103 will be consumed quickly, which may damage the top of the stacked gate structure 200, the first oxide layer 102 on the second region II of the substrate, and the first oxide layer 102 on the sidewalls of the stacked gate structure on both sides of the second region II. Consequently, the material on the top of the stacked gate structure 200 and the substrate 100 in the second region II will also be damaged. In this embodiment, the RF power of the cleaning step is less than 100W.

[0078] It should be noted that the cleaning step's processing time should not be too long or too short. If the cleaning step's processing time is too long, the shielding layer 103 is easily consumed, which can damage the top of the stacked gate structure 200, the first oxide layer 102 on the second region II of the substrate, and the first oxide layer 102 on the sidewalls of the stacked gate structure on both sides of the second region II. Consequently, the material on top of the stacked gate structure 200 and the substrate 100 in the second region II will also be damaged. If the cleaning step's processing time is too short, polymer impurities on the sidewalls of the stacked gate structure 200 on both sides of the first region I will not be removed, and the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I will not be exposed. During subsequent wet etching, the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I will have difficulty contacting the wet etching solution, and the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I will not be easily thinned. In this embodiment, the cleaning step's processing time is 5 to 10 seconds.

[0079] refer to Figure 12 After the cleaning step, the remaining first oxide layer 102 on the surface of the first region I in the substrate 100 is removed by a wet etching process. At the same time, the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I is thinned, while retaining a portion of the thickness of the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I.

[0080] The first region I is a low-voltage region. Removing the remaining first oxide layer 102 on the surface of the first region I in the substrate 100 is to meet the low-voltage design requirements of the first region I. Thinning the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I is to reduce the thickness of the dielectric material subsequently formed between the select gate and the floating gate structure 201 in the first region.

[0081] In this embodiment, the wet etching process is isotropic etching, which is simple to operate and has low process cost.

[0082] It should be noted that, in the wet etching step, the first oxide layer 102 retained on the sidewalls of the stacked gate structure 200 on both sides of the first region I should not be too thick or too thin. If the retained first oxide layer 102 is too thick, after the second oxide layer 104 is formed subsequently, the sum of the thicknesses of the second oxide layer 104 between the selected gate and the floating gate structure 201 and the remaining first oxide layer 102 after dry etching will be too large. Consequently, the resistance between the selected gate and the floating gate structure 201 will be too large. Therefore, when the semiconductor structure is working, the selected gate cannot smoothly perform read and program operations on the floating gate structure 201, leading to semiconductor structure failure. If the retained first oxide layer 102 is too thin, electrons in the floating gate structure 201 may be lost, or when a high voltage is applied to the selected gate, electrons may easily enter the floating gate structure 201. These will all adversely affect the reading of information in the floating gate structure 201. In this embodiment, during the wet etching step, the thickness of the first oxide layer 102 retained on the sidewalls of the stacked gate structure 200 on both sides of the first region I is 200 to 300 angstroms.

[0083] In this embodiment, the wet etching process parameters include: the etching solution includes hydrofluoric acid and ammonium fluoride.

[0084] It should be noted that, in the wet etching process, the remaining first oxide layer 102 on the surface of the first region I in the substrate 100 is removed using the masking layer 103 as a mask. The method for forming the semiconductor structure further includes: removing the masking layer 103 after the wet etching process.

[0085] In this embodiment, the shielding layer 103 is removed using an ashing process.

[0086] refer to Figure 13 The semiconductor structure further includes: after the wet etching process, forming a second oxide layer 104 on the stacked gate structure 200 and the substrate 100 exposed by the stacked gate structure 200, the second oxide layer 104 being located on the surface of the first region I in the substrate 100 and on the remaining first oxide layer 102.

[0087] Subsequently, an erase gate structure is formed on the second oxide layer 104 of the second region II of the substrate 100, and a select gate is formed on the second oxide layer 104 of the first region I of the substrate 100. Therefore, in the second region II, the erase gate structure of the second region II and the substrate 100 are separated by the first oxide layer 102 and the second oxide layer 104, which is to meet the high voltage design requirements of the second region II; in the first region I, the select gate and the substrate 100 are separated only by the second oxide layer 104, which meets the low voltage design requirements of the first region I. In addition, the select gate and the floating gate structure 201 are isolated by the second oxide layer 104 and the thinned first oxide layer 102, so that the select gate can smoothly perform read and program operations on the floating gate structure 201, which is beneficial to improving the performance of the semiconductor structure.

[0088] In this embodiment, the material of the second oxide layer 104 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the second oxide layer 104.

[0089] In this embodiment, the second oxide layer 104 is formed using a high-temperature oxidation process. The second oxide layer 104 formed by the high-temperature oxidation process has good thickness uniformity and density, thus providing good electrical isolation.

[0090] It should be noted that in the step of forming the second oxide layer 104 on the stacked gate structure 200 and the substrate 100, the second oxide layer 104 should not be too thick or too thin. If the second oxide layer 104 is too thick, the resistance between the subsequently formed select gate and the substrate of the first region will be too high, resulting in a higher operating voltage required when the select gate is working. If the second oxide layer 104 is too thin, there is a risk of leakage between the select gate and the substrate of the second region, causing the semiconductor structure to malfunction. In this embodiment, in the step of forming the second oxide layer 104 on the stacked gate structure 200 and the substrate 100, the thickness of the second oxide layer 104 is 15 angstroms to 25 angstroms.

[0091] refer to Figure 14 and Figure 15 The method for forming the semiconductor structure further includes: after forming the second oxide layer 104, forming an erase gate (EG) 205 on the second oxide layer 104 in the second region II of the substrate 100, and forming a select gate (EG) 206 on the second oxide layer 104 in the first region I of the substrate 100.

[0092] The erase gate structure 205 is used to erase signals from the memory. By applying a high voltage to the erase gate structure 205, a potential difference is formed on the inter-gate dielectric layer 202 between the erase gate structure 205 and the floating gate structure 201 due to the coupling capacitance. This difference can pull electrons from the floating gate structure 201 to the erase gate structure 205 through tunneling. As electrons are pulled out of the floating gate structure 201, the potential of the floating gate structure 201 increases, and the potential difference between it and the erase gate structure 205 decreases, weakening the potential difference of the inter-gate dielectric layer 202. Finally, the electrons in the floating gate structure 201 are completely pulled out, realizing the erasure of signals from the memory.

[0093] The primary function of the select gate 206 is to perform write and read operations on specific memory cells, which typically consist of a floating gate structure 201, a control gate structure 203, and an erase gate structure 205. The presence of the select gate 206 also provides electrical isolation to the memory cells, ensuring that only the selected memory cells are affected by the operation. The select gate 206 also helps enhance the data protection and security of the memory; by controlling the voltage of the select gate 206, unauthorized access or unwanted operations can be prevented, thus improving data security.

[0094] In this embodiment, the erase gate structure 205 and the select gate 206 are formed in the same step.

[0095] In this embodiment, both the erase gate structure 205 and the select gate 206 are made of polysilicon.

[0096] Specifically, the steps of forming the erase gate structure 205 and the select gate 206 include: forming a gate material layer 207 (e.g., ...) on the stacked gate structure 200 and the substrate. Figure 14 As shown, the top of the gate material layer 207 is higher than the top of the stacked gate structure 200; a mask layer is formed on the gate material layer 207 directly above the stacked gate structure 200, and the gate material layer 207 is etched using the mask layer as a mask. The gate material layer 207 located on the second oxide layer 104 in the second region II of the substrate 100 serves as an erase gate structure, and the gate material layer 207 on the second oxide layer 104 in the first region I of the substrate 100 serves as a select gate 206.

[0097] In other embodiments, the steps of forming the erase gate structure and the select gate may further include: forming a gate material layer on the stacked gate structure and the substrate, wherein the top of the gate material layer is higher than the top of the stacked gate structure; performing maskless etching on the gate material layer, wherein the gate material layer of the second oxide layer located in the second region of the substrate serves as the erase gate structure, and the gate material layer on the second oxide layer in the first region of the substrate serves as the select gate.

[0098] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Multiple stacked gate groups are formed on the substrate. The area between adjacent stacked gate groups is a first region. Each stacked gate group includes at least two stacked gate structures, and the stacked gate structures are arranged at intervals in an extension direction perpendicular to the stacked gate structures. The area between adjacent stacked gate structures in the same stacked gate group is a second region. A first oxide layer is formed on the sidewalls and topwalls of the stacked gate structure, as well as on the first and second regions of the substrate; Dry etching is performed on the first oxide layer on the surface of the first region in the substrate to remove a portion of the thickness of the first oxide layer; After the dry etching step, the surface of the first region in the substrate and the sidewalls of the stacked gate structure on both sides of the first region are cleaned. After the cleaning step, a wet etching process is used to remove the remaining first oxide layer on the surface of the first region in the substrate. At the same time, the first oxide layer on the sidewalls of the stacked gate structure on both sides of the first region is thinned while retaining a portion of its thickness.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gas used in the cleaning step is an oxygen-containing gas, which includes oxygen.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The parameters for the cleaning step include: The RF power is less than 100W, and the process time is 5 to 10 seconds.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the dry etching and before the cleaning step, the thickness of the remaining first oxide layer on the surface of the first region of the substrate is 200 to 400 angstroms.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the wet etching step, the thickness of the first oxide layer retained on the sidewalls of the stacked gate structure on both sides of the first region is 200 to 300 angstroms.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for the wet etching include: the etching solution includes hydrofluoric acid and ammonium fluoride.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first oxide layer is formed using a high-temperature oxidation process.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first oxide layer includes silicon oxide.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a first oxide layer on the stacked gate structure and the substrate, the thickness of the first oxide layer is 300 angstroms to 500 angstroms.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after forming the first oxide layer and before performing the dry etching, forming a shielding layer that covers the stacked gate group and the second region and exposes the first region. In the dry etching step, the first oxide layer on the surface of the first region in the substrate is etched using the shielding layer as a mask; In the cleaning step, the shielding layer is used as a mask to clean the surface of the first region in the substrate and the sidewalls of the stacked gate structure on both sides of the first region. In the wet etching process, the remaining first oxide layer on the surface of the first region in the substrate is removed using the shielding layer as a mask. The method for forming the semiconductor structure further includes: removing the shielding layer after the wet etching process.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first region is a low-pressure region, and the second region is a high-pressure region; The semiconductor structure further includes: after the wet etching process, forming a second oxide layer on the stacked gate structure and the substrate exposed by the stacked gate structure, the second oxide layer being located on the surface of a first region in the substrate and on the remaining first oxide layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the second oxide layer, the thickness of the second oxide layer is 15 to 25 angstroms.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming multiple stacked gate groups on the substrate, the stacked gate structure includes: a floating gate structure, an inter-gate dielectric layer located on the floating gate structure, and a control gate structure located on the inter-gate dielectric layer; The method for forming the semiconductor structure further includes: after forming the second oxide layer, forming an erase gate structure on the second oxide layer in the second region of the substrate, and forming a select gate on the second oxide layer in the first region of the substrate.

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