Semiconductor device, method for manufacturing the same, and electronic apparatus

Abstract

The semiconductor device, a method for manufacturing the same, and an electronic device according to the present disclosure include: a P+ anode; a first N− buffer layer, with the P+ anode embedded in the first N− buffer layer; an N− drift layer located on a side of the first N− buffer layer away from the P+ anode; a P− layer, in contact with the N− drift layer on a side of the N− drift layer facing the first N− buffer layer, and the first N− buffer layer is embedded in the P− layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] In a bipolar power device, both holes and electrons participate in conduction during conduction, and the number of minority carriers in the drift layer is much higher than the background doping concentration. Therefore, the conductivity modulation effect will occur in the drift layer, greatly reducing the on-resistance of the drift layer. Therefore, bipolar power devices are widely used in application fields that require high voltage and large current. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and an electronic device, which can fabricate an N-type IGBT based on an N-type substrate, integrate a freewheeling diode inside the device, and reduce the turn-off loss of the device.

[0004] The embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and an electronic device, and the specific solutions are as follows:

[0005] On the one hand, embodiments of the present disclosure provide a semiconductor device, including:

[0006] A P+ anode;

[0007] A first N- buffer layer, the P+ anode being embedded in the first N- buffer layer;

[0008] An N- drift layer, located on a side of the first N- buffer layer away from the P+ anode;

[0009] A P- layer, contacting the N- drift layer on a side of the N- drift layer facing the first N- buffer layer, and the first N- buffer layer being embedded in the P- layer.

[0010] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, an N+ substrate, a second N- buffer layer, a P- well layer, and a P+ cathode are further included, and the N+ substrate, the second N- buffer layer, the P- layer, the N- drift layer, the P- well layer, and the P+ cathode are stacked in sequence, and the first N- buffer layer and the second N- buffer layer are spaced apart.

[0011] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, a trench is further included, the trench partially penetrates the P- layer on a side of the P- layer away from the N- drift layer; the first N- buffer layer is embedded in the P- layer at the trench, and the second N- buffer layer contacts the P- layer outside the trench.

[0012] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, an anode conductive layer is further included. The trench further penetrates through the N+ substrate and the second N- buffer layer. The anode conductive layer is in contact with the P+ anode at the trench and is spaced apart from the N+ substrate, the second N- buffer layer, and the P- layer.

[0013] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, an anode dielectric layer is further included. The anode dielectric layer fills the gap between the anode conductive layer and the N+ substrate, the second N- buffer layer, and the P- layer.

[0014] On the other hand, the embodiments of the present disclosure provide a method for manufacturing the above semiconductor device, including:

[0015] Sequentially forming a stacked P- layer and an N- drift layer;

[0016] Forming a trench that partially penetrates the P- layer on a side of the P- layer away from the N- drift layer;

[0017] Injecting N- type impurities into the P- layer at the trench to form a first N- buffer layer;

[0018] Injecting P- type impurities into the first N- buffer layer to form a P+ anode.

[0019] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, before sequentially forming the stacked P- layer and the N- drift layer, it further includes: forming a second N- buffer layer on the N+ substrate;

[0020] When forming the trench that partially penetrates the P- layer on a side of the P- layer away from the N- drift layer, it further includes: forming the trench that penetrates through the N+ substrate and the second N- buffer layer;

[0021] After injecting N- type impurities into the P- layer at the trench to form a first N- buffer layer and before injecting P- type impurities into the first N- buffer layer to form a P+ anode, it further includes: forming a first hard mask covering the sidewall of the trench and the N+ substrate;

[0022] After injecting P- type impurities into the first N- buffer layer to form a P+ anode, it further includes: removing the first hard mask.

[0023] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, forming a trench that penetrates through the N+ substrate and the second N- buffer layer and partially penetrates the P- layer specifically includes:

[0024] Under the protection of the second hard mask, a trench is formed that penetrates through the N+ substrate and the second N- buffer layer and partially penetrates through the P- layer;

[0025] When removing the first hard mask, it also includes: removing the second hard mask.

[0026] In some embodiments, in the above preparation method provided by the embodiments of the present disclosure, after removing the first hard mask and the second hard mask, it further includes:

[0027] Form an anodic dielectric layer covering the sidewall of the trench;

[0028] Form an anodic conductive layer that contacts the lower surface of the P+ anode, the surface of the anodic dielectric layer away from the sidewall of the trench, and the lower surface of the N+ substrate.

[0029] On the other hand, the embodiments of the present disclosure also provide an electronic device, including the above semiconductor device provided by the embodiments of the present disclosure.

[0030] The beneficial effects of the present disclosure are as follows:

[0031] The semiconductor device, its preparation method and the electronic device provided by the embodiments of the present disclosure include: a P+ anode; a first N- buffer layer, with the P+ anode embedded in the first N- buffer layer; an N- drift layer located on the side of the first N- buffer layer away from the P+ anode; a P- layer, contacting the N- drift layer on the side of the N- drift layer facing the first N- buffer layer, and the first N- buffer layer is embedded in the P- layer. The present disclosure introduces a P- layer on the side of the N- drift layer facing the first N- buffer layer. This P- layer can jointly serve as the device drift region with the N- drift layer. Therefore, part of the drift region of the present disclosure is borne by the P- layer, which is equivalent to introducing hetero-impurity doping in the drift region, reducing the equivalent doping concentration of the device drift region, facilitating the acceleration of the establishment speed of the electric field in the drift region when the device is turned off, and thus reducing the turn-off loss. Description of the Drawings

[0032] Figure 1 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure;

[0033] Figure 2 It is Figure 1 A schematic diagram of the current distribution when the semiconductor device shown is conducting forward;

[0034] Figure 3 It is Figure 1 A schematic diagram of the current distribution when the semiconductor device shown is conducting reversely;

[0035] Figure 4 It is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure;

[0036] Figure 5 Flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure;

[0037] Figure 6(a) is Figure 1 a schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0038] Figure 6(b) is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0039] Figure 6(c) is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0040] Figure 6(d) is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0041] Figure 6(e) is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0042] Figure 6(f) is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0043] Figure 6(g) is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0044] Figure 6(h) is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0045] Figure 6(i) is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0046] Figure 6(j) is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process. Detailed implementation manners

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure. Also, the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of known functions and known components are omitted.

[0048] Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in the specification and claims of this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. "Inner", "outer", "upper", "lower", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0049] Embodiments of the present disclosure provide a semiconductor device, which can be prepared based on semiconductor materials such as silicon, silicon carbide, gallium nitride, etc., through processes such as epitaxy and ion implantation. In some embodiments, as Figure 1 shown, the semiconductor device provided by the present disclosure may include:

[0050] A P+ anode 101, optionally, the P+ anode 101 is formed by an ion implantation process.

[0051] A first N-buffer layer 102, covering the upper surface and the side surface of the P+ anode 101, which is equivalent to the P+ anode 101 being embedded in the first N-buffer layer 102. In some embodiments, the first N-buffer layer 102 can be prepared by an ion implantation process.

[0052] An N-drift layer 103, located on the side of the first N-buffer layer 102 away from the P+ anode 101, and the N-drift layer 103 can be formed by an epitaxial growth process.

[0053] A P-layer 104, in contact with the N-drift layer 103 on the side of the N-drift layer 103 facing the first N-buffer layer 102, and the first N-buffer layer 102 is embedded in the P-layer 104. The P-layer 104 of the present disclosure can be formed by an epitaxial growth process.

[0054] In the above semiconductor device provided by the embodiments of the present disclosure, a P-layer 104 is introduced on the side of the N-drift layer 103 facing the first N-buffer layer 102. The P-layer 104 and the N-drift layer 103 can jointly serve as the device drift region. Therefore, part of the drift region of the present disclosure is borne by the P-layer 104, which is equivalent to introducing hetero-impurity doping in the drift region, resulting in a decrease in the equivalent doping concentration of the device drift region, which is beneficial to accelerating the establishment speed of the electric field in the drift region when the device is turned off, thereby reducing the turn-off loss.

[0055] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, as Figure 1As shown, it may further include an N+ substrate 105, a second N- buffer layer 106, a P-well layer 107, and a P+ cathode 108. The N+ substrate 105, the second N- buffer layer 106, the P- layer 104, the N- drift layer 103, the P-well layer 107, and the P+ cathode 108 are sequentially stacked, and the first N- buffer layer 102 and the second N- buffer layer 106 are spaced apart.

[0056] Conventional bipolar devices such as bipolar junction transistors IGBTs, thyristors GTOs, MOS-controlled thyristors MCTs, etc. do not have reverse conduction capabilities. However, in most applications, a freewheeling current for the reverse current is required. Therefore, an external antiparallel diode is often used to achieve freewheeling. If the freewheeling diode can be integrated inside the bipolar device, not only can the parasitic inductance and parasitic resistance of the connection leads be reduced, but also the device power density can be increased by saving the terminal area, the device performance can be improved, and the system volume can be reduced. In the present disclosure, by arranging the P- layer 104 to be stacked with the N+ substrate 105, the second N- buffer layer 106, the N- drift layer 103, the P-well layer 107, and the P+ cathode 108, a PNPN diode structure composed of the P+ cathode 108, the P-well layer 107, the N- drift layer 103, the P- layer 104, the second N- buffer layer 106, and the N+ substrate 105 is formed inside the device, so that a freewheeling diode is integrated in the device, and the freewheeling function can be realized.

[0057] In some embodiments, such as Figure 2 As shown, in the forward conduction mode, the cathode of the device is connected to zero potential and the anode of the device is connected to positive potential. When the gate voltage changes from zero potential or negative potential to positive potential, an electron channel is formed by the inversion of the surface of the P-well layer 107 under the gate dielectric layer 113. Since the PN junction between the P- layer 104 and the second N- buffer layer 106 is in a reverse bias state, the N+ substrate 105 will not conduct, while the PN junction between the P+ anode 101 and the first N- buffer layer 102 is in a forward bias state, and this PN junction between the P+ anode 101 and the first N- buffer layer 102 will gradually turn on. As the hole current increases, the PNPN diode composed of the P+ anode 101, the first N- buffer layer 102, the P- layer 104, and the N- drift layer 103 will turn on, and the device enters the bipolar conduction mode. Therefore, the presence of the N+ substrate 105 will not affect the normal forward conduction process of the device. As Figure 3 As shown, in the reverse conduction mode, the cathode of the device is connected to zero potential, the anode of the device is connected to negative potential, and the gate voltage is zero potential or negative potential. The PNPN diode structure composed of the P+ cathode 108, the P-well layer 107, the N- drift layer 103, the P- layer 104, the second N- buffer layer 106, and the N+ substrate 105 inside the device will conduct, thereby realizing the freewheeling function. In the present disclosure, the first N- buffer layer 102 and the second N- buffer layer 106 are spaced apart, which can avoid the mutual interference between the forward conduction current and the reverse conduction current.

[0058] In addition, due to the high defects of the SiC P-type substrate, the epitaxial wafer grown on the P-type substrate has a high defect density. As a result, the performance and reliability of the bipolar device prepared therefrom are poor. Moreover, due to the high defects of the P-type substrate, its resistivity is relatively large. A relatively thick P-type substrate will result in an additional on-resistance. If the overall thickness of the substrate is thinned, the mechanical strength of the substrate will be reduced, leading to an increased probability of fragmentation. Therefore, currently, bipolar power devices are usually fabricated based on N-type substrates. However, for devices fabricated based on N-type substrates, such as IGBT devices, they are usually P-type IGBTs, which have opposite electrode polarities to the currently common N-type IGBTs. The application circuit and the drive circuit are relatively complex and incompatible with the commonly used application circuits, affecting the application of the device. The present disclosure can form the first N-buffer layer 102 and the P+ anode 101 by ion implantation after grooving through the N+ substrate 105 and the second N-buffer layer 106 and reaching into the P-layer 104, thereby forming an N-type IGBT structure based on the N+ substrate 105. The process is simple, and a relatively thick N+ substrate 105 can be retained to keep the device with sufficient mechanical strength.

[0059] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, as Figure 1 shown, it may further include a trench T. The trench T partially penetrates the P-layer 104 on the side of the P-layer 104 away from the N-drift layer 103; the first N-buffer layer 102 is embedded in the P-layer 104 at the trench T, and the second N-buffer layer 106 contacts the P-layer 104 outside the trench T. Thus, the trench T is used to isolate the first N-buffer layer 102 from the second N-buffer layer 106, effectively avoiding the mutual interference between the forward conduction current and the reverse conduction current.

[0060] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, as Figure 1 shown, it may further include an anode conductive layer 109. The trench T also penetrates the N+ substrate 105 and the second N-buffer layer 106. The anode conductive layer 109 contacts the P+ anode 101 at the trench T and is spaced from the N+ substrate 105, the second N-buffer layer 106, and the P-layer 104. At the same time, the anode conductive layer 109 also covers the lower surface of the N+ substrate 105, so that the anode conductive layer 109 is insulated from the N+ substrate 105, the second N-buffer layer 106, and the P-layer 104, avoiding the mutual influence between the forward conduction current and the reverse conduction current of the device. In some embodiments, the gap between the anode conductive layer 109 and the N+ substrate 105, the second N-buffer layer 106, and the P-layer 104 can be filled with an anode dielectric layer 110, so that the sidewalls of the anode conductive layer 109 and the N+ substrate 105, the second N-buffer layer 106, and the P-layer 104 are separated by the anode dielectric layer 110, and the anode conductive layer 109 can be led out as the device anode.

[0061] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, as Figure 1 shown, it may further include an N+ cathode 111, a cathode conductive layer 112, a gate dielectric layer 113, a gate conductive layer 114, and an isolation dielectric layer 115. Among them, a plurality of P-well layers 107, a plurality of N+ cathodes 111, and a plurality of P+ cathodes 108 may be included in one cell. The N+ cathode 111 is embedded in the P-well layer 107, the P+ cathode 108 is embedded in the N+ cathode 111, and the lower surfaces of the P+ cathode 108 and the N+ cathode 111 are both in contact with the upper surface of the P-well layer 107. The lower surface of the cathode conductive layer 112 is simultaneously in contact with the upper surfaces of the N+ cathode 111 and the P+ cathode 108. The gate dielectric layer 113 is in contact with the upper surfaces of the P-well layer 107 and the N+ cathode 111. The gate conductive layer 114 is located on the upper surface of the gate dielectric layer 113. The upper surface and the side surfaces of the gate conductive layer 114 are in contact with the isolation dielectric layer 115. The upper surface and the side surfaces of the isolation dielectric layer 115 are in contact with the cathode conductive layer 112. The isolation dielectric layer 115 and the gate dielectric layer 113 completely wrap the gate conductive layer 114. The gate conductive layer 114 can be led out as a device gate, and the cathode conductive layer 112 can be led out as a device cathode.

[0062] In some embodiments, the P-well layer 107, the P+ cathode 108, the N+ cathode 111, and the cathode conductive layer 112 of the present disclosure may belong to the cathode region. The gate dielectric layer 113, the gate conductive layer 114, and the isolation dielectric layer 115 may belong to the gate region. The N-drift layer 103 and the P-layer 104 may belong to the drift region. The P+ anode 101, the first N-buffer layer 102, the N+ substrate 105, the second N-buffer layer 106, the anode conductive layer 109, and the anode dielectric layer 110 may belong to the anode region. Figure 1 It shows that one drift region, one cathode region, and one gate region are provided on one anode region. In some embodiments, multiple repeated drift regions, cathode regions, and gate regions may be provided on one anode region according to process capabilities and required device performance. As Figure 4 shown, two drift regions, two cathode regions, and two gate regions are provided on one anode region. Among them, the two drift regions are integrally provided. The P-well layers 107 on the adjacent sides of the two cathode regions are integrally provided, the P+ cathodes 108 are integrally provided, and the cathode conductive layer 112 is integrally provided. The two gate regions are spaced apart by the cathode conductive layer 112.

[0063] Based on the same inventive concept, embodiments of the present disclosure provide a method for manufacturing the above semiconductor device. Since the principle of solving problems by this manufacturing method is similar to that of the above semiconductor device, the implementation of the manufacturing method provided by the embodiments of the present disclosure can refer to the implementation of the above semiconductor device provided by the embodiments of the present disclosure, and repeated parts will not be elaborated.

[0064] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, as Figure 5 shown, the following steps may be included:

[0065] S501. Sequentially form a stacked P-layer and an N-drift layer;

[0066] S502. Form a trench that partially penetrates the P-layer on the side of the P-layer away from the N-drift layer;

[0067] S503. Inject N-type impurities into the P-layer at the trench to form a first N-buffer layer;

[0068] S504. Inject P-type impurities into the first N-buffer layer to form a P+ anode.

[0069] To better understand the above manufacturing method provided by the embodiments of the present disclosure, the following Figure 1 describes in detail the manufacturing process of the semiconductor device shown.

[0070] In some embodiments, Figure 1 the manufacturing process of the semiconductor device shown may include the following steps:

[0071] Step (1): As shown in FIG. 6(a), sequentially epitaxially grow a second N-buffer layer 106, a P-layer 104, and an N-drift layer 103 on an N+ substrate 105.

[0072] Step (2): As shown in FIG. 6(b), sequentially form a P-well layer 107, an N+ cathode 111, and a P+ cathode 108 on the surface of the N-drift layer 103 by using ion implantation technology.

[0073] Step (3): As shown in FIG. 6(c), form a second hard mask HM2 on the back of the N+ substrate 105, and then perform selective etching. Use dry etching to etch the N+ substrate 105, the second N-buffer layer 106, and the P-layer 104, and etch into the P-layer 104, so as to form a trench T that penetrates the N+ substrate 105, the second N-buffer layer 106, and partially penetrates the P-layer 104.

[0074] Step (4): As shown in FIG. 6(d), while maintaining the state of the second hard mask HM2, inject N-type impurities from the back of the N+ substrate 105 into the N-drift layer 103 at the trench T, so as to form a first N-buffer layer 102.

[0075] Step (5): As shown in FIG. 6(e), while maintaining the state of the second hard mask HM2, a first hard mask HM1 is regrown on the back side.

[0076] Step (6): As shown in FIG. 6(f), using a reactive ion ICP etching method, the first hard mask HM1 on the back side is etched until the first hard mask HM1 at the middle of the surface of the first N-buffer layer 102 is removed.

[0077] Step (7): As shown in FIG. 6(g), P-type impurities are implanted from the back side of the N+ substrate 105 into the first N-buffer layer 102 at the trench T to form a P+ anode 101. Subsequently, the second hard mask HM2 on the back side of the N+ substrate 105 and the first hard mask HM1 on the sidewalls of the trench T are stripped. Then, an annealing process is performed to activate the implanted ions and repair the lattice damage.

[0078] Step (8): As shown in FIG. 6(h), a gate dielectric layer 113, a gate conductive layer 114, an isolation dielectric layer 115, and a cathode conductive layer 112 are sequentially formed on the device surface.

[0079] Step (9): As shown in FIG. 6(i), an anode dielectric layer 110 is deposited on the back side of the device.

[0080] Step (10): As shown in FIG. 6(j), using a reactive ion ICP etching method on the back side of the device, the anode dielectric layer 110 in the middle regions of the lower surface of the N+ substrate 105 and the lower surface of the P+ anode 101 is etched away, leaving only the anode dielectric layer 110 on the sidewalls of the trench T.

[0081] Step (11): As Figure 1 shown, an anode conductive layer 109 is formed by filling on the back side of the device using a method such as sputtering.

[0082] Thus far, the fabrication of the Figure 1 shown semiconductor device is completed.

[0083] Based on the same inventive concept, the embodiments of the present disclosure provide an electronic device including the above semiconductor device provided by the embodiments of the present disclosure. Since the principle of the electronic device for solving problems is similar to that of the above semiconductor device for solving problems, therefore, the implementation of the electronic device provided by the embodiments of the present disclosure can refer to the implementation of the above semiconductor device provided by the embodiments of the present disclosure, and the repeated parts will not be elaborated.

[0084] In some embodiments, the above-mentioned electronic devices provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, in addition to semiconductor devices, the electronic devices provided by the present disclosure may also include other structures. For example, when the electronic device is a radar, it further includes structures such as a transmitter, an antenna, and a receiver; when the electronic device is a mixer, it may further include structures such as an input port and an output port.

[0085] As can be seen from the above, the present disclosure achieves the purpose of fabricating an N-type IGBT based on an N+ substrate, which can retain a relatively thick N+ substrate to keep the device with sufficient mechanical strength. The present disclosure also introduces a P- layer above the N+ substrate and the first N- buffer layer to form a PNPN diode structure composed of a P+ cathode, a P-type well layer, an N- drift layer, a P- layer, a second N- buffer layer, and an N+ substrate inside the device, thereby integrating a freewheeling diode inside the device to achieve the freewheeling function. Moreover, when the device conducts forward, the PNPN diode composed of a P+ anode, a first N- buffer layer, a P- layer, and an N- drift layer conducts, and the presence of the N+ substrate does not affect the normal forward conduction process of the device. In addition, since part of the drift region is borne by the P-type region, the equivalent doping concentration of the device drift region decreases, which is beneficial to accelerating the establishment of the drift region electric field during turn-off, thereby reducing the turn-off loss. In addition, based on the N+ substrate epitaxy, the defect density of the device epitaxial layer (including the first N- buffer layer, the P- layer, and the N- drift layer) can be made lower. Only grooves need to be dug on the back and the P+ anode and the first N- buffer layer are formed through an ion implantation process, and the process is relatively simple.

[0086] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0087] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.

Claims

1. A semiconductor device, characterized in that: include: P+ anode; a first N-buffer layer, wherein the P+ anode is embedded in the first N-buffer layer; An N-drift layer, located on a side of the first N-buffer layer away from the P+ anode; A P-layer, contacting the N-drift layer at a side of the N-drift layer facing the first N-buffer layer, and the first N-buffer layer is embedded in the P-layer; The invention also includes an N+ substrate, a second N-buffer layer, a P-well layer, a P+ cathode, a groove, an anode conductive layer and an anode dielectric layer. The N+ substrate, the second N-buffer layer, the P-layer, the N-drift layer, the P-well layer and the P+ cathode are stacked in sequence, the first N-buffer layer and the second N-buffer layer are spaced apart, and the groove extends into the P-layer at a side of the P-layer away from the N-drift layer; the first N-buffer layer is embedded in the P-layer at the groove, and the second N-buffer layer is in contact with the P-layer at the periphery of the groove; the groove also penetrates the N+ substrate and the second N-buffer layer, the anode conductive layer in the groove is in contact with the P+ anode and is spaced apart from the N+ substrate, the second N-buffer layer and the P-layer; the anode dielectric layer fills the gap between the anode conductive layer in the groove and the N+ substrate, the second N-buffer layer and the P-layer, and the anode conductive layer is in contact with the surface of the N+ substrate away from the second N-buffer layer.

2. A method for preparing a semiconductor device as claimed in claim 1, characterized in that: include: sequentially forming a stacked P-layer and an N-drift layer; forming a trench extending into the P-layer on a side of the P-layer away from the N-drift layer; Implanting N-type impurities into the P-layer at the trench to form a first N-buffer layer; P-type impurities are implanted into the first N-buffer layer to form a P+ anode.

3. The preparation method according to claim 2, characterized in that: Before sequentially forming the stacked P-layer and the N-drift layer, the method further includes: forming a second N-buffer layer on the N+ substrate; Forming a groove extending into the P-layer on a side of the P-layer away from the N-drift layer, specifically comprising: forming a groove to penetrate the N+ substrate, the second N-buffer layer and extend into the P-layer; After injecting N-type impurities into the P-layer at the trench to form a first N-buffer layer, and before injecting P-type impurities into the first N-buffer layer to form a P+ anode, the method further includes: forming a first hard mask covering the sidewalls of the trench and the N+ substrate; After implanting P-type impurities into the first N-buffer layer to form a P+ anode, the method further includes: removing the first hard mask.

4. The preparation method according to claim 3, characterized in that: Forming a trench to penetrate the N+ substrate, the second N-buffer layer and extend into the P-layer specifically includes: Under the protection of the second hard mask, forming a trench penetrating the N+ substrate and the second N-buffer layer and extending into the P-layer; While removing the first hard mask, the method further includes: removing the second hard mask.

5. The preparation method according to claim 4, characterized in that: After removing the first hard mask and the second hard mask, the method further includes: forming an anode dielectric layer covering the sidewalls of the trench; An anode conductive layer is formed to contact the lower surface of the P+ anode, the surface of the anode dielectric layer away from the trench sidewall, and the lower surface of the N+ substrate.

6. An electronic device, characterized in that: Comprising the semiconductor device as claimed in claim 1.

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