Transistor with improved self-heating effect and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and particularly relates to a transistor with an improved self-heating effect and a preparation method thereof, and the method specifically comprises the steps: selecting a silicon substrate, and preparing a beryllium oxide heat dissipation layer on the silicon substrate through atomic layer deposition; performing atomic layer deposition on the beryllium oxide heat dissipation layer to prepare an indium oxide channel layer; etching two ends of the indium oxide channel layer to obtain a channel region, wherein a middle non-etched region is a non-channel region; preparing a source electrode and a drain electrode on the channel region; preparing a hafnium oxide gate dielectric layer on the source and drain electrodes and the non-channel region through atomic layer deposition; preparing a top gate electrode on the hafnium oxide gate dielectric layer; and annealing in an oxygen atmosphere. And the beryllium oxide material with high thermal conductivity is introduced as the heat dissipation substrate, so that the stability of the device is improved, the device can normally work under higher working voltage or working current, and the reliability of the transistor is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a transistor with improved self-heating effect and a preparation method thereof. Background Art

[0002] In the past few decades, thin film transistors (TFTs) have been continuously developed, and their channel materials have changed several times. In 2004, the work of thin film transistors using indium gallium zinc oxide (IGZO), a ternary compound composed of gallium oxide (Ga2O3), indium oxide (In2O3) and zinc oxide (ZnO) as channel materials, was published in the journal Nature. Since then, research based on amorphous oxide semiconductors has developed rapidly. Among them, indium oxide (In2O3) is regarded as a potential channel material due to its low manufacturing thermal budget, high carrier mobility, high bandgap width, atomically smooth surface roughness and wafer-level scalability. It is suitable for the next generation of back-end (BEOL) compatible monolithic three-dimensional integration of transistors. Compared with the traditional magnetron sputtering film forming method, atomic layer deposition (ALD) has better conformality and thickness control. In2O3 transistors prepared by ALD can be used in gate-all-around structures (GAA) and ultra-thin channel thicknesses as low as 0.5nm (T ch ).

[0003] The device size of high-performance transistors is shrinking year by year according to the trend of "Moore's Law". While the power and integration of transistors are increasing, the power density is increasing geometrically, which has become a huge challenge on the road of device development. Oxide channel thin film transistors prepared by ALD have higher mobility and current, so they need more heat dissipation control. If the heat cannot be effectively dissipated, the temperature in the channel area will rise sharply, resulting in serious self-heating effect. Local high temperature will destroy the channel material and the dielectric layer, causing local crystallization of the channel material, thereby affecting the off-state characteristics, and causing premature breakdown of the dielectric layer, affecting the service life of the transistor. In addition, local high temperature will also damage the interface between the channel material and the dielectric layer, resulting in the generation of interface defects and device instability, which seriously damages the long-term reliability of the transistor. Common insulating substrates include silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), etc., and their thermal conductivities are 1.5, 23, and 40 W / m·K, respectively. The low thermal conductivity of the substrate seriously affects the heat dissipation efficiency of high-performance transistors. Substrates with higher thermal conductivity reported so far include silicon carbide, diamond, etc., but they all have difficulties in process compatibility or cost. Summary of the invention

[0004] In view of the defects of the prior art, the present invention provides a transistor with improved self-heating effect and a preparation method thereof, which solves the technical problems of the self-heating effect of high-performance indium oxide thin film transistors, resulting in the generation of interface defects and device instability.

[0005] According to a first aspect of the present invention, there is provided a method for preparing a transistor with improved self-heating effect, comprising the following steps: S1 selects a silicon substrate, and prepares a beryllium oxide heat dissipation layer on the silicon substrate by atomic layer deposition; S2: performing atomic layer deposition on the beryllium oxide heat dissipation layer to prepare an indium oxide channel layer; S3: etching the two ends of the indium oxide channel layer to obtain a channel region, and the unetched area in the middle is a non-channel region; S4: preparing source and drain electrodes on the channel region; S5: preparing a hafnium oxide gate dielectric layer on the source and drain electrodes and the non-channel region by atomic layer deposition; S6: preparing a top gate electrode on the hafnium oxide gate dielectric layer; S7 annealing the composite layer obtained in step S6 in an oxygen atmosphere.

[0006] Preferably, in step S1, the substrate is pre-treated, and the pre-treatment specifically comprises placing the substrate in a mixed solution of ammonia water and hydrogen peroxide, heating it, and then washing it with deionized water.

[0007] Preferably, step S1 specifically includes placing the silicon substrate into a reaction chamber of an atomic layer deposition device, and then introducing precursors diethylberyllium and ozone to react at a reaction temperature of 250-300° C. to obtain a beryllium oxide heat dissipation layer.

[0008] Preferably, step S2 is specifically to place the composite layer obtained in step S1 into a reaction chamber of an atomic layer deposition device, and then introduce precursors trimethylindium and water respectively for reaction, and the reaction temperature is 200-225°C.

[0009] Preferably, the etching in step S3 is wet etching, and the etching solution is selected from a solution of hydrochloric acid, sulfuric acid, or nitric acid, and the concentration of the etching solution is 0.1-1 mol / L.

[0010] Preferably, step S5 is specifically to place the composite layer obtained in step S4 into a reaction chamber of an atomic layer deposition device, and then introduce precursors tetra(methylethylamine)hafnium and ozone respectively, and the reaction temperature is 250-300°C.

[0011] Preferably, in step S7, the annealing method is rapid thermal annealing, the annealing temperature is 250-300° C., the annealing atmosphere is oxygen, and the annealing time is 1-10 min.

[0012] According to another aspect of the present invention, a transistor prepared by the method for preparing a transistor with improved self-heating effect is provided, which comprises, from bottom to top, a silicon substrate, a beryllium oxide heat dissipation layer, and an indium oxide channel layer, wherein source and drain electrodes are arranged at intervals at both ends of the indium oxide channel layer, the source and drain electrodes and the top of the indium oxide channel layer are covered with a hafnium oxide gate dielectric layer, and the top of the hafnium oxide gate dielectric layer is covered with a top gate electrode.

[0013] Preferably, the beryllium oxide heat dissipation layer has a thickness of 10-20 nm; the indium oxide channel layer has a thickness of 2-4 nm; and the hafnium oxide gate dielectric layer has a thickness of 5-10 nm.

[0014] In general, the above technical solution conceived by the present invention has the following technical advantages compared with the prior art: (1) The present invention adopts a high thermal conductivity beryllium oxide heat dissipation substrate, and obtains a thin film by atomic layer deposition on a silicon substrate, which effectively solves the self-heating effect of indium oxide top-gate thin film transistors. The thermal conductivity of beryllium oxide is 300~400 W / m·K, which is an order of magnitude higher than that of common insulating substrates, and it only needs to be prepared by atomic layer deposition on any substrate. Since high thermal conductivity material beryllium oxide is introduced as a heat dissipation substrate, the heat generated in the channel region of the device when operating at high voltage or high current is quickly dissipated to the silicon substrate after passing through the beryllium oxide layer, thereby reducing the temperature and improving the stability of the device. The device can work normally at a higher operating voltage or current, thereby improving the reliability of the transistor.

[0015] (2) The present invention adopts a top-gate transistor. Compared with a back-gate device structure, a top-gate transistor can use hafnium oxide with a higher dielectric constant as a gate dielectric. While maintaining a high gate capacitance and electrostatic control capability, the influence of the self-heating effect can be reduced by replacing the heat dissipation substrate. In addition, the top-gate structure has the advantage of being compatible with mature complementary metal oxide semiconductor (CMOS) technology while maintaining high performance, laying the foundation for future applications in three-dimensional integration.

[0016] (3) The present invention prepares the beryllium oxide heat dissipation layer by atomic deposition, and uses ozone as an oxygen source to reduce the hydrogen content of the beryllium oxide layer and avoid doping of the indium oxide channel layer; the hafnium oxide gate dielectric layer is prepared by atomic layer deposition, and uses ozone as an oxygen source, which can avoid the reduction of oxygen atoms and the increase of oxygen vacancies in the indium oxide channel region caused by the deposition and oxidation of the hafnium source.

[0017] (4) The rapid thermal annealing used in the present invention can repair the interface defects between the channel layer and the gate dielectric layer, and the oxygen annealing can fill the oxygen vacancies in the indium oxide channel to improve the off-state characteristics. The shorter annealing time will not significantly increase the contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The figure is a schematic diagram of the structure of a transistor with improved self-heating effect according to the present invention.

[0019] Figure 2 1 and 2 are high-field output current curves of the transistors of Example 1 and Comparative Example 1.

[0020] In the figure, 1, silicon substrate; 2, beryllium oxide heat dissipation layer; 3, indium oxide channel layer; 4, source and drain electrodes; 5, hafnium oxide gate dielectric layer, 6, top gate electrode. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0022] The present invention provides a method for preparing a transistor with improved self-heating effect, comprising the following steps: S1 selects a silicon substrate, and prepares a beryllium oxide heat dissipation layer on the silicon substrate by atomic layer deposition; S2: performing atomic layer deposition on the beryllium oxide heat dissipation layer to prepare an indium oxide channel layer; S3: etching the two ends of the indium oxide channel layer to obtain a channel region, and the unetched area in the middle is a non-channel region; S4: preparing source and drain electrodes on the channel region; S5: preparing a hafnium oxide gate dielectric layer on the source and drain electrodes and the non-channel region by atomic layer deposition; S6: preparing a top gate electrode on the hafnium oxide gate dielectric layer; S7 annealing the composite layer obtained in step S6 in an oxygen atmosphere.

[0023] In some embodiments, in step S1, the substrate is pre-treated, and the pre-treatment specifically includes placing the substrate in a mixed solution of ammonia water and hydrogen peroxide and heating it, and then washing it with deionized water; In some embodiments, the cleaning is performed using an aqueous hydrofluoric acid solution.

[0024] In some embodiments, the source and drain electrodes have a bottom layer of nickel and an upper layer of gold; In some embodiments, the top gate electrode has a bottom layer of platinum and an upper layer of gold; In some embodiments, step S1 specifically uses hydrofluoric acid aqueous solution to remove the self-heating oxide layer on the surface of the silicon substrate, so that the subsequently deposited beryllium oxide heat dissipation layer is in direct contact with the silicon substrate, thereby avoiding thermal resistance due to the presence of silicon dioxide.

[0025] In some embodiments, step S2 specifically includes placing the silicon substrate into a reaction chamber of an atomic layer deposition device, and then introducing precursors diethylberyllium and ozone to react at a reaction temperature of 250-300° C. to obtain a beryllium oxide heat dissipation layer.

[0026] In some embodiments, step S3 specifically includes placing the composite layer obtained in step S2 into a reaction chamber of an atomic layer deposition device, and then introducing precursors trimethylindium and water to react at a reaction temperature of 200-225°C.

[0027] In some embodiments, in step S4, the etching solution is selected from one or more solutions of hydrochloric acid, sulfuric acid, and nitric acid, and the concentration of the etching solution is 0.1 to 1 mol / L. The rate of etching indium oxide with dilute acid is slower, and the etching time can be better controlled to reduce the degree of side etching. The specific concentration and etching time need to be based on the thickness of indium oxide.

[0028] In some embodiments, step S6 specifically includes placing the composite layer obtained in step S5 into a reaction chamber of an atomic layer deposition device, and then introducing precursors tetra(methylethylamine)hafnium and ozone, respectively, at a reaction temperature of 250-300°C.

[0029] In some embodiments, in step S7, the annealing method is rapid thermal annealing, the annealing temperature is 250-300° C., and the annealing time is 1-10 min.

[0030] Example 1 S1, cleaning silicon substrate: select silicon wafers without thermal oxide layer, prepare RCA-1 solution with ammonia: hydrogen peroxide: deionized water = 1:1:5, soak the silicon wafer in 80 ℃ RCA-1 solution for 10 min to remove particles, impurities and other contaminants on the surface, and then rinse it with deionized water; soak the silicon wafer in 6 times diluted buffered oxide etchant (BOE) solution for 30 s to remove the natural oxide layer on the surface, rinse it with deionized water and quickly put it into the atomic layer deposition equipment to prevent oxidation.

[0031] S2, deposition of beryllium oxide heat dissipation layer: using diethyl beryllium as the beryllium source, heating temperature is 45 °C, and ozone is used as the oxygen source. The silicon wafer is placed in the reaction chamber of the atomic layer deposition equipment, the chamber temperature is 250 °C, the pulse time of diethyl beryllium and ozone is 0.5 s and 1 s respectively, the nitrogen purge time is 10 s and 12 s respectively, and 100 cycles are repeated to obtain a beryllium oxide film with a thickness of about 10 nm.

[0032] S3, depositing an indium oxide channel layer: using trimethyl indium as an indium source and water as an oxygen source, both are not heated. The silicon wafer is placed in an atomic layer deposition reaction chamber, the chamber temperature is 225°C, and an indium oxide film with a thickness of about 4 nm is grown.

[0033] S4, determine the channel area: drop electron beam glue methyl methacrylate (PMMA) on the silicon wafer, rotate at 3000 rpm for 60 s, bake on a 180 ℃ hot plate for 90 s, use electron beam exposure equipment (EBL) to expose the area outside the channel, develop in a developer solution of methyl isobutyl ketone (MIBK): isopropyl alcohol (IPA) = 1:3 for 50 s, and then clean with IPA for 30 s; immerse the developed silicon wafer in 0.1 mol / L dilute hydrochloric acid for 8 min, and then clean with a large amount of deionized water; put the cleaned silicon wafer into N-methylpyrrolidone (NMP) at 120 ℃ and heat it to remove the electron beam glue on the channel, and then clean it with IPA.

[0034] S5, preparation of source and drain electrodes: drip PMMA on the silicon wafer, rotate at 3000 rpm for 60 s, bake on a 180℃ hot plate for 90 s, expose the source and drain electrode areas by EBL, develop in a developer with a ratio of MIBK:IPA=1:3 for 50 s, and then clean with IPA for 30 s; place the developed silicon wafer in an electron beam evaporation (EBE) device to deposit 20 nm of nickel and 40 nm of gold respectively; immerse the silicon wafer in 120℃ NMP and heat for 2 hours to strip off the metal on the electron beam glue, and then clean with IPA for 2 min.

[0035] S6, deposition of hafnium oxide gate dielectric layer: using tetra(methylethylamine) hafnium as the hafnium source, heating temperature is 75 °C, and ozone is used as the oxygen source. The silicon wafer is placed in the atomic layer deposition reaction chamber, the chamber temperature is 250 °C, the pulse time of tetra(methylethylamine) hafnium and ozone is 0.5 s and 3 s respectively, the nitrogen purge time is 7 s and 10 s respectively, and 60 cycles are repeated to obtain a hafnium oxide film with a thickness of about 6 nm.

[0036] S7, preparation of top gate electrode: drip PMMA on the silicon wafer, rotate at 3000 rpm for 60 s, bake on a 180℃ hot plate for 90 s, expose the top gate electrode area by EBL, develop in a developer with a ratio of MIBK:IPA=1:3 for 50 s, and then clean with IPA for 30 s; place the developed silicon wafer in EBE to deposit 10 nm of platinum and 25 nm of gold respectively; immerse the silicon wafer in 120℃ NMP to heat and strip the metal on the electron beam glue, and then clean with IPA.

[0037] S8, oxygen annealing: Place the wafer with the top gate prepared in a rapid thermal annealing (RTA) device, evacuate the vacuum and then introduce oxygen, anneal at 300 °C for 1 min, and take it out after cooling to 100 °C.

[0038] Comparative Example 1 A method for preparing a transistor comprises the following steps: S1, cleaning silicon substrate: select a silicon wafer with a 100 nm thermal oxide layer, prepare an RCA-1 solution with a ratio of ammonia water: hydrogen peroxide: deionized water = 1:1:5, soak the silicon wafer in the RCA-1 solution at 80 °C for 10 min to remove particles, impurities and other contaminants on the surface, and then clean it with deionized water.

[0039] S2, depositing an indium oxide channel layer: using trimethyl indium as an indium source and water as an oxygen source, both are not heated. The silicon wafer is placed in an atomic layer deposition reaction chamber, the chamber temperature is 225 °C, and an indium oxide film with a thickness of about 4 nm is grown.

[0040] S3, determine the channel area: drop electron beam glue methyl methacrylate (PMMA) on the silicon wafer, rotate at 3000 rpm for 60 s, bake on a 180 ℃ hot plate for 90 s, use electron beam exposure equipment (EBL) to expose the area outside the channel, develop in a developer solution of methyl isobutyl ketone (MIBK): isopropyl alcohol (IPA) = 1:3 for 50 s, and then clean with IPA for 30 s; immerse the developed silicon wafer in 0.1 mol / L dilute hydrochloric acid for 8 min, and then clean with a large amount of deionized water; put the cleaned silicon wafer into 120 ℃ N-methylpyrrolidone (NMP) to heat to remove the electron beam glue on the channel, and then clean with IPA.

[0041] S4, preparation of source and drain electrodes: drip PMMA on the silicon wafer, rotate at 3000 rpm for 60 s, bake on a 180℃ hot plate for 90 s, expose the source and drain electrode areas by EBL, develop in a developer with a ratio of MIBK:IPA=1:3 for 50 s, and then clean with IPA for 30 s; place the developed silicon wafer in an electron beam evaporation (EBE) device to deposit 20 nm of nickel and 40 nm of gold respectively; immerse the silicon wafer in 120℃ NMP to heat and strip off the metal on the electron beam glue, and then clean with IPA.

[0042] S5, deposition of hafnium oxide gate dielectric layer: using tetra(methylethylamine) hafnium as the hafnium source, heating temperature is 75 °C, and ozone is used as the oxygen source. The silicon wafer is placed in the atomic layer deposition reaction chamber, the chamber temperature is 250 °C, the pulse time of tetra(methylethylamine) hafnium and ozone is 0.5 s and 3 s respectively, the nitrogen purge time is 7 s and 10 s respectively, and 60 cycles are repeated to obtain a hafnium oxide film with a thickness of about 6 nm.

[0043] S6, preparation of top gate electrode: drip PMMA on the silicon wafer, rotate at 3000 rpm for 60 s, bake on a 180℃ hot plate for 90 s, expose the top gate electrode area by EBL, develop in a developer with a ratio of MIBK:IPA=1:3 for 50 s, and then clean with IPA for 30 s; place the developed silicon wafer in EBE to deposit 10 nm of platinum and 25 nm of gold respectively; immerse the silicon wafer in 120℃ NMP to strip off the metal on the electron beam glue, and then clean with IPA.

[0044] S7, oxygen annealing: put the wafer with the top gate prepared into a rapid thermal annealing (RTA) device, introduce oxygen, anneal at 300°C for 1 min, and take it out after cooling to 100°C.

[0045] As can be seen from the above embodiments, the present invention provides a heat dissipation substrate 2 based on atomic layer deposition of beryllium oxide, an atomic layer deposition of indium oxide channel layer 3, an electron beam evaporation deposition of source and drain electrodes 4, an atomic layer deposition of hafnium oxide gate dielectric layer 5, and an electron beam evaporation deposition of top gate electrode 6, and its structure is as follows: Figure 1 described.

[0046] like Figure 2 As shown, the introduction of the beryllium oxide heat sink substrate can make the transistor withstand the source-drain voltage V ds =2 V at I ds = 4 mA source-drain current, while the indium oxide top-gate transistor on the low thermal conductivity substrate silicon oxide (SiO2) (Comparative Example 1) has a current anomaly caused by obvious thermal effects. This shows that the self-heating effect caused by high current can be well solved by introducing a high thermal conductivity beryllium oxide heat dissipation substrate, and the top-gate device preparation process is well compatible with CMOS technology.

[0047] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a transistor with improved self-heating effect, characterized in that: The steps include: S1 selects a silicon substrate, and prepares a beryllium oxide heat dissipation layer on the silicon substrate by atomic layer deposition; S2: performing atomic layer deposition on the beryllium oxide heat dissipation layer to prepare an indium oxide channel layer; S3: etching the two ends of the indium oxide channel layer to obtain a channel region, and the unetched area in the middle is a non-channel region; S4: preparing source and drain electrodes on the channel region; S5: preparing a hafnium oxide gate dielectric layer on the source and drain electrodes and the non-channel region by atomic layer deposition; S6: preparing a top gate electrode on the hafnium oxide gate dielectric layer; S7 annealing the composite layer obtained in step S6 in an oxygen atmosphere.

2. The method for preparing a transistor with improved self-heating effect according to claim 1, characterized in that: In step S1, the substrate is pre-treated. Specifically, the substrate is placed in a mixed solution of ammonia water and hydrogen peroxide and heated, and then washed with deionized water.

3. The method for preparing a transistor with improved self-heating effect according to claim 1, characterized in that: Step S1 specifically includes placing the silicon substrate into a reaction chamber of an atomic layer deposition device, and then introducing precursors diethyl beryllium and ozone to react at a reaction temperature of 250-300° C. to obtain a beryllium oxide heat dissipation layer.

4. The method for preparing a transistor with improved self-heating effect according to claim 1, characterized in that: Step S2 specifically includes placing the composite layer obtained in step S1 into a reaction chamber of an atomic layer deposition device, and then introducing precursors trimethylindium and water to react at a reaction temperature of 200-225°C.

5. The method for preparing a transistor with improved self-heating effect according to claim 1, characterized in that: The etching in step S3 is wet etching, and the etching solution is selected from one or more of hydrochloric acid, nitric acid, and sulfuric acid solutions, and the concentration of the etching solution is 0.1-1 mol / L.

6. The method for preparing a transistor with improved self-heating effect according to claim 1, characterized in that: Step S5 specifically includes placing the composite layer obtained in step S4 into a reaction chamber of an atomic layer deposition device, and then introducing precursors tetra(methylethylamine)hafnium and ozone respectively, with the reaction temperature being 250-300°C.

7. The method for preparing a transistor with improved self-heating effect according to claim 1, characterized in that: In step S7, the annealing method is rapid thermal annealing, the annealing temperature is 250-300°C, the annealing atmosphere is oxygen, and the annealing time is 1-10 min.

8. The transistor prepared by the method for preparing a transistor with improved self-heating effect according to any one of claims 1 to 7, characterized in that: From bottom to top, there are a silicon substrate (1), a beryllium oxide heat dissipation layer (2), and an indium oxide channel layer (3); source and drain electrodes (4) are arranged at both ends of the indium oxide channel layer (3); the source and drain electrodes (4) and the indium oxide channel layer (3) are covered on top by a hafnium oxide gate dielectric layer (5); and the hafnium oxide gate dielectric layer is covered on top by a top gate electrode (6).

9. The transistor according to claim 8, characterized in that The beryllium oxide heat dissipation layer (2) has a thickness of 10 to 20 nm; the indium oxide channel layer (3) has a thickness of 2 to 4 nm; and the hafnium oxide gate dielectric layer (5) has a thickness of 5 to 10 nm.

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