Formation method of semiconductor structure
By removing the protective layer in the semiconductor structure and exposing the gate layer, the problem of abnormal resistance value during the growth of the metal silicide layer is solved, and a more uniform resistance distribution and higher device performance are achieved.
Patent Information
- Application Number
- CN202510096861.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-04-25
AI Technical Summary
The existing metal silicide layer has abnormal resistance during growth, resulting in RC delay or device leakage, affecting device performance.
Before forming the metal silicide layer, the protective layer is removed by a wet etching process to expose the gate layer on the second surface, so that the second surface of the substrate is uniformly heated in the subsequent annealing process to form a metal silicide layer.
The resistance of the metal silicide layer is reduced, and the uniformity of its resistance is improved, thereby improving the performance of the device.
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Figure CN119894066A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a method for forming a semiconductor structure. Background Art
[0002] In the semiconductor process, a metal silicide (Salicide) needs to be provided between the contact hole and the silicon substrate to form an ohmic contact and reduce resistance. The metal silicide is formed by the reaction between the metal and the silicon substrate.
[0003] However, the resistance of existing metal silicides has abnormal growth, which leads to RC delay (ie, RC delay) or device leakage problems, thereby affecting device performance. Summary of the invention
[0004] The technical problem solved by the present invention is how to improve the performance of semiconductor devices.
[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a first surface and a second surface relative to each other, the first surface having a gate structure and source / drain regions located on both sides of the gate structure, the second surface having a gate layer and a protective layer located on the surface of the gate layer; using a wet etching process to remove the protective layer until the gate layer on the second surface is exposed; depositing a metal layer on the gate structure and the first surface of the substrate; and performing an annealing process to react the metal layer with the top of the source / drain region and the top of the gate structure to form a metal silicide layer.
[0006] Optionally, the step of forming the protective layer includes: forming an oxide layer on the second surface; and forming a nitride layer on the oxide layer.
[0007] Optionally, the step of using a wet etching process to remove the protective layer until the gate layer on the second surface is exposed includes: using a wet etching process to remove the nitride layer and the oxide layer until the gate layer on the second surface is exposed.
[0008] Optionally, process parameters of the wet etching process for removing the nitride layer and the oxide layer include: an etching solution of 47% to 51% hydrofluoric acid, and an etching time ranging from 1 minute to 2 minutes.
[0009] Optionally, the metal layer material is nickel-platinum alloy, titanium or cobalt, and the thickness of the metal layer ranges from 80 angstroms to 130 angstroms.
[0010] Optionally, the annealing process includes: performing a first annealing process on the metal layer and the substrate to cause the metal layer and the substrate to react to form a high-resistance metal silicide layer; performing a second annealing process on the high-resistance metal silicide layer to cause a phase change reaction in the high-resistance metal silicide layer to form a metal silicide layer.
[0011] Optionally, the first annealing process uses a rapid thermal annealing furnace, and the process parameters of the first annealing process are: an annealing temperature of 280° C. to 320° C., and an annealing time of 15 seconds to 35 seconds.
[0012] Optionally, the second annealing process uses a rapid thermal annealing furnace, and the process parameters of the second annealing process are: annealing temperature of 390° C. to 430° C., and time of 15 seconds to 25 seconds.
[0013] Optionally, the material of the metal silicide layer is: NiSi containing Pt, and the thickness of the metal silicide layer ranges from 200 angstroms to 400 angstroms.
[0014] Optionally, the resistance of the metal silicide layer ranges from 9 ohms to 12 ohms.
[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0016] The technical solution of the present invention adopts a wet etching process to remove the protective layer until the gate layer on the second surface is exposed before the step of forming the metal silicide layer, so that the second surface of the substrate can be sufficiently and evenly heated and reach the reaction temperature during the subsequent annealing process to form a metal silicide layer, thereby reducing the resistance of the metal silicide layer, improving the uniformity of the resistance of the metal silicide layer, and thus improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;
[0018] Figure 2 It is a schematic diagram of the structure of an annealing furnace;
[0019] Figure 3 It is a graph of the impedance distribution of metal silicide in a semiconductor structure;
[0020] Figures 4 to 10 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention;
[0021] Fig.11 is an impedance distribution diagram of a metal silicide in a semiconductor structure in one embodiment of the present invention;
[0022] Fig.121 is a performance parameter diagram of a metal silicide in a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0023] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.
[0024] Please refer to Figure 1 , Figure 1 The present invention is a schematic diagram of a process of forming a semiconductor structure, comprising: providing a substrate 100, wherein the substrate 100 has a first surface a and a second surface b relative to each other, wherein the first surface a has a gate structure 102 and source / drain regions 103 located on both sides of the gate structure 102, and the second surface b has a protective layer 104; depositing a metal layer (not shown in the figure) on the first surface a; and performing an annealing process to react the metal layer with the substrate 100 to form a metal silicide layer 105.
[0025] Please refer to Figure 2 , Figure 2 It is a schematic diagram of the structure of the annealing furnace, where Figure 1 The metal silicide layer in the annealing furnace is formed by reaction in the annealing furnace, wherein BTM corresponds to the bottom position of the annealing furnace, BC corresponds to the middle and bottom position of the annealing furnace, CTR corresponds to the middle position of the annealing furnace, TC corresponds to the middle and top position of the annealing furnace, and TOP corresponds to the top position of the annealing furnace.
[0026] Please Figure 1 and Figure 2 Based on reference Figure 3 , Figure 3 is Figure 2 The resistance value variation diagram of the metal silicide layer formed at different positions in the annealing furnace, Figure 3 The horizontal axis represents different positions in the annealing furnace. Figure 3 The ordinate is the resistance value of the metal silicide layer. It can be seen from the figure that the resistance values of the metal silicide layer formed at different positions in the annealing furnace fluctuate in a range of 33% to 40%.
[0027] In the above scheme, since the annealing equipment controls the temperature with the second surface b during the process of forming the metal silicide layer, the film layers of the protective layer on the second surface b are greatly different due to the influence of different positions in the annealing furnace, which leads to large fluctuations in the resistance value of the formed metal silicide layer, affecting the performance of the device.
[0028] In order to solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same. Before the step of forming a metal silicide layer, the protective layer is removed to expose the gate layer on the second surface, so that during the subsequent annealing process, the gate layer on the second surface of the substrate can be evenly heated and reach the reaction temperature to form a metal silicide layer, thereby reducing the resistance of the metal silicide layer, improving the uniformity of the resistance of the metal silicide layer, and thereby improving the performance of the device.
[0029] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0030] Please refer to Figure 4 , providing a substrate 300, wherein the substrate 300 has a first surface a and a second surface b relative to each other; forming a first photoresist layer on the first surface a; exposing and developing the first photoresist layer to form a first photoresist layer having an isolation region I pattern; using the first photoresist layer having the isolation region I pattern as a mask, etching the substrate 300 to form an isolation trench 301.
[0031] In some embodiments of the present invention, the substrate 300 includes a device region II and isolation regions I located on both sides of the device region II.
[0032] In some embodiments of the present invention, the substrate 300 is made of silicon.
[0033] In other embodiments, the material of the substrate 300 includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). The multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
[0034] In some embodiments of the present invention, a dry etching process is used to etch the substrate 300 to form an isolation trench 301. The process parameters of the dry etching process are: the chamber pressure is 5 mT to 15 mT, the source power is 350W to 1200W, the bias voltage is 150 V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.
[0035] The isolation trench 301 is used to accommodate an isolation structure 302 to be formed subsequently.
[0036] Please refer to Figure 5 , filling the isolation trench 301 with isolation material to form an isolation structure 302 .
[0037] In some embodiments of the present invention, the isolation trench 301 is filled by a chemical vapor deposition process.
[0038] In some embodiments of the present invention, the isolation structure 302 is made of silicon oxide.
[0039] In other embodiments, the material of the isolation region I is silicon nitride.
[0040] In some embodiments of the present invention, the isolation structure 302 is used to avoid electrical crosstalk between adjacent devices.
[0041] In some embodiments of the present invention, the method further includes: removing the isolation structure 302 above the surface of the substrate 300 through a planarization process.
[0042] In some embodiments of the present invention, the planarization process adopts a chemical mechanical polishing process.
[0043] In this embodiment, by adjusting the process parameters of chemical mechanical polishing, it is possible to ensure that during the polishing process, the isolation structure 302 above the surface of the substrate 300 is removed and stops at a surface flush with the substrate 300 .
[0044] In other embodiments, the thickness of the isolation structure above the surface of the substrate is 0 angstroms to 80 angstroms.
[0045] Please refer to Figure 6 , forming a gate structure 303 on the device region II of the first surface a; performing ion implantation processing in the substrate 300 on both sides of the gate structure 303 to form source / drain regions 304.
[0046] In some embodiments of the present invention, the method for forming the gate structure 303 includes: forming a gate oxide material layer (not shown in the figure) on the first surface a; forming a gate material layer (not shown in the figure) on the gate oxide material layer; forming a second photoresist layer on the gate material layer; exposing and developing the second photoresist layer to form a second photoresist layer having a gate structure 303 pattern; etching the gate material layer and the gate oxide material layer in sequence using the second photoresist layer having the gate structure 303 pattern as a mask to form a gate layer 3032 and a gate oxide layer 3031; forming a first side wall 3033 on the side wall surfaces of the gate layer 3032 and the gate oxide layer 3031; and forming a second side wall 3034 on the side wall of the first side wall 3033.
[0047] In this embodiment, the gate material layer and the gate oxide material layer are formed by a chemical vapor deposition process.
[0048] In this embodiment, the thickness of the gate oxide layer 3031 ranges from 50 angstroms to 70 angstroms, and the thickness of the gate layer 3032 ranges from 950 angstroms to 1050 angstroms.
[0049] In some embodiments of the present invention, the gate oxide layer 3031 is made of silicon nitride or silicon oxide.
[0050] In some embodiments of the present invention, the material of the gate layer 3032 is single crystal silicon or polycrystalline silicon.
[0051] In some embodiments of the present invention, a dry etching process is used to etch away the gate material layer and the gate oxide material layer until the substrate 300 is exposed. The parameters of the dry etching process include: the chamber pressure is 5.5mT to 50mT, the source power is 180W to 1000W, the etching gas contains one or more combinations of CH2F2, Cl2, HBr, He and O2, the gas flow rate is 20sccm to 200sccm, and the etching time is 6s to 40s.
[0052] In this embodiment, the process method for forming the first sidewall 3033 and the second sidewall 3034 is a chemical vapor deposition process or a physical vapor deposition process.
[0053] In this embodiment, the material of the first sidewall 3033 includes one or more of silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide; the material of the second sidewall 3034 includes boron nitride or aluminum nitride.
[0054] In some embodiments of the present invention, the method of forming the source / drain region 304 includes: injecting ions of opposite types into the substrate 300 on both sides of the gate structure 303 through an ion implantation process.
[0055] In this embodiment, the process parameters of the ion implantation process include: the ion doping type in the source / drain region 304 is N-type ion or P-type ion, and the ion doping concentration of the P-type ion is 1E15atom / cm 3 To 3E15atom / cm 3 The N-type ion doping concentration is 0.9E15atom / cm 3 to 2.7E15atom / cm 3 .
[0056] In some embodiments of the present invention, while forming the gate layer 3032 on the first surface a, the method further includes: forming the gate layer 3032 on the second surface b.
[0057] In some embodiments of the present invention, the method further includes: forming a protective layer 305 on the second surface b.
[0058] The step of forming the protection layer 305 and the step of forming the first sidewall 3033 and the second sidewall 3034 are performed simultaneously.
[0059] In some embodiments of the present invention, a thermal oxidation process is used to form the protective layer 305, and the process parameters of the thermal oxidation process are an oxidation temperature range of 500°C to 2000°C, an oxidation time range of 10 seconds to 24 hours, and an oxidation atmosphere of O2, H2O or HCl.
[0060] In a specific embodiment, the step of forming the protection layer 305 includes: forming an oxide layer 3051 on the second surface b; and forming a nitride layer 3052 on the oxide layer 3051 .
[0061] In some embodiments of the present invention, the material of the oxide layer 3051 includes: one or more of silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide; the material of the nitride layer 3052 includes: boron nitride or aluminum nitride.
[0062] Please refer to Figure 7 , using a wet etching process, remove the protection layer 305 until the gate layer 3032 on the second surface b is exposed.
[0063] In some embodiments of the present invention, a wet etching process is used to remove the nitride layer 3052 and the oxide layer 3051 until the gate layer 3032 on the second surface b is exposed.
[0064] In some embodiments of the present invention, process parameters of the wet etching process for removing the nitride layer 3052 and the oxide layer 3051 include: an etching solution of 47% to 51% hydrofluoric acid, and an etching time ranging from 1 minute to 2 minutes.
[0065] In the above scheme, a wet etching process is used to remove the protective layer 305 until the gate layer 3032 on the second surface b is exposed. Compared with the prior art, in the subsequent annealing process, the film layer change of the protective layer 305 on the second surface b will affect the reaction temperature of the metal layer 306 and the substrate 300. In the technical scheme of the present invention, the second surface b of the substrate 300 is exposed, so that in the subsequent annealing process, the second surface b of the substrate 300 can be evenly heated and reach the reaction temperature to form a metal silicide layer 308, thereby reducing the resistance of the metal silicide layer 308, improving the uniformity of the resistance of the metal silicide layer 308, and thus improving the performance of the device.
[0066] Please refer to Figure 8, a metal layer 306 is deposited on the gate structure 303 and the substrate 300 on the first surface a.
[0067] In some embodiments of the present invention, the method for forming the metal layer 306 is a physical vapor deposition process, and the parameters of the physical vapor deposition process are a deposition rate of 350 angstroms per minute to 450 angstroms per minute and a deposition time of 12 seconds to 20 seconds.
[0068] In some embodiments of the present invention, the metal layer 306 is made of nickel-platinum alloy, titanium or cobalt, and the thickness of the metal layer 306 is in a range of 80 angstroms to 130 angstroms.
[0069] In some embodiments of the present invention, after depositing the metal layer 306 , the process further includes: performing an annealing process to allow the metal layer 306 to react with the top of the source / drain region 304 and the top of the gate structure 303 .
[0070] Please refer to Fig. 9 , performing a first annealing process on the metal layer 306 and the substrate 300 so that the metal layer 306 and the substrate 300 react to form a high-resistance metal silicide layer 307 .
[0071] In some embodiments of the present invention, the first annealing process adopts a rapid thermal annealing furnace, and the process parameters of the first annealing process are: annealing temperature is 280° C. to 320° C., and annealing time is 15 seconds to 45 seconds.
[0072] Preferably, the annealing temperature of the first annealing process is 300° C. to form a high-resistance metal silicide layer 307 .
[0073] In this embodiment, after the first annealing process, the method further includes: removing the metal layer 306 that has not reacted with silicon by wet etching to prevent a circuit short caused by bridging.
[0074] Please refer to Fig.10 , performing a second annealing process on the high-resistance metal silicide layer 307 to cause a phase change reaction in the high-resistance metal silicide layer 307 to form a metal silicide layer 308 .
[0075] In some embodiments of the present invention, the second annealing process adopts a rapid thermal annealing furnace, and the process parameters of the second annealing process are: annealing temperature is 390° C. to 430° C., and time is 15 seconds to 45 seconds.
[0076] Preferably, the annealing temperature of the second annealing process is 410° C. to form a low-resistance metal silicide layer 308. In some embodiments of the present invention, the material of the metal silicide layer 308 is: NiSi containing Pt, the thickness of the metal silicide layer 308 ranges from 200 angstroms to 400 angstroms, and the resistance of the metal silicide layer 308 ranges from 9 ohms to 12 ohms.
[0077] In some embodiments of the present invention, the temperature of the first annealing process is lower than the temperature of the second annealing process. In the first annealing process, the annealing temperature is 200°C to 350°C, and the metal layer 306 will only react with the silicon epitaxial layer to form a high-resistance metal silicide layer 308. If the annealing temperature is outside the range of 200°C to 350°C, it will cause problems such as incomplete reaction or over-reaction of the metal layer 306 with the silicon epitaxial layer.
[0078] In some embodiments of the present invention, during the second annealing process, the annealing temperature is 300°C to 600°C, and the high-resistance metal silicide layer 308 is converted into a low-resistance metal silicide layer 308. If the annealing temperature is outside the range of 300°C to 600°C, the high-resistance metal silicide layer 308 may not be completely converted into the low-resistance metal silicide layer 308.
[0079] In the above scheme, two annealing processes are used to form the metal silicide layer 308, avoiding the problem of short circuit caused by generating a low-resistance metal silicide layer 308 through only one annealing process. Specifically, the process temperature under the one annealing process will be very high. In such a high temperature environment, silicon can diffuse along the grain boundaries of the metal silicide layer 308, resulting in excessive growth of the metal silicide layer 308 on the silicon oxide boundary, and subsequent wet etching cannot remove the metal silicide layer 308 on the oxide, causing a short circuit.
[0080] Correspondingly, the present invention also provides a semiconductor structure, including: a substrate 300, the substrate 300 having a first surface a and a second surface b relative to each other, the first surface a having a gate structure 303 and source / drain regions 304 located on both sides of the gate structure 303, and the second surface b having a protective layer 305; a metal silicide layer 308, the metal silicide layer 308 being located on the top of the source / drain region 304 and the top of the gate structure 303.
[0081] In some embodiments of the present invention, the material of the metal silicide layer 308 is: NiSi containing Pt, the thickness of the metal silicide layer 308 ranges from 200 angstroms to 400 angstroms, and the resistance of the metal silicide layer 308 ranges from 9 ohms to 12 ohms.
[0082] In the above solution, the resistance of the metal silicide layer 308 ranges from 9 ohms to 12 ohms. Compared with the resistance of the metal silicide layer 308 in the prior art, the resistance of the metal silicide layer 308 of the present invention is reduced as much as possible, thereby improving the performance of the device.
[0083] Combine the following Fig.11 and Fig.12 The properties of the metal silicide layer are described in detail:
[0084] Please refer to Fig.11 , Fig.11 is the impedance distribution diagram of the metal silicide layer. Specifically, Fig.11 The horizontal axis is the metal silicide layer formed under different conditions. Fig.11 The ordinate is the impedance corresponding to the metal silicide layer, wherein the metal silicide corresponding to TOP1 is: without removing the protective layer, an annealing process is performed, and the metal layer and the top of the source / drain region and the top of the gate structure are reacted at the top of the annealing furnace to form a first metal silicide layer TOP1; the metal silicide corresponding to BTM1 is: without removing the protective layer, an annealing process is performed, and the metal layer and the top of the source / drain region and the top of the gate structure are reacted at the bottom of the annealing furnace to form a second metal silicide layer BTM1.
[0085] As can be seen from the figure, the impedance corresponding to the first metal silicide layer TOP1 is about 15 ohms, and the impedance corresponding to the first metal silicide layer TOP1 is about 12 ohms. The difference between the two impedances is 3 ohms. It can be seen that without removing the protective layer, the impedance difference of the metal silicide layer formed at different positions in the annealing furnace is large and the impedance value itself is also large, which further indicates that the resistance uniformity of the metal silicide layer is poor and the impedance value is high, affecting the performance of the device.
[0086] Please continue to refer to Fig.11 , the metal silicide corresponding to TOP2 is: when the protective layer is removed, an annealing process is performed, and the metal layer and the top of the source / drain region and the top of the gate structure are reacted at the top of the annealing furnace to form a third metal silicide layer TOP2; the metal silicide corresponding to BTM2 is: when the protective layer is removed, an annealing process is performed, and the metal layer and the top of the source / drain region and the top of the gate structure are reacted at the bottom of the annealing furnace to form a fourth metal silicide layer BTM2.
[0087] As can be seen from the figure, the impedance corresponding to the third metal silicide layer TOP2 is approximately 11 ohms, and the impedance corresponding to the fourth metal silicide layer BTM2 is approximately 11 ohms. The difference between the two impedances is 11 ohms. It can be seen that without removing the protective layer, the impedance difference of the metal silicide layers formed at different positions in the annealing furnace is small and the impedance value itself is also small, which improves the uniformity of the resistance of the metal silicide layer and reduces the impedance of the metal silicide layer, thereby improving the performance of the device.
[0088] Please refer to Fig.12 , Fig.12 It is a performance parameter diagram of the metal silicide layer. The performance parameters of the first metal silicide layer formed under the condition of not removing the protective layer and reacting at the top of the annealing furnace include: an impedance average value of 15.19 ohms, and a standard deviation STD of 0.0949; the performance parameters of the second metal silicide layer formed under the condition of not removing the protective layer and reacting at the bottom of the annealing furnace include: an impedance average value of 12.09 ohms, and a standard deviation STD of 0.0658; wherein, the volatility between the impedance of the first metal silicide layer and the impedance of the second metal silicide layer is 20.4%. It can be seen from the above data that the impedance of the metal silicide formed without removing the protective layer is large, and the impedance value itself is also large, and in the annealing furnace, it is further explained that the uniformity of the resistance of the metal silicide layer is poor and the impedance value is high, which affects the performance of the device.
[0089] Please continue to refer to Fig.12 , the performance parameters of the third metal silicide layer formed under the condition of removing the protective layer and reacting at the top of the annealing furnace include: an impedance average value of 11.34 ohms, and a standard deviation STD of 0.1080; the performance parameters of the fourth metal silicide layer formed under the condition of not removing the protective layer and reacting at the bottom of the annealing furnace include: an impedance average value of 11.36 ohms, and a standard deviation STD of 0.0946, wherein the volatility between the impedance of the third metal silicide layer and the impedance of the fourth metal silicide layer is -1.7%. It can be seen from the above data that the impedance of the metal silicide formed when the protective layer is removed is small, and the impedance value itself is also small, and in the annealing furnace, it is further explained that the uniformity of the resistance of the metal silicide layer is improved and the impedance value is reduced, thereby improving the performance of the device.
[0090] To summarize, after removing the protective layer to expose the second surface of the substrate, compared with the prior art, in the subsequent annealing process, the film layer change of the protective layer on the second surface affects the reaction temperature of the metal layer and the substrate. In the technical solution of the present invention, the second surface of the substrate is exposed, so that in the subsequent annealing process, the second surface of the substrate can be evenly heated and reach the reaction temperature to form a metal silicide layer, which reduces the resistance of the metal silicide layer, improves the uniformity of the resistance of the metal silicide layer, and thus improves the performance of the device.
[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a first surface and a second surface opposite to each other, the first surface having a gate structure and source / drain regions located on both sides of the gate structure, and the second surface having a gate layer and a protective layer located on a surface of the gate layer; Using a wet etching process, the protective layer is removed until the gate layer on the second surface is exposed; Depositing a metal layer on the gate structure and the first surface substrate; An annealing process is performed to react the metal layer with the top of the source / drain region and the top of the gate structure to form a metal silicide layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the protective layer include: forming an oxide layer on the second surface; A nitride layer is formed on the oxide layer.
3. The method for forming a semiconductor structure according to claim 2, wherein: The step of removing the protective layer to expose the gate layer on the second surface by a wet etching process comprises: The nitride layer and the oxide layer are removed by a wet etching process until the gate layer on the second surface is exposed.
4. The method for forming a semiconductor structure according to claim 3, wherein: The process parameters of the wet etching process for removing the nitride layer and the oxide layer include: the etching solution is 47% to 51% hydrofluoric acid, and the etching time ranges from 1 minute to 2 minutes.
5. The method for forming a semiconductor structure according to claim 1, wherein: The metal layer material is nickel-platinum alloy, titanium or cobalt, and the thickness of the metal layer ranges from 80 angstroms to 130 angstroms.
6. The method for forming a semiconductor structure according to claim 1, wherein: The steps of the annealing process include: Performing a first annealing process on the metal layer and the substrate to allow the metal layer and the substrate to react and form a high-resistance metal silicide layer; The high-resistance metal silicide layer is subjected to a second annealing process to cause a phase change reaction in the high-resistance metal silicide layer to form a metal silicide layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: The first annealing process adopts a rapid annealing process, and the process parameters of the first annealing process are: annealing temperature is 280° C. to 320° C., and annealing time is 15 seconds to 35 seconds.
8. The method for forming a semiconductor structure according to claim 6, wherein: The second annealing process adopts a rapid annealing process, and the process parameters of the second annealing process are: annealing temperature is 390° C. to 430° C., and time is 15 seconds to 25 seconds.
9. The method for forming a semiconductor structure according to claim 6, wherein: The material of the metal silicide layer is: NiSi containing Pt, and the thickness of the metal silicide layer ranges from 200 angstroms to 400 angstroms.
10. The method for forming a semiconductor structure according to claim 6, wherein: The resistance of the metal silicide layer is in a range of 9 ohms to 12 ohms.