Method and structure for improving ESD (Electro-Static Discharge) performance of metal gate high-voltage device

Abstract

The invention provides a method and a structure for improving ESD (Electro-Static Discharge) performance of a metal gate high-voltage device. The method comprises the following steps: forming a high-voltage P-type potential well on a P-type substrate; forming a first STI region and a second STI region in the high-voltage P-type potential well; forming a first high-voltage region N-type diffusion region in the high-voltage P-type potential well between the first STI region and the second STI region; filling silicon oxide in a region adjacent to the first STI region and a region adjacent to the second STI region, wherein the silicon oxide on one side, far away from the second STI region, of the first STI region and the silicon oxide in the groove on one side, far away from the first STI region, of the second STI region respectively form gate oxide layers; the silicon oxide adjacent to the first STI region forms a first silicon oxide structure, and the silicon oxide adjacent to the second STI region forms a second silicon oxide structure; and forming an IO N-type potential well in the first high-voltage region N-type diffusion region in a lower region between the first silicon oxide structure and the second silicon oxide structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and structure for improving the ESD performance of a metal gate high voltage device. Background Art

[0002] OLED is a current-driven type. The current density of OLED depends on the driving voltage at both ends. The higher the voltage, the greater the current density. During long-term use, the OLED device itself will age, and the relationship between its voltage, current density, and luminous brightness will not always remain constant. The most direct manifestation of OLED device aging is the increase in OLED turn-on voltage and the reduction in luminous efficiency. In order to maintain the same luminous brightness, the OLED current flowing through must be increased, so high-voltage devices are required in OLED to achieve high current functions. In 28HV metal gate technology, low-voltage SRAM and high-voltage drive devices need to be integrated, and high voltage requires thick silicon oxide gates, which affects the subsequent metal gate process. In order to be compatible with metal gate technology, the active area of ​​the high-voltage area will be etched back, and then thick silicon oxide will be grown to make it as consistent as possible with the height of the active area.

[0003] 28nm process high voltage devices use field diffusion process (Field Diffusion Drain) structure, and the source and drain in the symmetrical structure both contain shallow trench isolation structure. When used as high voltage ESD devices, 28HV 32V devices are always turned on first in ESD due to their large size and the largest base resistance of the parasitic BJT of the center finger, limiting the voltage to Vholding. If the trigger voltage 2 (Vtriggr2) is less than the trigger voltage 1 (Vtrigger1), then other fingers will not be able to turn on. In response to this problem, Tai-Hsiang Lai.et.al and others proposed to use the N-type potential well of the original MV device to inject into the drain end of the ESD circuit. Since the ion implantation depth and doping concentration of IONW (N-type potential well doping of medium voltage devices) are greater than the HVNDF (high voltage area N-type diffusion) of the original high voltage device. Advantages: reduce the corresponding trigger voltage, reduce the holding voltage to prevent the occurrence of parasitic latch-up, and increase the total amount of It2. The reason is that the trigger voltage is reduced, mainly due to the transfer of the junction of the original HVNDF (N-type diffusion in the high-voltage area) and HVPW (high-voltage P-well) to IONW (N-type potential well doping of the medium-voltage device) and HVPW (high-voltage P-well), and because the doping concentration of IONW is high, the corresponding junction breakdown voltage is reduced. The holding voltage is increased: The high concentration of IONW reduces the corresponding trigger voltage and prevents the Kirk effect caused by large current, thereby increasing the corresponding holding voltage. Moreover, since the corresponding IONW is deeper, its discharge current can be far away from the original shallow trench isolation, thereby improving its uniformity, and the discharge current capacity is proportional to the width. However, this structure requires the corresponding IONW doping concentration to be higher than HVNDF, but the depth is lower than HVNDF, which cannot achieve the expected results. If the same effect is to be achieved, additional masks and corresponding process development are required. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a structure and method for improving the ESD performance of metal gate high-voltage devices, which is used to solve the problem that in the prior art, high-voltage devices use a field area diffusion process structure. When the device is turned on and ESD is triggered, the Kirk effect caused by the large current causes the junction to be transferred from the high-voltage N-type diffusion area or the high-voltage P-well to the high-voltage P-well or the source and drain N-type doped area, and when the large current passes through the STI corner, the effective area of ​​​​the ESD is reduced.

[0005] To achieve the above objectives and other related objectives, the present invention provides a method for improving the ESD performance of a metal gate high voltage device.

[0006] Step 1: providing a P-type substrate, and forming a high-voltage P-type potential well on the P-type substrate;

[0007] Step 2: forming a first STI region and a second STI region spaced apart from each other in the high-voltage P-type potential well; the high-voltage P-type potential well between the first STI region and the second STI region and the high-voltage P-type potential well on the side of the first STI region and the second STI region away from each other are active regions;

[0008] Step 3, forming a first high-voltage region N-type diffusion region in the high-voltage P-type potential well between the first STI region and the second STI region;

[0009] Step 4: etching the active region between the first STI region and the second STI region to form grooves in a region between the first STI region and the second STI region that is adjacent to the first STI region and in a region that is adjacent to the second STI region; etching the active region of the first STI region on a side away from the second STI region and the active region of the second STI region on a side away from the first STI region to form grooves respectively;

[0010] Step 5, filling the grooves with silicon oxide respectively, wherein the silicon oxide in the groove of the first STI region away from the second STI region and the silicon oxide in the groove of the second STI region away from the first STI region are respectively formed into gate oxide layers; the silicon oxide in the groove between the first STI region and the second STI region adjacent to the first STI region is formed into a first silicon oxide structure, and the silicon oxide in the groove between the first STI region and the second STI region adjacent to the second STI region is formed into a second silicon oxide structure;

[0011] Step six: forming a 10 N-type potential well in the N-type diffusion region of the first high-voltage region in the lower region between the first silicon oxide structure and the second silicon oxide structure.

[0012] Preferably, in step 2, a third STI region and a fourth STI region are also formed in the high-voltage P-type potential well, wherein the third STI region is located on a side of the first STI region away from the second STI region, and the fourth STI region is located on a side of the second STI region away from the first STI region, and the high-voltage P-type potential well between the third STI region and the first STI region and the high-voltage P-type potential well between the second STI region and the fourth STI region are active regions.

[0013] Preferably, in step three, a second high voltage region N-type diffusion region and a first high voltage region P-type diffusion region adjacent to each other are formed in the active region between the third STI region and the first STI region; and a third high voltage region N-type diffusion region and a second high voltage region P-type diffusion region adjacent to each other are formed in the active region between the second STI region and the fourth STI region.

[0014] Preferably, the method further comprises step seven, forming a metal gate on the gate oxide layer.

[0015] Preferably, the method also includes step eight, forming a first SDN region in the N-type diffusion region of the first high voltage region between the first silicon oxide structure and the second silicon oxide structure; forming a second SDN region on the N-type diffusion region of the second high voltage region; forming a third SDN region in the N-type diffusion region of the third high voltage region; forming a first SDP region in the P-type diffusion region of the first high voltage region, and forming a second SDP region in the P-type diffusion region of the second high voltage region.

[0016] The present invention provides a structure for improving the ESD performance of a metal gate high voltage device, comprising at least:

[0017] A P-type substrate, a high-voltage P-type potential well located on the P-type substrate; a first STI region, a second STI region, a third STI region and a fourth STI region located in the high-voltage P-type potential well and spaced from each other; wherein the third STI region is located on a side of the first STI region away from the second STI region, and the fourth STI region is located on a side of the second STI region away from the first STI region; the high-voltage P-type potential well between the first STI region and the second STI region and the high-voltage P-type potential well on the side away from each other of the first STI region and the second STI region are active regions; the high-voltage P-type potential well between the third STI region and the first STI region and the high-voltage P-type potential well between the second STI region and the fourth STI region are active regions; a first high-voltage region N-type diffusion region formed in the high-voltage P-type potential well between the first STI region and the second STI region;

[0018] A gate oxide layer is formed in the active region of the first STI region away from the second STI region and in the active region of the second STI region away from the first STI region; a first silicon oxide structure is formed in the active region between the first STI region and the second STI region and adjacent to the first STI region, and a second silicon oxide structure is formed in the active region between the first STI region and the second STI region and adjacent to the second STI region;

[0019] A 10 N-type potential well is formed in the first high-voltage region N-type diffusion region in the lower region between the first silicon oxide structure and the second silicon oxide structure.

[0020] Preferably, the active area between the third STI region and the first STI region forms a second high voltage region N-type diffusion region and a first high voltage region P-type diffusion region adjacent to each other; the active area between the second STI region and the fourth STI region forms a third high voltage region N-type diffusion region and a second high voltage region P-type diffusion region adjacent to each other.

[0021] Preferably, a metal gate is formed on the gate oxide layer.

[0022] Preferably, the first high-voltage region N-type diffusion region between the first silicon oxide structure and the second silicon oxide structure forms a first SDN region; the second high-voltage region N-type diffusion region forms a second SDN region; the third high-voltage region N-type diffusion region forms a third SDN region; the first high-voltage region P-type diffusion region forms a first SDP region, and the second high-voltage region P-type diffusion region forms a second SDP region.

[0023] As described above, the structure and method of improving the ESD performance of metal gate high voltage devices of the present invention have the following beneficial effects: the present invention introduces IO N-type potential well plasma injection greater than the depth of the active area back-etching area, increases the N-type doping in this area, and is conducive to suppressing the kirk-effect. Since the active area back-etching area can form a current limiting channel, the corresponding current flows along the heavily doped area to reach the high voltage P-type potential well area, thereby preventing the current from gathering at the STI corner and causing the problem of non-uniform conduction. The layout area does not increase, the original STI area is used, and it is compatible with the existing process without adding a new mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shown is a flow chart of a method for improving the ESD performance of a metal gate high voltage device according to the present invention;

[0025] Figure 2 The schematic cross-sectional view shows the structure for improving the ESD performance of a metal gate high voltage device according to the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See also Figure 1 to Figure 2 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0028] The present invention provides a method for improving the ESD performance of a metal gate high voltage device, such as Figure 1 As shown, Figure 1 The flowchart of the method for improving the ESD performance of a metal gate high voltage device according to the present invention is shown, and the method at least comprises:

[0029] Step 1: providing a P-type substrate, and forming a high-voltage P-type potential well on the P-type substrate;

[0030] like Figure 2 As shown, Figure 2 The schematic cross-sectional view of the structure for improving the ESD performance of a metal gate high voltage device of the present invention is shown. The first step is to provide a P-type substrate (P-sub), and form a high voltage P-type potential well (HVPW) on the P-type substrate (P-sub);

[0031] Step 2: forming a first STI region and a second STI region spaced apart from each other in the high-voltage P-type potential well; the high-voltage P-type potential well between the first STI region and the second STI region and the high-voltage P-type potential well on the side of the first STI region and the second STI region away from each other are active regions;

[0032] Furthermore, in step 2 of this embodiment, a third STI region and a fourth STI region are also formed in the high-voltage P-type potential well, wherein the third STI region is located on a side of the first STI region away from the second STI region, and the fourth STI region is located on a side of the second STI region away from the first STI region, and the high-voltage P-type potential well between the third STI region and the first STI region and the high-voltage P-type potential well between the second STI region and the fourth STI region are active regions.

[0033] like Figure 2 As shown, in step 2, a first STI region 01 and a second STI region 02 are formed in the high-voltage P-type potential well (HVPW), which are spaced apart from each other; the high-voltage P-type potential well (HVPW) between the first STI region 01 and the second STI region 02 and the high-voltage P-type potential well (HVPW) on the side of the first STI region 01 and the second STI region 02 away from each other are active regions; a third STI region 03 and a fourth STI region 04 are also formed in the high-voltage P-type potential well (HVPW), wherein the third STI region 03 is located on the side of the first STI region 01 away from the second STI region 02, and the fourth STI region 04 is located on the side of the second STI region 02 away from the first STI region 01, and the high-voltage P-type potential well (HVPW) between the third STI region 03 and the first STI region 01 and the high-voltage P-type potential well (HVPW) between the second STI region 02 and the fourth STI region 04 are active regions.

[0034] Step 3, forming a first high-voltage region N-type diffusion region in the high-voltage P-type potential well between the first STI region and the second STI region;

[0035] Furthermore, in step 3 of this embodiment, a second high-voltage region N-type diffusion region and a first high-voltage region P-type diffusion region adjacent to each other are formed in the active region between the third STI region and the first STI region; and a third high-voltage region N-type diffusion region and a second high-voltage region P-type diffusion region adjacent to each other are formed in the active region between the second STI region and the fourth STI region. Figure 2 As shown, in step three, a first high-voltage region N-type diffusion region (HVNDF) 05 is formed in the high-voltage P-type potential well (HVPW) between the first STI region 01 and the second STI region 02; a second high-voltage region N-type diffusion region (HVNDF) 06 and a first high-voltage region P-type diffusion region (HVPDF) 07 are formed adjacent to each other in the active region between the third STI region 03 and the first STI region 01; and a third high-voltage region N-type diffusion region (HVNDF) 08 and a second high-voltage region P-type diffusion region (HVPDF) 09 are formed adjacent to each other in the active region between the second STI region 02 and the fourth STI region 04.

[0036] Step 4: etching the active region between the first STI region and the second STI region to form grooves in the region between the first STI region and the second STI region adjacent to the first STI region and adjacent to the second STI region; etching the active region of the first STI region away from the second STI region and the active region of the second STI region away from the first STI region to form grooves respectively; Figure 2 As shown, in step 4, the active region between the first STI region 01 and the second STI region 02 is etched to form grooves in the region between the first STI region 01 and the second STI region 02 adjacent to the first STI region 01 and adjacent to the second STI region 02, respectively. Figure 2 The active area of ​​the first STI region 01 away from the second STI region 02 and the active area of ​​the second STI region 02 away from the first STI region 01 are etched to form grooves ( Figure 2 Grooves not shown).

[0037] Step 5, filling the grooves with silicon oxide respectively, wherein the silicon oxide in the groove on the side of the first STI region away from the second STI region and the silicon oxide in the groove on the side of the second STI region away from the first STI region are respectively formed as gate oxide layers; the silicon oxide in the groove between the first STI region and the second STI region adjacent to the first STI region is formed as a first silicon oxide structure, and the silicon oxide in the groove between the first STI region and the second STI region adjacent to the second STI region is formed as a second silicon oxide structure; Figure 2As shown, in step five, silicon oxide is filled in the grooves respectively, wherein the silicon oxide in the groove of the first STI region 01 away from the side of the second STI region 02 and the silicon oxide in the groove of the second STI region 02 away from the side of the first STI region 01 are respectively formed into gate oxide layers, that is, the silicon oxide in the groove of the first STI region 01 away from the side of the second STI region 02 is formed into a gate oxide layer (GOX / HK) 10; the silicon oxide in the groove of the second STI region 02 away from the side of the first STI region 01 is formed into a gate oxide layer (GOX / HK) 11.

[0038] The silicon oxide in the groove between the first STI region 01 and the second STI region 02 and adjacent to the first STI region 01 forms a first silicon oxide structure 12 , and the silicon oxide in the groove between the first STI region 01 and the second STI region 02 and adjacent to the second STI region 02 forms a second silicon oxide structure 13 .

[0039] Step 6: Form a 10 N-type potential well in the N-type diffusion region of the first high-voltage region below the first silicon oxide structure and the second silicon oxide structure. Figure 2 As shown, in step six, an IO N-type potential well (IONW) is formed in the first high voltage region N-type diffusion region 05 in the lower region between the first silicon oxide structure 12 and the second silicon oxide structure 13 .

[0040] like Figure 2 As shown, further, the method of this embodiment also includes step seven, forming a metal gate on the gate oxide layer. Further, the method of this embodiment also includes step eight, forming a first SDN region (SDN) 14 in the first high voltage region N-type diffusion region 05 between the first silicon oxide structure 12 and the second silicon oxide structure 13; forming a second SDN region 15 on the second high voltage region N-type diffusion region 06; forming a third SDN region 16 in the third high voltage region N-type diffusion region 08; forming a first SDP region 17 in the first high voltage region P-type diffusion region 07, and forming a second SDP region 18 in the second high voltage region P-type diffusion region 09.

[0041] The present invention also provides a structure for improving the ESD performance of a metal gate high voltage device, such as Figure 2 As shown, including at least:

[0042] A P-type substrate (P-sub), a high-voltage P-type potential well located on the P-type substrate (P-sub); a first STI region 01, a second STI region 02, a third STI region 03 and a fourth STI region 04 located in the high-voltage P-type potential well (HVPW) and spaced from each other; wherein the third STI region 03 is located on a side of the first STI region 01 away from the second STI region 03, and the fourth STI region 04 is located on a side of the second STI region 02 away from the first STI region 01; all the STI regions between the first STI region 01 and the second STI region 02 are The high-voltage P-type potential well (HVPW) and the high-voltage P-type potential well (HVPW) on the side of the first STI region 01 and the second STI region 02 away from each other are active regions; the high-voltage P-type potential well (HVPW) between the third STI region 03 and the first STI region 01 and the high-voltage P-type potential well (HVPW) between the second STI region 02 and the fourth STI region 04 are active regions; the first high-voltage region N-type diffusion region 05 formed in the high-voltage P-type potential well (HVPW) between the first STI region 01 and the second STI region 02;

[0043] A gate oxide layer (GOX / HK) is formed in the active region of the first STI region 01 away from the second STI region 02 and in the active region of the second STI region 02 away from the first STI region 01; a first silicon oxide structure 12 is formed in the active region of the first STI region between the first STI region and the second STI region and adjacent to the active region of the second STI region; a second silicon oxide structure 13 is formed in the active region of the second STI region between the first STI region and the second STI region;

[0044] An IO N-type potential well (IONW) is formed in the first high-voltage region N-type diffusion region 05 below the first silicon oxide structure 12 and the second silicon oxide structure 13 .

[0045] Furthermore, in this embodiment, the active area between the third STI region 03 and the first STI region 01 forms a second high-voltage region N-type diffusion region 06 and a first high-voltage region P-type diffusion region 07 adjacent to each other; the active area between the second STI region 02 and the fourth STI region 04 forms a third high-voltage region N-type diffusion region 08 and a second high-voltage region P-type diffusion region 09 adjacent to each other.

[0046] Furthermore, a metal gate is formed on the gate oxide layer in this embodiment.

[0047] Furthermore, in the present embodiment, the first high voltage region N-type diffusion region between the first silicon oxide structure and the second silicon oxide structure forms a first SDN region 14; the second high voltage region N-type diffusion region 06 forms a second SDN region 15; the third high voltage region N-type diffusion region 08 forms a third SDN region 16; the first high voltage region P-type diffusion region 07 forms a first SDP region 17, and the second high voltage region N-type diffusion region 09 forms a second SDP region 18.

[0048] The present invention proposes a method of using a high-voltage etch-back area to improve the ESD device problems of existing high-voltage devices. The drain area corresponding to the ESDpad area is partially etched back to form a shallow isolation structure, and the N-type potential well doping (IONW) is injected into the MV (medium voltage) area, so that low-voltage triggering can be achieved and the drift of the junction caused by the Kirk effect under high voltage can be prevented. At the same time, since the high-voltage etch-back area used in this area is lower than the original shallow trench isolation area, the current can be prevented from approaching the corner of the STI. Prevent damage to the large current in the middle area, thereby improving the uniformity of the high-voltage ESD device and the ultimate conduction capability. The structure proposed by the present invention is compatible with existing processes and does not require the development of new processes or the addition of new mask templates.

[0049] In summary, the present invention introduces 10 N-type potential well plasma injection greater than the depth of the active area back-etching area, increases the N-type doping in this area, and is beneficial to suppressing the kirk-effect. Since the active area back-etching area can form a current limiting channel, the corresponding current flows along the heavily doped area to reach the high-voltage P-type potential well area, thereby preventing the current from gathering at the STI corner and causing the problem of non-uniform conduction. The layout area does not increase, the original STI area is used, and it is compatible with the existing process without adding a new mask. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving the ESD performance of a metal gate high voltage device, characterized in that: At least: Step 1: providing a P-type substrate, and forming a high-voltage P-type potential well on the P-type substrate; Step 2: forming a first STI region and a second STI region spaced apart from each other in the high-voltage P-type potential well; the high-voltage P-type potential well between the first STI region and the second STI region and the high-voltage P-type potential well on the side of the first STI region and the second STI region away from each other are active regions; Step 3, forming a first high-voltage region N-type diffusion region in the high-voltage P-type potential well between the first STI region and the second STI region; Step 4: etching the active region between the first STI region and the second STI region to form grooves in a region between the first STI region and the second STI region that is adjacent to the first STI region and in a region that is adjacent to the second STI region; etching the active region of the first STI region on a side away from the second STI region and the active region of the second STI region on a side away from the first STI region to form grooves respectively; Step 5, filling the grooves with silicon oxide respectively, wherein the silicon oxide in the groove on the side of the first STI region away from the second STI region and the silicon oxide in the groove on the side of the second STI region away from the first STI region are respectively formed as gate oxide layers; the silicon oxide in the groove between the first STI region and the second STI region adjacent to the first STI region is formed as a first silicon oxide structure, and the silicon oxide in the groove between the first STI region and the second STI region adjacent to the second STI region is formed as a second silicon oxide structure; Step 6: forming a 10 N-type potential well in the N-type diffusion region of the first high voltage region in the lower region between the first silicon oxide structure and the second silicon oxide structure.

2. The method for improving the ESD performance of a metal gate high voltage device according to claim 1, characterized in that: In step 2, a third STI region and a fourth STI region are also formed in the high-voltage P-type potential well, wherein the third STI region is located on a side of the first STI region away from the second STI region, and the fourth STI region is located on a side of the second STI region away from the first STI region, and the high-voltage P-type potential well between the third STI region and the first STI region and the high-voltage P-type potential well between the second STI region and the fourth STI region are active regions.

3. The method for improving the ESD performance of a metal gate high voltage device according to claim 2, characterized in that: In step three, a second high voltage region N-type diffusion region and a first high voltage region P-type diffusion region are formed adjacent to each other in the active region between the third STI region and the first STI region; a third high voltage region N-type diffusion region and a second high voltage region P-type diffusion region are formed adjacent to each other in the active region between the second STI region and the fourth STI region.

4. The method for improving the ESD performance of a metal gate high voltage device according to claim 3, characterized in that: The method also includes step seven, forming a metal gate on the gate oxide layer.

5. The method for improving the ESD performance of a metal gate high voltage device according to claim 4, characterized in that: The method also includes step eight, forming a first SDN region in the N-type diffusion region of the first high voltage region between the first silicon oxide structure and the second silicon oxide structure; forming a second SDN region on the N-type diffusion region of the second high voltage region; forming a third SDN region in the N-type diffusion region of the third high voltage region; forming a first SDP region in the P-type diffusion region of the first high voltage region, and forming a second SDP region in the P-type diffusion region of the second high voltage region.

6. A structure for improving the ESD performance of a metal gate high voltage device, characterized in that: At least: A P-type substrate, and a high-voltage P-type potential well located on the P-type substrate; The first STI region, the second STI region, the third STI region and the fourth STI region are located in the high-voltage P-type potential well and are spaced from each other; wherein the third STI region is located on the side of the first STI region away from the second STI region, and the fourth STI region is located on the side of the second STI region away from the first STI region; the high-voltage P-type potential well between the first STI region and the second STI region and the high-voltage P-type potential well on the side away from each other of the first STI region and the second STI region are active regions; the high-voltage P-type potential well between the third STI region and the first STI region and the high-voltage P-type potential well between the second STI region and the fourth STI region are active regions; the first high-voltage region N-type diffusion region formed in the high-voltage P-type potential well between the first STI region and the second STI region; A gate oxide layer is formed in the active region of the first STI region away from the second STI region and in the active region of the second STI region away from the first STI region; a first silicon oxide structure is formed in the active region between the first STI region and the second STI region and adjacent to the first STI region, and a second silicon oxide structure is formed in the active region between the first STI region and the second STI region and adjacent to the second STI region; A 10 N-type potential well is formed in the first high-voltage region N-type diffusion region in the lower region between the first silicon oxide structure and the second silicon oxide structure.

7. The structure for improving the ESD performance of a metal gate high voltage device according to claim 6, characterized in that: The active area between the third STI area and the first STI area forms a second high-voltage area N-type diffusion area and a first high-voltage area P-type diffusion area adjacent to each other; the active area between the second STI area and the fourth STI area forms a third high-voltage area N-type diffusion area and a second high-voltage area P-type diffusion area adjacent to each other.

8. The structure for improving the ESD performance of a metal gate high voltage device according to claim 6, characterized in that: A metal gate is formed on the gate oxide layer.

9. The structure for improving the ESD performance of a metal gate high voltage device according to claim 6, characterized in that: The first high-voltage region N-type diffusion region between the first silicon oxide structure and the second silicon oxide structure forms a first SDN region; the second high-voltage region N-type diffusion region forms a second SDN region; the third high-voltage region N-type diffusion region forms a third SDN region; the first high-voltage region P-type diffusion region forms a first SDP region, and the second high-voltage region P-type diffusion region forms a second SDP region.

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