Integrated circuit device with dual power supplies

Abstract

A CMOS device is provided. The CMOS device includes a PMOS transistor and an NMOS transistor. Further, the CMOS device includes a dual power rail having a front side power rail and a back side power rail, both of which are coupled to one of the PMOS transistor or the NMOS transistor. The PMOS and NMOS transistors are in a vertical transistor stack, or side-by-side.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 592,269, filed on October 23, 2023, entitled “Integrated Circuit Device and Method for Forming the Same,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to the field of integrated circuit devices, and more particularly, to integrated circuit devices having dual power supplies. Background Art

[0004] Integrated circuit (IC) devices, chips, and / or blocks may receive power and data signals from one or more external sources (e.g., power supplies and data sources) as part of their operation. Some IC devices may receive power and data signals via front-side (FS) conductive structures. For example, an IC device may include a FS power distribution network (FSPDN) having one or more components formed during a back-end of line (BEOL) process, and the conductive structures for data signals may be on the same side of the IC device as the FSPDN. IC devices may include various transistor structures, including, for example, two-dimensional (2D) planar structures, fin field effect transistors, gate-around transistors, multi-bridge channel FETs (MBCFETs), and gate-around transistors. TM ) and stacked transistors (e.g., three-dimensional (3D) stacked transistors).

[0005] Recently, backside PDN (BSPDN) has also been developed in which the back side of the substrate of an IC device is used as a power distribution network (PDN). For example, a power rail can be used in the BSPDN of an IC device and can be on the side of the substrate opposite to the active components (e.g., transistors) of the IC device. In addition, the conductive structure for data signals can be on the FS of the IC device, so the BSPDN and the conductive structure for data signals can be on opposite sides of the IC device.

[0006] Whether providing FS power or BS power, it may be difficult to control power consumption using a single power supply. Conventional blocks of IC devices may be designed as separate high voltage blocks and low voltage blocks, where each block receives a single voltage (high voltage or low voltage). Therefore, it may be necessary to design and / or separate conventional blocks based on voltage levels. Summary of the invention

[0007] According to some embodiments of the present invention, an integrated circuit device may include a vertical transistor stack including a first transistor having a first conductivity type and a second transistor having a second conductivity type different from the first conductivity type. For example, the device may be a complementary metal oxide semiconductor (CMOS) device, the first transistor may be a p-type metal oxide semiconductor (PMOS) transistor, and the second transistor may be an n-type metal oxide semiconductor (NMOS) transistor. In addition, the CMOS device may include a first power supply and a second power supply coupled to a front side (FS) power rail and a back side (BS) power rail, respectively, wherein both the front side and back side power rails are coupled to the PMOS transistor.

[0008] According to some embodiments of the present invention, an integrated circuit device may include a substrate having a PMOS transistor and an NMOS transistor. The integrated circuit device may include a front side (FS) power rail and a back side (BS) power rail, both coupled to the PMOS transistor. The integrated circuit device may include a FS power supply and a BS power supply, and the FS power supply and the BS power supply are coupled to the PMOS transistor via the FS power rail and the BS power rail, respectively. In addition, the CMOS device may include a controller coupled to the FS power supply and the BS power supply. The controller may be configured to activate the FS power supply when the BS power supply is deactivated, and may also be configured to activate the BS power supply when the FS power supply is deactivated.

[0009] According to some embodiments of the present invention, an integrated circuit device may include a vertical transistor stack including a first transistor and a second transistor. The integrated circuit device may include a first power supply configured to supply a first power signal having a first voltage and a second power supply configured to supply a second power signal having a second voltage higher than the first voltage. Both the first power supply and the second power supply may be coupled to the first transistor. In addition, the CMOS device may include a controller coupled to the first power supply and the second power supply. The controller may be configured to turn on the first power supply when the second power supply is turned off, and may also be configured to turn on the second power supply when the first power supply is turned off. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic block diagram of a device according to some embodiments herein.

[0011] Figure 2 and Figure 3 yes Figure 1 An example cross-sectional view of a standard cell of a device.

[0012] Figure 4A and Figure 4B is shown to turn on / off the coupling to Figure 2 Cross-sectional diagram of the operation of a standard cell power supply. DETAILED DESCRIPTION

[0013] According to an embodiment of the present invention, an IC device is provided, each IC device including a dual power supply that can provide power at both the FS and BS of the IC device. The dual power supply may include a first power supply coupled to the IC device via a first power rail (e.g., via the FS power rail) and a second power supply coupled to the IC device via a second power rail (e.g., via the BS power rail). The power signal provided at the FS may be different from the power signal provided at the BS. For example, the FS may use a relatively narrow power rail to provide a relatively low voltage, and the BS may use a relatively wide power rail to provide a relatively high voltage. This may avoid the need to design and / or separate blocks based on voltage levels. The first power rail and the second power rail configured to provide the corresponding first power signal and the second power signal to the same first transistor may be referred to as a dual power rail in this article.

[0014] In other words, both the first power rail and the second power rail (FS and BS) of the dual power rail can be connected to the same transistor (e.g., a p-channel MOS (PMOS) transistor) at the same time, although the first power rail and the second power rail may not be active at the same time. For example, the FS power rail can be active (i.e., coupled to a power supply that is turned on) while the BS power rail is inactive (i.e., coupled to a power supply that is turned off), or vice versa. In some embodiments, the designer of the IC device can control which power rail is turned on based on the purpose or operation of the IC device or its block. In some embodiments, the controller can select between power supplies (and corresponding power rails) based on functional requirements and / or power consumption settings. Therefore, the dual power rails can advantageously optimize power consumption based on the block purpose (e.g., low power or high power).

[0015] Some examples of embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0016] Figure 1 1 is a schematic block diagram of a device 100 according to some embodiments of the present invention. The device 100 may be referred to as a CMOS device. The device 100 includes an IC 110 having one or more standard cells 112 (e.g., one or more blocks). For example, the standard cell 112 of the IC 110 may be a CMOS standard cell including a PMOS transistor and an n-channel MOS (NMOS) transistor.

[0017] The device 100 also includes a first power supply PS-F (e.g., FS power supply) and a second power supply PS-B (e.g., BS power supply) each coupled to the IC 110. In some embodiments, the first power supply PS-F and the second power supply PS-B can provide different power signals with different voltage levels to the IC 110. As an example, the first power supply PS-F can be configured to provide a first voltage (e.g., 0.4-0.7 volts), and the second power supply PS-B can be configured to provide a second voltage (e.g., 0.7-1.1 volts) relatively higher than the first voltage.

[0018] According to some embodiments, the second voltage may be at least 0.7 volts, and the first voltage may be a non-zero voltage lower than 0.7 volts (e.g., lower than the second voltage). In some embodiments, the second voltage may be higher than 0.7 volts, and the first voltage may be a non-zero voltage not exceeding 0.7 volts (e.g., not exceeding the second voltage).

[0019] Although various examples herein describe a lower voltage power supply (e.g., a first power supply PS-F) and a higher voltage power supply (e.g., a second power supply PS-B), in other examples, the first power supply PS-F and the second power supply PS-B may instead be higher voltage and lower voltage power supplies, respectively. Lower power wiring (e.g., lower power power rails) are typically on the FS, and higher power wiring (e.g., higher power power rails) are typically on the BS because the BS typically has more space for higher power (e.g., wider) wiring. However, the present disclosure is not limited thereto.

[0020] To simplify the description, the first power supply PS-F and the second power supply PS-B are both Figure 1 However, it should be understood that the first power supply PS-F and the second power supply PS-B may be in different planes in the Z direction, with IC 110 coupled between the first power supply PS-F and the second power supply PS-B. Similarly, although in Figure 1 1 and 12. The first power supply PS-F and the second power supply PS-B are shown at different positions along the X direction, but it should be understood that the first power supply PS-F and the second power supply PS-B can be parallel to each other along the X direction. It will also be understood that the first power supply PS-F and the second power supply PS-B can be relatively spaced apart from the IC 110.

[0021] The device 100 also includes a controller 114 coupled to both the first power supply PS-F and the second power supply PS-B. The controller 114 may include one or more microprocessors (not shown) configured to control the operation of the first power supply PS-F and the second power supply PS-B. For example, the controller 114 may include a microprocessor that is configured to turn the first power supply PS-F on or off. The same microprocessor or a different microprocessor in the controller 114 may be configured to turn the second power supply PS-B on or off. Figure 1 As shown, the controller 114 may be external (ie, outside) the IC 110 that includes the standard cell 112 .

[0022] Figure 2 and Figure 3 yes Figure 1 FIG. 1 is an exemplary cross-sectional view of a standard cell 112 .

[0023] Figure 2 A standard cell 112-1 is shown having a PMOS transistor TP and an NMOS transistor TN in a vertical transistor stack VTS in (and / or on) a substrate 202. For example, the PMOS transistor TP may be on top of (i.e., may overlap vertically) the NMOS transistor TN. Thus, an axis extending in the vertical (Z) direction passes through both the PMOS transistor TP and the NMOS transistor TN.

[0024] on the other hand, Figure 3 A standard cell 112-2 is shown in which a PMOS transistor TP and an NMOS transistor TN are arranged side by side in (and / or on) a substrate 302. The PMOS transistor TP may overlap the NMOS transistor TN horizontally. Thus, an axis extending in a lateral (X) direction passes through both the PMOS transistor TP and the NMOS transistor TN. In some embodiments, the side-by-side transistors (e.g., the PMOS transistor TP and the NMOS transistor TN) may be FinFETs. In other embodiments, the side-by-side transistors may be planar transistors.

[0025] Figure 2 and Figure 3 The cross-sectional views in FIG. 1 each show a portion of a PMOS transistor TP and a portion of an NMOS transistor TN. Figure 2 The portion of the PMOS transistor TP shown in FIG. 4 may be a source / drain (S / D) region of the PMOS transistor TP. Figure 2 The portion of the NMOS transistor TN shown in FIG. 1 may be an S / D region of the NMOS transistor TN. Similarly, Figure 3 The portion of the PMOS transistor TP shown in FIG. 1 may be an S / D region of the PMOS transistor TP, and Figure 3 The portion of the NMOS transistor TN shown in FIG. 4 may be an S / D region of the NMOS transistor TN. Furthermore, in some embodiments, the PMOS transistor TP and the NMOS transistor TN may be corresponding FETs (eg, vertically stacked FETs or side-by-side FETs).

[0026] like Figure 2 As shown, the substrate 202 (e.g., semiconductor substrate) of the standard cell 112-1 can be coupled between two power rails of a dual power rail DPR, which includes a first power rail FSR and a second power rail BSR. Therefore, the first power rail FSR and the second power rail BSR are on opposite sides (front and back sides) of the substrate 202 / adjacent to opposite sides (front and back sides) of the substrate 202. For example, the first power rail FSR is on the front side of the substrate 202 (or adjacent to the front side of the substrate 202), and the second power rail BSR is on the back side of the substrate 202 (or adjacent to the back side of the substrate 202).

[0027] The first power rail FSR may be narrower in the X direction than the second power rail BSR. As an example, the width WU of the uppermost surface of the second power rail BSR may be at least two times (or even at least three times) the width WC of the first power rail FSR. In some embodiments, the width WU of the second power rail BSR may be wider than the width WL of the lowermost surface of the second power rail BSR, while the width WC of the first power rail FSR may be constant (i.e., the same for the uppermost and lowermost surfaces of the first power rail FSR). The lowest width (e.g., WL) may be wider (e.g., at least 50% wider, or even at least two times wider) than the constant width (e.g., WC), and the highest width (e.g., WU) may be at least two times wider than the constant width (e.g., WC).

[0028] The first power rail FSR and the second power rail BSR may have different shapes in the XZ plane. For example, the first power rail FSR may be rectangular, while the second power rail BSR may be a non-rectangular quadrilateral, such as a trapezoid. In some embodiments where the PMOS transistor TP is on top of the NMOS transistor TN, the PMOS transistor TP may be closer to the first power rail FSR than to the second power rail BSR.

[0029] In some embodiments, the PMOS transistor TP and the NMOS transistor TN may be of different sizes. For example, the S / D region of the PMOS transistor TP may have a smaller surface area in the XZ plane than the S / D region of the NMOS transistor TN, where the S / D region of the NMOS transistor TN overlaps the S / D region of the PMOS transistor TP (in the Z direction). As an example, the S / D region of the PMOS transistor TP may be narrower (in the X direction) than the S / D region of the NMOS transistor TN.

[0030] The first power rail FSR and the second power rail BSR may be coupled to the PMOS transistor TP. The first power rail FSR and the second power rail BSR may be metal lines / wirings that may be configured to transmit lower voltage power and higher voltage power to the PMOS transistor TP, respectively. The lower voltage power may be a lower drain supply voltage VDD1 (e.g., 0.4-0.7 volts), and the higher voltage power may be a higher drain supply voltage VDD2 (e.g., 0.7-1.1 volts).

[0031] In addition to the first power rail FSR, the FS of the standard cell 112-1 also includes metal lines (e.g., interconnects) FM-1, FM-2, FM-3, FM-4, and FM-5, which may be in the same plane (in the Z direction) as the first power rail FSR. One or more of the metal lines FM (e.g., FM-1 to FM-4) may be signal lines that may be configured to transmit data instead of power. In some embodiments, another one of the metal lines FM (e.g., FM-5) may be configured to transmit power, such as a source-power supply (e.g., negative power supply) voltage VSS. For example, the source-power supply voltage VSS may be zero volts (0V). However, the metal line FM-5 is not limited to transmitting power. Therefore, the metal line FM-5 may be a signal line configured to transmit data instead of power.

[0032] The first power rail FSR can be coupled to the PMOS transistor TP through the FS via 204 and the S / D contact 206. The S / D contact 206 can contact the first S / D region of the PMOS transistor TP. Another S / D contact 208 can also contact the first S / D region of the PMOS transistor TP. The S / D contact 208 can be in the same plane (in the Z direction) as the S / D contact 206 and can be spaced apart (e.g., separated) from the S / D contact 206 in the X direction. The second S / D region of the PMOS transistor TP is not in the Z direction. Figure 2 Instead, it may be parallel to the first S / D region of the PMOS transistor TP in the substrate 202 (or on the substrate 202) at a depth in the Y direction that is different from Figure 2The second power rail BSR may be coupled to the S / D contact 208 through a first via 210 and a second via 212 in the substrate 202 .

[0033] In addition to the second power rail BSR, the BS of the standard cell 112-1 includes metal lines BM-1 and BM-2, which may be power rails. For example, the metal line BM-1 may be configured to transmit a source-supply voltage VSS to the NMOS transistor TN. The metal line BM-2 may be configured to transmit a higher drain-supply voltage VDD2. In addition, the metal lines BM-1 and BM-2 may be in the same plane (in the Z direction) as the second power rail BSR and may overlap each other in the horizontal direction (e.g., the X direction).

[0034] Metal line BM-1 can be coupled to NMOS transistor TN through BS via 214. Metal line BM-2 can be coupled to NMOS transistor TN through BS via 214. Figure 2 One or more through-holes (not shown) are coupled to substrate 202 (e.g., coupled to components thereon). For example, (one or more) through-holes may be in substrate 202 at the same Figure 2 The depths shown are at different depths in the Y direction.

[0035] like Figure 2 As shown, standard cell 112-1 has two parallel cell boundaries CB. In some embodiments, metal line FM-1, first via 210 and second via 212, and second power rail BSR may each be on a first of the cell boundaries CB. In addition, metal lines FM-5 and BM-2 may each be on a second of the cell boundaries CB.

[0036] like Figure 3 As shown, the substrate 302 (e.g., semiconductor substrate) of the standard cell 112-2 can be coupled between two power rails (a first power rail FSR and a second power rail BSR) of the dual power rail DPR. Both power rails (e.g., FSR and BSR) can be coupled to the PMOS transistor TP. The first power rail FSR can be configured to transmit a lower drain power supply voltage VDD1 (e.g., 0.4 volts to 0.7 volts) to the PMOS transistor TP, and the second power rail BSR can be configured to transmit a higher drain power supply voltage VDD2 (e.g., 0.7 volts to 1.1 volts) to the PMOS transistor TP.

[0037] The first power rail FSR can be coupled to the PMOS transistor TP through the FS via 304 and the contact 308. For example, the contact 308 can be an S / D contact that contacts the top portion of the S / D of the PMOS transistor TP. In addition, the second power rail BSR can be coupled to the PMOS transistor TP through the via 312. In some embodiments, the via 312 can contact the bottom portion of the S / D of the PMOS transistor TP.

[0038] In addition to the second power rail BSR, the BS of the standard cell 112-2 includes a BS metal line BM, which may be a power rail. For example, the metal line BM may be configured to transmit a source-supply voltage VSS to the NMOS transistor TN. The BS metal line BM may be coupled to the NMOS transistor TN through a via 316. For example, the via 316 may contact a bottom portion of the NMOS transistor TN. In some embodiments, the vias 312 and 316 may be in the same plane (in the Z direction) with respect to each other. In addition, the PMOS transistor TP and the NMOS transistor TN may be in the same plane (in the Z direction) with respect to each other. As an example, the PMOS transistor TP and the NMOS transistor TN may have coplanar corresponding uppermost surfaces and coplanar corresponding lowermost surfaces. According to some embodiments, the PMOS transistor TP and the NMOS transistor TN may have the same cross-sectional shape and / or surface area in the XZ plane.

[0039] In addition to the first power rail FSR, the FS of the standard cell 112-2 also includes metal lines (e.g., interconnects) FM-1 to FM-5. One or more of the metal lines FM (e.g., FM-1 to FM-4) may be signal lines configured to transmit data instead of power. In some embodiments, another one of the metal lines FM (e.g., FM-5) may be configured to transmit power, such as a source-power supply voltage VSS.

[0040] like Figure 3 As shown, standard cell 112-2 has two parallel cell boundaries CB. In some embodiments, first power rail FSR, FS via 304, and contact 308 may each be on a first of the cell boundaries CB. In addition, metal line FM-5 may be on a second of the cell boundaries CB.

[0041] Metal wires FM-1 to FM-5 can each pass through Figure 3 One or more through-holes not shown in the figure are coupled to the substrate 302 (e.g., coupled to corresponding elements thereon). For example, (one or more) through-holes can be in the substrate 302 at the same Figure 3 The depths shown are at different depths in the Y direction.

[0042] Figure 4A and Figure 4B is shown to turn on / off the coupling to Figure 2 FIG. 1 is a cross-sectional view of the operation of the power supply PS of the standard cell 112 - 1 .

[0043] like Figure 4A As shown, the first power supply PS-F is turned on (i.e., is active), and thus provides power to the PMOS transistor TP. The second power supply PS-B is turned off (i.e., inactive), and thus does not provide power to the PMOS transistor TP. Therefore, lower power (lower voltage) can be provided to the PMOS transistor TP via the first power rail FSR, and no power is provided to the standard cell 112-1 via the second power rail BSR. In addition, no power is provided to the standard cell 112-1 via the metal line BM-2.

[0044] like Figure 4B As shown, the second power supply PS-B is turned on (i.e., is active) and thus provides power to the PMOS transistor TP. The first power supply PS-F is turned off (i.e., inactive) and thus does not provide power to the PMOS transistor TP. Therefore, higher power (higher voltage) is provided to the PMOS transistor TP by the second power rail BSR, and no power is provided to the standard cell 112-1 via the first power rail FSR. In addition, higher power can be provided to the standard cell 112-1 via the metal line BM-2.

[0045] Therefore, although both the first power supply PS-F and the second power supply PS-B are coupled to the PMOS transistor TP at the same time, only one of the first power supply PS-F or the second power supply PS-B is supplying power to the PMOS transistor TP at a given time. Figure 1 ) can activate one of the first power supply PS-F or the second power supply PS-B while the other of the first power supply PS-F or the second power supply PS-B is inactive.

[0046] According to some embodiments of the present invention, the device 100 ( Figure 1 ) can provide many advantages. These advantages can include IC 110 ( Figure 1 ) of the power consumption. This improved control can be achieved by making the dual power rail DPR ( Figure 2 and Figure 3 ) is coupled to two separate power supplies (including a first (FS) power supply PS-F and a second (BS) power supply PS-B ( Figure 1)). The individual power supplies may be configured to supply different power levels and thus may be turned on or off based on power (voltage / performance) targets. As an example, when IC 110 operates in a relatively high performance mode, it may use a higher voltage power supply (e.g., second power supply PS-B). For other operations, such as standard or lower performance operations (or lower power consumption operations), IC 110 may use a lower voltage power supply (e.g., first power supply PS-F).

[0047] At any given time, only one of the two power supplies PS of the standard cell 112 may be enabled. In contrast, conventional power distribution techniques may lack dual power rails DPR and / or separate first power supplies PS-F and second power supplies PS-B, with the first power supply PS-F being configured to provide power signals with different power levels to the same standard cell 112. For example, conventional techniques may use a single power supply for a standard cell (or block) (e.g., may have a power supply only at BS or only at FS), which may make it difficult to provide detailed control over voltage and power consumption.

[0048] The first and second power rails (power rails BSR and FSR) of the dual power rail DPR may be coupled to the CMOS standard cell 112 ( Figure 1 ) of the same transistor (e.g., PMOS transistor TP). Thus, the dual power rail DPR can supply power signals (e.g., first and second power signals) having two different voltage levels (higher and lower) to the standard cell 112 (where only one of the voltage levels is supplied at a given time), thereby eliminating or alleviating the need for voltage level-specific standard cells (e.g., a higher voltage-only standard cell and a separate lower voltage-only standard cell). In addition, in some embodiments, the IC 110 may include a vertical transistor stack VTS ( Figure 2 ) in the PMOS transistor TP and the NMOS transistor TN. In contrast, conventional power distribution techniques may lack a CMOS vertical transistor stack coupled to dual power rails (and / or coupled to separate power supplies).

[0049] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and therefore the present disclosure should not be construed as being limited to the example embodiments set forth herein. On the contrary, these exemplary embodiments are provided to make the present disclosure thorough and complete, and to convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0050] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic diagrams of idealized embodiments and intermediate structures of example embodiments. Thus, variations from the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, the embodiments herein should not be construed as limited to the particular shapes shown herein but are to include deviations in shapes that may result, for example, from manufacturing.

[0051] It should also be noted that in some alternative implementations, the function / action indicated in the flowchart frame of this paper may not occur in the order indicated in the flowchart. For example, two frames shown in succession can actually be performed substantially simultaneously, or frames can sometimes be performed in reverse order, depending on the function / action involved. In addition, the function of a given frame of a flowchart and / or block diagram can be divided into multiple frames and / or the function of two or more frames of a flowchart and / or block diagram can be integrated at least in part. Finally, without departing from the scope of the present invention, other frames can be added / inserted between the frames shown, and / or frames / operations can be omitted.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0053] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or groups thereof.

[0054] It should be understood that when an element is referred to as being "coupled," "connected," or "responsive to" another element or "on another element," it may be directly coupled, connected, or responsive to another element or on another element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly coupled," "directly connected," or "directly responsive to" another element or "directly on" another element, there are no intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be equivalent to the term "and / or."

[0055] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of the present embodiment, the first element may be referred to as the second element.

[0056] For ease of description, spatially relative terms, such as "below", "below", "lower", "above", "upper", etc., may be used herein to describe the relationship between one element or feature as shown in the figure and another one or more elements or features. It should be understood that in addition to the orientation shown in the figure, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as "below" or "below" other elements or features will be oriented as "above" other elements or features. Therefore, the term "below" can cover both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0057] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It should be understood that literally describing and illustrating every combination and subcombination of these embodiments would be overly repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be interpreted as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as the manner and process of making and using them, and should support claims to any such combination or subcombination.

[0058] The subject matter disclosed above is considered to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A complementary metal oxide semiconductor (CMOS) device, comprising: a vertical transistor stack including a first transistor having a first conductivity type and a second transistor having a second conductivity type opposite to the first conductivity type, the first transistor being arranged to overlap the second transistor in a vertical direction; as well as A dual power rail includes a first power rail and a second power rail, the first power rail and the second power rail are located on opposite sides of the first transistor in the vertical direction and are configured to provide corresponding power signals to the first transistor. 2 . The CMOS device according to claim 1 , wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

3. The CMOS device according to claim 1, wherein the first power rail has a first width, and The second power rail has a second width that is wider than the first width.

4. The CMOS device according to claim 1, further comprising a signal line, Wherein the signal line is configured to transmit a data signal and is on a side of the first transistor that is common to the first power rail.

5. The CMOS device according to claim 1, wherein the first power rail is configured to transmit a first power signal having a first voltage, and The second power rail is configured to transmit a second power signal having a second voltage higher than the first voltage.

6. The CMOS device according to claim 1 , further comprising a first front side metal line and a second front side metal line, The first power rail is an inner rail arranged between the first front side metal line and the second front side metal line in a horizontal direction.

7. The CMOS device of claim 1, further comprising a first power supply and a second power supply, the first power supply and the second power supply being coupled to the first transistor via the first power rail and the second power rail, respectively.

8. The CMOS device according to claim 7, wherein the first power supply is configured to provide a first power signal having a first voltage to the first transistor through the first power rail, and The second power supply is configured to provide a second power signal having a second voltage higher than the first voltage to the first transistor through the second power rail.

9. The CMOS device according to claim 7, wherein: The first power source is configured to be active when the second power source is inactive, and Wherein the second power source is configured to be active when the first power source is inactive.

10. The CMOS device of claim 9, further comprising a controller coupled to both the first power supply and the second power supply, The controller is configured as follows: activating the first power source when the second power source is inactive, and The second power source is activated when the first power source is inactive.

11. The CMOS device according to claim 7, wherein the second power rail is the first backside power rail, and The CMOS device further includes a second backside power rail coupled to the second power supply.

12. The CMOS device according to claim 1, wherein the first transistor comprises a first source / drain S / D region and a second S / D region, and Wherein both the first power rail and the second power rail are coupled to a first S / D region of the first transistor.

13. A complementary metal oxide semiconductor (CMOS) device, comprising: A substrate, the substrate comprising a PMOS transistor and an NMOS transistor; a dual power rail coupled to the PMOS transistor and arranged on opposite sides of the PMOS transistor in a vertical direction, a dual power supply coupled to the PMOS transistor via the dual power rails; as well as a controller coupled to the dual power supply, wherein the controller is configured to activate the first power source of the dual power source when the second power source of the dual power source is deactivated, and The controller is further configured to activate the second power source when the first power source is deactivated.

14. The CMOS device according to claim 13, wherein: The PMOS transistor and the NMOS transistor are arranged to overlap each other in the vertical direction.

15. The CMOS device according to claim 13, wherein: The PMOS transistor and the NMOS transistor are arranged to overlap each other in a horizontal direction.

16. The CMOS device according to claim 13, wherein the first power source is configured to supply a first power signal having a first voltage, wherein the second power supply is configured to supply a second power signal having a second voltage higher than the first voltage, and The dual power rails include a first power rail and a second power rail wider than the first power rail.

17. The CMOS device of claim 13, wherein the dual power rails include a first power rail and a second power rail, both of which are coupled to the PMOS transistor and are arranged on the opposite sides of the PMOS transistor in the vertical direction, and The CMOS device further comprises a third power rail, and the third power rail is arranged to overlap with the second power rail in a horizontal direction.

18. A complementary metal oxide semiconductor (CMOS) device, comprising: a vertical transistor stack comprising a first transistor and a second transistor arranged to overlap each other in a vertical direction; a dual power supply coupled to the first transistor and configured to provide a corresponding plurality of power signals to the first transistor; as well as a controller coupled to the dual power supply, wherein the controller is configured to turn on the first power supply of the dual power supply when the second power supply of the dual power supply is turned off, and The controller is further configured to turn on the second power supply when the first power supply is turned off.

19. The CMOS device according to claim 18, further comprising: a first power rail coupled between the first power supply and the first transistor; as well as a second power rail coupled between the second power supply and the first transistor, wherein an uppermost surface of the first power rail is at least twice as wide as an uppermost surface of the second power rail, and Wherein the first power rail and the second power rail are located on opposite sides of the first transistor in the vertical direction.

20. The CMOS device according to claim 19, Wherein the first transistor is closer to the first power rail than to the second power rail.

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