A back-contact solar cell, a preparation method thereof, and a battery module

Abstract

The present invention relates to the technical field of solar cells, and provides a back-contact solar cell, a preparation method thereof, and a battery module. By adjusting the process of the back mask layer, the front edge of the silicon wafer is also coated with a film to form a mask layer with a certain width, and the film thickness gradually decreases from the edge of the silicon wafer inward. This special coating design can achieve the effect that 70% - 90% of the area in the middle of the front of the silicon wafer forms a large pyramid texture, while 10% - 30% of the area at the edge forms a small pyramid texture. As a result, the edge of the large-sized silicon wafer is a small pyramid texture, and the edge maintains a relatively thick silicon wafer state and the pyramid is smoothed, which is beneficial to reducing the fragment rate and improving the production yield in the manufacturing process.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and particularly relates to a back-contact solar cell, a preparation method thereof, and a battery module. Background Art

[0002] When preparing the existing back-contact solar cells, because large pyramid textures are formed on the edges of silicon wafers, sharp channels on their surfaces are prone to form crack initiation sites, which will cause a certain probability of fragmentation. Especially for large-sized silicon wafers, the existing back-contact process is likely to cause a greater deformation of the silicon wafers, resulting in an increase in the fragmentation rate during the manufacturing process, and thus reducing the yield.

[0003] It should be noted that this part of the content of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or well-known technology. Summary of the Invention

[0004] The purpose of the present invention is to provide a back-contact solar cell, a preparation method thereof, and a battery module to solve the technical problem that large-sized silicon wafers are prone to fragmentation, resulting in poor yield.

[0005] To achieve the above purpose, in the first aspect, the present invention provides a back-contact solar cell, including:

[0006] A silicon wafer having a front side and a back side; the front side of the silicon wafer includes a plating-around area and a texturing area, the plating-around area is located at the edge of the silicon wafer, and the texturing area is surrounded by the plating-around area; the thickness of the plating-around area gradually decreases from the edge of the silicon wafer towards the direction close to the texturing area, and after the plating-around area is texturing-cleaned, a first textured surface is formed, and after the texturing area is texturing-cleaned, a second textured surface is formed, and the degree of protrusion of the first textured surface is less than that of the second textured surface;

[0007] A first semiconductor layer disposed on the back side of the silicon wafer, the first semiconductor layer includes a tunneling oxide layer and an N-type doped polysilicon layer formed in sequence on the back side of the silicon wafer; the first semiconductor layer is partitioned by a plurality of second semiconductor opening areas, and the second semiconductor opening areas and the surfaces of the first semiconductor layer around the second semiconductor opening areas are all covered with a second semiconductor layer; a first semiconductor opening area is provided between adjacent second semiconductor opening areas, and the first semiconductor opening area partitions the second semiconductor layer;

[0008] A passivation layer and an antireflection layer, the passivation layer and the antireflection layer are disposed on the front side of the silicon wafer in sequence; wherein, a first surface structure is formed on the surfaces of the passivation layer and the antireflection layer covering the plating-around area, and a second surface structure is formed on the surfaces of the passivation layer and the antireflection layer covering the texturing area, and the protrusion amplitude of the first surface structure is less than that of the second surface structure.

[0009] Optionally, the first textured surface includes a plurality of first pyramid structures, and the second textured surface includes a plurality of second pyramid structures; the height of the first pyramid structures is less than the height of the second pyramid structures.

[0010] Optionally, the structural height of the first pyramid is 0.3 μm to 0.6 μm, and the height of the second pyramid structure is 2 μm to 3 μm.

[0011] Optionally, the ratio of the width of the plating-around area to the width of the textured area is (10% - 30%) : (70% - 90%).

[0012] Optionally, the thickness of the plating-around area gradually decreases from the edge of the silicon wafer towards the textured area, and the inclination angle of the plating-around area on the front side of the silicon wafer is 0.018° to 0.0238°.

[0013] Optionally, the first semiconductor layer includes a tunneling silicon oxide layer and an N-type doped polysilicon layer, the thickness of the tunneling silicon oxide layer is 1 to 2 nm, and the thickness of the N-type doped polysilicon layer is 80 to 140 nm.

[0014] Optionally, the width of the first semiconductor opening area is 400 μm to 600 μm, and the width of the second semiconductor opening area is 200 μm to 300 μm.

[0015] In a second aspect, the present invention provides a method for manufacturing a back-contact solar cell for manufacturing the back-contact solar cell as described in the first aspect, including:

[0016] S1. Provide a double-sided polished silicon wafer;

[0017] S2. Form a first semiconductor layer and a first mask layer on the back side of the silicon wafer, and form a second mask layer in the plating-around area on the front side of the silicon wafer; the thickness of the second mask layer gradually thins from the edge of the front side of the silicon wafer towards the textured area;

[0018] S3. Etch an opening for the first time on the back side of the silicon wafer to form a second semiconductor opening area;

[0019] S4. Texturize and clean the opening areas on the front and back sides of the above silicon wafer;

[0020] Form a first textured surface in the plating-around area on the front side of the silicon wafer through texturizing and cleaning, and form a second textured surface in the textured area in the middle of the silicon wafer; during the entire texturizing time, the reaction time ratio of the plating-around area and the textured area of the silicon wafer in the texturing solution is 1 : (3 - 5);

[0021] S5. Form a second semiconductor layer on the back side of the silicon wafer; the second semiconductor layer is a combination of an intrinsic amorphous silicon layer and a P-type doped amorphous / microcrystalline silicon layer;

[0022] S6. Form a passivation layer and an antireflection layer on the front side of the silicon wafer;

[0023] S7. Etch an opening for the second time on the back side of the silicon wafer to form a first semiconductor opening area;

[0024] S8. Deposit a transparent conductive film layer on the back side of the silicon wafer;

[0025] S9. Etch an opening for the third time on the back side of the silicon wafer to form an insulating groove;

[0026] S10. Form metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

[0027] Optionally, in the step S2, the first semiconductor layer includes a tunneling silicon oxide layer and an N-type doped polysilicon layer, the first mask layer and the second mask layer are both carbon-doped silicon nitride layers, the deposition temperature is 250°C to 400°C, the mass flow rate of silane is 1000 sccm to 2000 sccm, the mass flow rate of ammonia is 300 sccm to 1000 sccm, the mass flow rate of nitrogen is 2000 sccm to 50000 sccm, the mass flow rate of methane is 1000 sccm to 2000 sccm, the pressure is 200 Pa to 400 Pa, the power density of the power supply is 1.25 kW / m² to 3.75 kW / m², and the deposition time is 200 s to 500 s.

[0028] Optionally, in the step S2, the thickness of the first mask layer is 70 nm to 120 nm; the thickness of the second mask layer decreases from 10 nm to 20 nm to 0 to 5 nm in the direction from the edge of the silicon wafer to the texturing area, and the width of the second mask layer is 1 cm to 2 cm.

[0029] Optionally, in step S4, it includes:

[0030] The texturing solution is a mixed solution of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage content of potassium hydroxide or sodium hydroxide is 1% to 5%, and the mass percentage content of the texturing additive is 0.5% to 1%. The texturing time is 10 to 60 minutes, and the texturing temperature is 70°C to 85°C.

[0031] Optionally, in step S4, it further includes:

[0032] During the texturing cleaning process, the first mask layer on the back of the silicon wafer is also removed by the final cleaning solution. The solution used to remove the first mask layer is an HF solution. The mass percentage of HF acid in the HF solution is 0.5% - 5%, the mass percentage of hydrogen peroxide is 3% - 10%, and the mass percentage of deionized water is 95% - 99.5%. The treatment temperature is 20°C - 30°C, and the removal time is 60s - 300s.

[0033] Optionally, in step S5, it includes:

[0034] The second semiconductor layer is formed by plate CVD. The thickness of the intrinsic amorphous silicon layer is 4 - 8nm, the thickness of the P-type doped amorphous / microcrystalline silicon layer is 6 - 12nm, and the deposition temperature of the second semiconductor layer is 150 - 250°C.

[0035] Optionally, in step S6, it includes:

[0036] The passivation layer is a combination of a silicon oxide layer and an aluminum oxide layer. The aluminum oxide layer is formed by atomic layer deposition. The conditions of the atomic layer deposition method include: the process temperature is between 150°C and 180°C, the reaction gases are trimethylaluminum and ozone. In the first stage, the flow rate of trimethylaluminum is 2000 sccm - 5000 sccm, the reaction time is 20s - 40s, and then the chamber and pipelines are purged with nitrogen; then the second stage is carried out. In the second stage, the flow rate of ozone is 3000 sccm - 6000 sccm, the ozone introduction time is 15 - 30s, and then the chamber and pipelines are purged with nitrogen; one cycle reaction is carried out by sequentially performing the first stage and the second stage, and a total of 30 - 80 cycle reactions are carried out.

[0037] In a third aspect, the present invention provides a battery module, including: the back-contact solar cell as described in the first aspect.

[0038] The embodiments of the present invention at least have the following beneficial effects:

[0039] Through the above technical solutions of the present invention, by debugging the process of the back mask layer, a mask layer with a certain width is formed by edge plating on the front edge of the silicon wafer, and the film thickness gradually decreases from the edge of the silicon wafer inward. This special edge plating design can make 70% - 90% of the area in the middle of the front of the silicon wafer form a large pyramid texture surface, while 10% - 30% of the area at the edge of the silicon wafer forms a small pyramid texture surface. As a result, the edge of the large-sized silicon wafer is a small pyramid texture surface, and the edge maintains a relatively thick silicon wafer state and the pyramid is smoothed, which is beneficial to reducing the breakage rate in the manufacturing process and improving the production yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figure 1 Schematic diagram of the structure of a back-contact solar cell provided by an embodiment of the present invention;

[0042] Figure 2 Flowchart of a method for manufacturing a back-contact solar cell provided by an embodiment of the present invention;

[0043] Figure 3 Process structure diagram corresponding to step S3 in a method for manufacturing a back-contact solar cell provided by an embodiment of the present invention;

[0044] Figure 4 Process structure diagram corresponding to step S4 in a method for manufacturing a back-contact solar cell provided by an embodiment of the present invention;

[0045] Figure 5 Process structure diagram after steps S5 to S10 in a method for manufacturing a back-contact solar cell provided by an embodiment of the present invention;

[0046] Figure 6 Electron micrograph of the first pyramid structure of a back-contact solar cell provided by an embodiment of the present invention;

[0047] Figure 7 Electron micrograph of the second pyramid structure of a back-contact solar cell provided by an embodiment of the present invention.

[0048] In the figure: 1 - silicon wafer; 2 - tunneling silicon oxide layer; 3 - N-type doped polysilicon layer; 4.1 - first mask layer; 4.2 - second mask layer; 5 - intrinsic amorphous silicon layer; 6 - P-type doped amorphous / microcrystalline silicon layer; 7 - passivation layer; 7.1 - silicon oxide layer; 7.2 - aluminum oxide layer; 8 - antireflection layer; 9 - transparent conductive film layer; 10 - metal electrode. Specific Embodiments

[0049] The following will clearly and completely describe the technical solutions of the present application in conjunction with the embodiments. Obviously, the described embodiments are some embodiments of the present application, rather than all of them. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0050] Those skilled in the art can understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as the general understanding of those of ordinary skill in the art to which this application belongs. It should also be understood that terms such as those defined in a general dictionary should be understood to have a meaning consistent with their meaning in the context of the prior art, and will not be interpreted in an idealized or overly formal sense unless specifically defined as here.

[0051] Those skilled in the art can understand that, unless specifically stated, the singular forms "a", "an", "the", and "said" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups. The phrase "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0052] In the first aspect, as Figure 1 shown, an embodiment of the present invention provides a back-contact solar cell based on the preparation method of the foregoing embodiment, including:

[0053] A silicon wafer 1 having a front side and a back side; the front side of the silicon wafer 1 includes a plating-around area and a texturing area, the plating-around area is located at the edge of the silicon wafer 1, and the texturing area is surrounded by the plating-around area. Optionally, the ratio of the width of the plating-around area to the width of the texturing area is (10% - 30%):(70% - 90%). For example: the side length of the silicon wafer 1 is 182 mm, the width of the plating-around area is 10 mm, and the width of the texturing area is 162 mm.

[0054] The thickness of the plating-around area gradually decreases from the edge of the silicon wafer 1 towards the direction close to the texturing area. Optionally, the inclination angle of the plating-around area on the front side of the silicon wafer 1 is 0.018° - 0.0238°.

[0055] After the plating-around area is texturized and cleaned, a first texturing surface is formed, and after the texturing area is texturized and cleaned, a second texturing surface is formed. The degree of protrusion of the first texturing surface is less than that of the second texturing surface.

[0056] The first textured surface includes a plurality of first pyramid structures, and the second textured surface includes a plurality of second pyramid structures; the height of the first pyramid structures is less than the height of the second pyramid structures. Among them, the first pyramid structures formed on the front surface of the silicon wafer 1 are large pyramid textured surfaces, which are beneficial to reducing the reflection of sunlight, increasing the incident rate and utilization rate of sunlight, and are beneficial to increasing the current density of the battery. The second pyramid structures on the edge of the silicon wafer 1 are small pyramid textured surfaces, and the edge maintains a relatively thick state of the silicon wafer 1 and the pyramids are rounded, which is beneficial to reducing the breakage rate of the silicon wafer 1 in the manufacturing process and maintaining a certain reflectivity, achieving the effect of balancing optics and process yield.

[0057] Optionally, the height of the first pyramid structures is 0.3 μm to 0.6 μm, and the height of the second pyramid structures is 2 μm to 3 μm.

[0058] The first semiconductor layer is disposed on the back surface of the silicon wafer 1, and the first semiconductor layer includes a tunneling oxide layer 2 and an N-type doped polysilicon layer 3 formed in sequence on the back surface of the silicon wafer 1; the first semiconductor layer is partitioned by a plurality of second semiconductor opening regions, and the surfaces of the second semiconductor opening regions and the first semiconductor layer around the second semiconductor opening regions are all covered with a second semiconductor layer; a first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region partitions the second semiconductor layer.

[0059] The passivation layer 7 and the antireflection layer 8 are disposed on the front surface of the silicon wafer 1 in sequence; among them, a first surface structure with a relatively small protrusion amplitude is formed on the surfaces of the passivation layer 7 and the antireflection layer 8 covering the plating-around region, and a second surface structure with a relatively large protrusion amplitude is formed on the surfaces of the passivation layer 7 and the antireflection layer 8 covering the textured region.

[0060] In the embodiment of the present invention, by forming a plating-around structure with a certain width and a thickness gradually decreasing from the edge of the silicon wafer 1 inward on the front surface of the silicon wafer 1, it is possible to form a large pyramid textured surface on 70% to 90% of the area in the middle of the front surface of the silicon wafer 1 and a small pyramid textured surface on 10% to 30% of the area at the edge of the silicon wafer 1 in the subsequent masking and texturing processes, so that the edge of the large-size silicon wafer 1 is a small pyramid textured surface and the edge maintains a relatively thick state of the silicon wafer 1 and the pyramids are rounded, which is beneficial to reducing the breakage rate in the manufacturing process and improving the production yield.

[0061] Optionally, the first semiconductor layer includes a tunneling oxide layer 2 and an N-type doped polysilicon layer 3, the thickness of the tunneling oxide layer 2 is 1 nm to 2 nm, and the thickness of the N-type doped polysilicon layer 3 is 80 nm to 140 nm.

[0062] Optionally, the width of the first semiconductor opening region is 400 μm to 600 μm, and the width of the second semiconductor opening region is 200 μm to 300 μm.

[0063] Optionally, the passivation layer 7 is a laminated composite structure of a silicon oxide layer 7.1 and an aluminum oxide layer 7.2. The thickness of the silicon oxide layer 7.1 is 1 nm to 2 nm, and the aluminum oxide layer 7.2 is 3 nm to 4 nm.

[0064] Optionally, the antireflection layer 8 is a laminated composite structure of a silicon nitride layer and the silicon oxide layer 7.1. The thickness of the silicon nitride layer is 50 nm to 100 nm, and the thickness of the silicon oxide layer 7.1 is 80 nm to 150 nm.

[0065] In a second aspect, as Figure 2 shown, an embodiment of the present invention provides a method for manufacturing a back-contact solar cell for manufacturing the back-contact solar cell in the foregoing embodiment. The manufacturing method includes the following steps:

[0066] S1. Provide a double-sided polished silicon wafer 1.

[0067] Specifically, the silicon wafer 1 has a front side and a back side, which are polished to achieve this. Among them, the front side refers to the light-receiving surface of the silicon wafer 1, and the back side is the opposite side of the light-receiving surface. In the embodiment of the present invention, it is usually defined that the side close to the silicon wafer 1 is the inside, and the side far from the silicon wafer 1 is the outside. Optionally, the silicon wafer 1 is an N-type single-crystal silicon wafer 1, for example, a Czochralski single-crystal silicon wafer 1 or a cast single-crystal silicon wafer 1.

[0068] S2. Form a first semiconductor layer and a first mask layer 4.1 on the back side of the silicon wafer 1, and form a second mask layer 4.2 in the plating-around region on the front side of the silicon wafer 1; the thickness of the second mask layer 4.2 gradually decreases from the edge of the front side of the silicon wafer 1 towards the texturing region.

[0069] Optionally, the first semiconductor layer includes a tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 3. The thickness of the tunneling silicon oxide layer 2 is 1 - 2 nm, and the thickness of the N-type doped polysilicon layer 3 is 80 - 140 nm. Both the tunneling silicon oxide layer 2 and the N-type doped polysilicon layer 3 are formed by sequential deposition and high-temperature annealing using a tube-type polysilicon deposition furnace. The deposition temperature is 400 - 500 °C. When depositing the tunneling oxide layer, the mass flow rate of nitrous oxide is 8000 - 1200 sccm, the pressure is 100 - 200 Pa, the power of the power supply is 3 - 20 KW, and the time is 20 - 100 seconds; when depositing the N-type doped polysilicon layer 3, the mass flow rate of silane is 1000 - 3000 sccm, the mass flow rate of phosphine (2% PH3 and 98% H2) is 1000 - 2500 sccm, the mass flow rate of hydrogen is 7000 - 9000 sccm, the pressure is 100 - 300 Pa, the power of the power supply is 5 - 20 KW, and the time is 800 - 1300 seconds.

[0070] Both the first mask layer 4.1 and the second mask layer 4.2 are carbon-doped silicon nitride layers, which are deposited using a plate-type PECVD device. The deposition temperature is 250 - 400 °C, the mass flow rate of silane is 1000 - 2000 sccm, the mass flow rate of ammonia is 300 - 1000 sccm, the mass flow rate of nitrogen is 2000 - 50000 sccm, the mass flow rate of methane is 1000 - 2000 sccm, the pressure is 200 - 400 Pa, the pressure is increased by 100% - 200% compared with the existing process, the power density of the power supply is 1.25 kw / m2 - 3.75 kw / m2, the power density is increased by 15% - 40% compared with the existing process, the time is 200 - 500 seconds. By increasing the gas pressure of the deposited film layer and matching the appropriate power, the back surface of the silicon wafer 1 can be uniformly coated, and sufficient overplating can occur at the front edge.

[0071] Optionally, the thickness of the first mask layer 4.1 is 70 - 120 nm. The thickness H of the second mask layer 4.2 gradually decreases from the edge of the silicon wafer 1 inward, decreasing from 10 - 20 nm to 0 - 5 nm. The width W4 of the overplated carbon-doped silicon nitride film layer on the front surface is 1 - 2 cm, specifically as Figure 1 shown, and the corresponding size of the silicon wafer 1 is 18.2 cm × 18.2 cm or 21 cm × 21 cm or a larger size.

[0072] In this embodiment, both the first mask layer 4.1 and the second mask layer 4.2 are prepared by doping silicon nitride with carbon, which is beneficial to improving the denseness of the film layer under low-temperature deposition conditions, improving the etching effect of resistance to strong alkali, and avoiding damage to the underlying polycrystalline layer during the texturing process.

[0073] S3. Etch an opening on the back surface of the silicon wafer 1 for the first time to form a second semiconductor opening region.

[0074] Optionally, as shown in Figure 3 , the first etching opening can be formed by laser or mask etching, as long as the second semiconductor opening region can be formed; wherein, the laser can be ultraviolet or green laser, the pulse width is less than 10 ns, and the width of the formed second semiconductor opening region is 400 - 600 um.

[0075] S4. Texturize and clean the front and back opening regions of the above-mentioned silicon wafer 1.

[0076] Optionally, as shown in Figure 4 , texturize and clean the front and back opening regions of the above-mentioned silicon wafer 1. The texturing solution is a mixed solution of potassium hydroxide or sodium hydroxide, a texturing additive, and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1% - 5%, the mass percentage of the texturing additive is 0.5% - 1%, the texturing time is 10 - 60 minutes, and the texturing temperature is 70°C - 85°C.

[0077] Due to the blockage of the mask layer at the edge of the silicon wafer 1, in the early stage of the reaction, there is a significant difference in the reaction rate between the middle and the edge of the silicon wafer 1 in the texturing solution; as the reaction progresses, after the mask layer of the edge plating is etched and consumed in the texturing solution, the texturing reaction of the edge of the silicon wafer 1 starts. Therefore, after the reaction ends, a first textured surface with a smaller size is formed in the plating area on the front of the silicon wafer 1, and a second textured surface with a larger size is formed in the texturing area in the middle of the silicon wafer 1. The height of the second textured surface (the second pyramid structure) is 2 - 3 um (the electron microscope image of the middle pyramid is as shown in Figure 7 ), and the height of the first textured surface (the first pyramid structure) is 0.3 - 0.6 um (the electron microscope image of the first textured surface is as shown in Figure 6 ); during the entire texturing time, the reaction time ratio of the plating area and the texturing area of the silicon wafer 1 in the texturing solution is 1:(3 - 5).

[0078] During the texturing and cleaning process, the first mask layer 4.1 on the back of the silicon wafer 1 is also removed by the final cleaning solution. The solution used to remove the first mask layer 4.1 is an acid solution such as HF. The mass percentage of HF acid is 0.5% - 5%, the mass percentage of hydrogen peroxide is 3% - 10%; the mass percentage of deionized water is 95% - 99.5%, the treatment temperature is 20°C - 30°C, and the removal time is 60 - 300 s.

[0079] In this embodiment, by adding a certain amount of hydrogen peroxide in the cleaning tank, it is beneficial to make the pyramid texture surface smoother, reduce the formation of sharp concave corners at the edge, further reduce the probability of chip breakage, and improve the yield.

[0080] S5. Form a second semiconductor layer on the back of the silicon wafer 1; the second semiconductor layer is a combination of an intrinsic amorphous silicon layer 5 and a P-type doped amorphous / microcrystalline silicon layer 6.

[0081] Optionally, as Figure 5 shown, the second semiconductor layer is formed by plate CVD. The thickness of the intrinsic amorphous silicon layer 5 is 4 - 8 nm, the thickness of the P-type doped amorphous silicon layer or the P-type microcrystalline silicon layer is 6 - 12 nm, and the deposition temperature of the second semiconductor layer is 150 - 250 °C.

[0082] S6. Form a passivation layer 7 and an antireflection layer 8 on the front side of the silicon wafer 1.

[0083] Optionally, continue to refer to Figure 5 , the passivation layer 7 is a combination of a silicon oxide layer 7.1 and an aluminum oxide layer 7.2. The thickness of the silicon oxide layer 7.1 is 1 - 2 nm, and the thickness of the aluminum oxide layer 7.2 is 3 - 4 nm. Among them, the aluminum oxide is formed by atomic layer deposition. The conditions of the atomic layer deposition method include: the process temperature is between 150 and 180 °C, the reaction gases are trimethylaluminum and ozone. In the first stage, the flow rate of trimethylaluminum is 2000 sccm - 5000 sccm, the reaction time is 20 - 40 s, and then the chamber and pipeline are purged with nitrogen; then the second stage is carried out. In the second stage, the flow rate of ozone is 3000 sccm - 6000 sccm, the time for introducing ozone is 15 - 30 s, and then the chamber and pipeline are purged with nitrogen; the first stage and the second stage are carried out in sequence as a cyclic reaction, and a total of 30 - 80 cyclic reactions are carried out.

[0084] The antireflection layer 8 can be one or a combination of silicon nitride and the silicon oxide layer 7.1. Preferably, it is a combination of silicon nitride and silicon oxide. The thickness of the silicon nitride layer is 50 - 100 nm, and the thickness of the silicon oxide layer 7.1 is 80 - 150 nm.

[0085] S7. Etch an opening on the back side of the silicon wafer 1 for the second time to form a first semiconductor opening area.

[0086] Optionally, the second etching of the opening uses a laser method. The laser can be an ultraviolet or green laser, and the pulse width is less than 10 ns. The width of the formed first semiconductor opening area is 200 - 300 μm.

[0087] S8. Deposit a transparent conductive film layer 9 on the back side of the silicon wafer 1.

[0088] Optionally, a transparent conductive film is deposited on the back side of the silicon wafer 1 by physical vapor deposition technology (PVD) or reactive plasma deposition technology (RPD). The thickness of the transparent conductive film is 40 - 80 nm, and the material of the transparent conductive film can be an indium oxide-based film doped with tin / tungsten / titanium / zinc or a zinc oxide-based film doped with aluminum / boron.

[0089] S9. Etch an opening on the back side of the silicon wafer 1 for the third time to form an insulating groove.

[0090] Optionally, an opening is etched on the back surface of the silicon wafer 1 by means of mask etching or laser to form an insulating groove W3 between the first semiconductor and the second semiconductor. The width of the insulating groove W3 is 20 - 100 μm, and the resistance between the first semiconductor and the second semiconductor after etching is greater than 1 KΩ.

[0091] S10. Metal electrodes 10 are respectively formed at the first semiconductor opening and the second semiconductor opening on the back surface of the silicon wafer 1.

[0092] Optionally, a metal electrode 10 is formed on the surfaces of the first semiconductor opening region W1 and the second semiconductor opening region W2 on the back surface of the silicon wafer 1 by means of screen printing technology.

[0093] In a third aspect, an embodiment of the present invention further provides a battery assembly, including: a back-contact solar cell as described in the foregoing embodiment.

[0094] The embodiments of the present invention are described in detail below. They are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0095] Embodiment 1

[0096] This embodiment provides a back-contact solar cell, including: a silicon wafer 1 having a front surface and a back surface; the front surface of the silicon wafer 1 includes a plating-around region and a texturing region. The plating-around region is located at the edge of the silicon wafer 1, the texturing region is surrounded by the plating-around region, the ratio of the width of the plating-around region to the width of the texturing region is 12%:88%, the thickness of the plating-around region gradually decreases from the edge of the silicon wafer 1 towards the direction close to the texturing region, and the inclination angle of the plating-around region on the front surface of the silicon wafer 1 is 0.021°.

[0097] After the plating-around region is texturing-cleaned, a first textured surface is formed, and after the texturing region is texturing-cleaned, a second textured surface is formed. The degree of protrusion of the first textured surface is less than that of the second textured surface. Specifically, the first textured surface includes a plurality of first pyramid structures, and the second textured surface includes a plurality of second pyramid structures; the height of the first pyramid structure is less than the height of the second pyramid structure.

[0098] The height of the first pyramid structure is 0.5 μm, and the height of the second pyramid structure is 2.5 μm.

[0099] The first semiconductor layer is disposed on the back surface of the silicon wafer 1, and the first semiconductor layer includes a tunneling oxide layer 2 and an N-type doped polysilicon layer 3 that are sequentially formed on the back surface of the silicon wafer 1; the first semiconductor layer is partitioned by a plurality of second semiconductor opening regions, and the second semiconductor layer covers both the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions; a first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region partitions the second semiconductor layer.

[0100] The passivation layer 7 and the antireflection layer 8 are sequentially disposed on the front surface of the silicon wafer 1; wherein, a first surface structure with a relatively small protrusion amplitude is formed on the surfaces of the passivation layer 7 and the antireflection layer 8 covering the plating-around region, and a second surface structure with a relatively large protrusion amplitude is formed on the surfaces of the passivation layer 7 and the antireflection layer 8 covering the texturing region.

[0101] Embodiment 1 of the present invention further provides a method for manufacturing a back-contact solar cell for manufacturing the back-contact solar cell as shown in the embodiment, and the manufacturing method includes:

[0102] S1. Provide a double-sided polished silicon wafer 1;

[0103] S2. Form a first semiconductor layer and a first mask layer 4.1 on the back surface of the silicon wafer 1, and form a second mask layer 4.2 in the plating-around region on the front surface of the silicon wafer 1; the thickness of the second mask layer 4.2 gradually decreases from the edge of the front surface of the silicon wafer 1 towards the texturing region, and the thickness decreases from 15 nm to 2 nm, and the width ratio of the plating-around region to the texturing region of the silicon wafer 1 is 12%:88%;

[0104] S3. Etch openings on the back surface of the silicon wafer 1 for the first time to form second semiconductor opening regions;

[0105] S4. Texturize and clean the opening regions on the front and back surfaces of the silicon wafer 1;

[0106] By texturizing and cleaning, a smaller-sized textured surface effect is formed in the plating-around region on the front surface of the silicon wafer 1, and a larger-sized textured surface effect is formed in the texturing region in the middle of the silicon wafer 1; during the entire texturing time, the reaction time ratio of the plating-around region and the texturing region of the silicon wafer 1 in the texturing solution is 1:4.5;

[0107] S5. Form a second semiconductor layer on the back surface of the silicon wafer 1; the second semiconductor layer is a combination of an intrinsic amorphous silicon layer 5 and a P-type doped amorphous / microcrystalline silicon layer 6;

[0108] S6. Form a passivation layer 7 and an antireflection layer 8 on the front surface of the silicon wafer 1;

[0109] S7. Etch openings on the back surface of the silicon wafer 1 for the second time to form first semiconductor opening regions;

[0110] S8. Deposit a transparent conductive film layer 9 on the back surface of the silicon wafer 1;

[0111] S9. Etch openings on the back surface of the silicon wafer 1 for the third time to form insulating grooves;

[0112] S10. Form metal electrodes 10 at the first semiconductor opening and the second semiconductor opening on the back surface of the silicon wafer 1 respectively.

[0113] Example 2

[0114] Referring to the back-contact solar cell of Example 1, the difference is that the ratio of the width of the plating-around area to the width of the texturing area is 25%:75%.

[0115] Example 3

[0116] Referring to the back-contact solar cell of Example 1, the difference is that the thickness of the plating-around area gradually decreases from the edge of the silicon wafer 1 towards the direction close to the texturing area, and the inclination angle of the plating-around area on the front surface of the silicon wafer 1 is 0.018°.

[0117] Example 4

[0118] Referring to the back-contact solar cell of Example 1, the difference is that the height of the first pyramid structure is 0.6 μm and the height of the second pyramid structure is 2 μm.

[0119] Example 5

[0120] Referring to the preparation method of the back-contact solar cell of Example 1, the difference is that in step S2, the thickness of the second mask layer 4.2 gradually thins from the edge of the front surface of the silicon wafer 1 towards the texturing area, and the thickness decreases from 10 nm to 2 nm.

[0121] Example 6

[0122] Referring to the preparation method of the back-contact solar cell of Example 1, the difference is that in step S2, the reaction time ratio of the plating-around area and the texturing area of the silicon wafer 1 in the texturing solution is 1:3.

[0123] Comparative Example 1

[0124] Referring to the back-contact solar cell of Example 1, the difference is that no plating-around area is set.

[0125] Comparative Example 2

[0126] Referring to the back-contact solar cell of Example 1, the difference is that a plating-around area is set, but the plating-around area and the texturing area are in the same plane and the plating-around area has no inclination angle.

[0127] Comparative Example 3

[0128] Referring to the preparation method of the back-contact solar cell in Embodiment 1, the difference is that the ratio of the width of the plating-around area to the width of the texturing area is 2%:95%.

[0129] Comparative Example 4

[0130] Referring to the back-contact solar cell in Embodiment 1, the difference is that the thickness of the plating-around area gradually decreases from the edge of Wafer 1 towards the texturing area, and the inclination angle of the plating-around area on the front side of Wafer 1 is 0.005°.

[0131] Comparative Example 5

[0132] Referring to the preparation method of the back-contact solar cell in Embodiment 2, the difference is that in Step S2, the thickness of the second mask layer 4.2 gradually thins from the edge on the front side of Wafer 1 towards the texturing area, with the thickness decreasing from 5 nm to 0 nm.

[0133] Comparative Example 6

[0134] Referring to the preparation method of the back-contact solar cell in Embodiment 1, the difference is that in Step S2, the reaction time ratio of the plating-around area and the texturing area of Wafer 1 in the texturing solution is 1:1.2.

[0135] Test Example

[0136] The performance of the back-contact solar cells obtained in the above embodiments and comparative examples was tested, and the specific test results are shown in Table 1.

[0137] Table 1 Test Results of Different Embodiments and Comparative Examples

[0138]

[0139] From the above results, it can be seen that compared with the comparative examples, adopting the embodiment solutions of the present invention can significantly reduce the fragment rate, ensure high performance of the battery, and facilitate the promotion of production. Further, according to Embodiment 1 and Embodiments 2 to 6, adopting the preferred solutions of the present invention can improve the conversion efficiency and is more conducive to reducing the fragment rate.

[0140] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A back contact solar cell, characterized in that: include: A silicon wafer having a front side and a back side; the front side of the silicon wafer includes a plating-around area and a texturing area, the plating-around area is located at the edge of the silicon wafer, and the texturing area is surrounded by the plating-around area; the thickness of the plating-around area gradually decreases from the edge of the silicon wafer toward the texturing area, and the plating-around area is cleaned by texturing to form a first texturing surface, and the texturing area is cleaned by texturing to form a second texturing surface, and the convexity of the first texturing surface is less than that of the second texturing surface; A first semiconductor layer is arranged on the back side of the silicon wafer, the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer sequentially formed on the back side of the silicon wafer; the first semiconductor layer is separated by a plurality of second semiconductor opening regions, the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with the second semiconductor layer; a first semiconductor opening region is provided between adjacent second semiconductor opening regions, the first semiconductor opening region separates the second semiconductor layer; A passivation layer and an anti-reflection layer, wherein the passivation layer and the anti-reflection layer are sequentially arranged on the front side of the silicon wafer; wherein the surfaces of the passivation layer and the anti-reflection layer covering the plating area form a first surface structure, and the surfaces of the passivation layer and the anti-reflection layer covering the texturing area form a second surface structure, and the convex amplitude of the first surface structure is smaller than the convex amplitude of the second surface structure; The first textured surface includes a plurality of first pyramid structures, and the second textured surface includes a plurality of second pyramid structures; the height of the first pyramid structure is smaller than the height of the second pyramid structure.

2. The back contact solar cell according to claim 1, characterized in that: The structure height of the first pyramid is 0.3 μm to 0.6 μm, and the height of the second pyramid structure is 2 μm to 3 μm.

3. The back contact solar cell according to claim 1, characterized in that: The ratio of the width of the plating area to the width of the texturing area is (10%~30%): (70%~90%).

4. The back contact solar cell according to claim 1, characterized in that: The thickness of the plating-around area gradually decreases from the edge of the silicon wafer toward the texturing area, and the inclination angle of the plating-around area on the front side of the silicon wafer is 0.018° to 0.0238°.

5. The back contact solar cell according to claim 1, characterized in that: The first semiconductor layer includes a tunneling silicon oxide layer and an N-type doped polysilicon layer. The thickness of the tunneling silicon oxide layer is 1-2 nm, and the thickness of the N-type doped polysilicon layer is 80-140 nm.

6. The back contact solar cell according to claim 1, characterized in that: The width of the first semiconductor opening region is 400 μm to 600 μm, and the width of the second semiconductor opening region is 200 μm to 300 μm.

7. A method for preparing a back-contact solar cell, for preparing the back-contact solar cell according to any one of claims 1 to 6, characterized in that: include: S1. Provide a double-sided polished silicon wafer; S2, forming a first semiconductor layer and a first mask layer on the back side of the silicon wafer, and forming a second mask layer in the plating area on the front side of the silicon wafer; the thickness of the second mask layer gradually decreases from the edge of the front side of the silicon wafer to the texturing area; S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region; S4, texturing and cleaning the front and back opening areas of the silicon wafer; The first texturing surface is formed in the plating area on the front side of the silicon wafer by texturing cleaning, and the texturing area in the middle of the silicon wafer forms the second texturing surface; during the entire texturing time, the reaction time ratio of the plating area and the texturing area of ​​the silicon wafer in the texturing liquid is 1:(3-5); S5, forming a second semiconductor layer on the back side of the silicon wafer; the second semiconductor layer is a combination of an intrinsic amorphous silicon layer and a P-type doped amorphous / microcrystalline silicon layer; S6, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer; S7, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region; S8, depositing a transparent conductive film layer on the back side of the silicon wafer; S9, etching an opening on the back side of the silicon wafer for the third time to form an insulating groove; S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

8. The method for preparing a back contact solar cell according to claim 7, characterized in that: In step S2, The first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer, the first mask layer and the second mask layer are both carbon-doped silicon nitride layers, the deposition temperature is 250°C~400°C, the mass flow rate of silane is 1000sccm~2000sccm, the mass flow rate of ammonia is 300sccm~1000sccm, the mass flow rate of nitrogen is 2000sccm~50000sccm, the mass flow rate of methane is 1000sccm~2000sccm, the pressure is 200Pa~400Pa, the power density of the power supply is 1.25kW / m2~3.75kW / m2, and the deposition time is 200s~500s.

9. The method for preparing a back-contact solar cell according to claim 7, characterized in that: In step S2, the thickness of the first mask layer is 70nm~120nm; the thickness of the second mask layer decreases from 10nm~20nm to 0~5nm from the edge of the silicon wafer to the texturing area, and the width of the second mask layer is 1cm~2cm.

10. The method for preparing a back contact solar cell according to claim 7, characterized in that: In step S4, it includes: The texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1% to 5%, the mass percentage of the texturing additive is 0.5% to 1%, the texturing time is 10 to 60 minutes, and the texturing temperature is 70°C to 85°C.

11. The method for preparing a back contact solar cell according to claim 7, characterized in that: In step S4, it also includes: During the texturing cleaning process, the first mask layer on the back of the silicon wafer is also removed through the final cleaning solution. The solution used to remove the first mask layer is HF solution. The mass percentage of HF acid in the HF solution is 0.5%~5%, the mass percentage of hydrogen peroxide is 3%~10%, and the mass percentage of deionized water is 95%~99.5%. The processing temperature is 20℃~30℃, and the removal time is 60s~300s.

12. The method for preparing a back contact solar cell according to claim 7, characterized in that: In step S5, it includes: The second semiconductor layer is formed by plate-type CVD, the thickness of the intrinsic amorphous silicon layer is 4-8 nm, the thickness of the P-type doped amorphous / microcrystalline silicon layer is 6-12 nm, and the deposition temperature of the second semiconductor layer is 150-250° C.

13. The method for preparing a back contact solar cell according to claim 7, characterized in that: In step S6, it includes: The passivation layer is a combination of a silicon oxide layer and an aluminum oxide layer, and the aluminum oxide layer is formed by an atomic layer deposition method. The conditions of the atomic layer deposition method include: a process temperature between 150°C and 180°C, reaction gases are trimethylaluminum and ozone, and in the first stage, the flow rate of trimethylaluminum introduced is 2000sccm to 5000sccm, the reaction time is 20s to 40s, and then nitrogen is used to purge the chamber and pipelines; then the second stage is carried out, and the flow rate of ozone introduced in the second stage is 3000sccm to 6000sccm, the ozone introduction time is 15 to 30s, and then nitrogen is used to purge the chamber and pipelines; the first stage and the second stage are carried out in sequence as a cycle reaction, and a total of 30 to 80 cycle reactions are carried out.

14. A battery assembly, characterized in that: include: A back-contact solar cell as claimed in any one of claims 1 to 6.

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